ArmPkg: only attempt buildin MmCommunicationDxe for AArch64
[mirror_edk2.git] / UefiCpuPkg / Application / Cpuid / Cpuid.c
CommitLineData
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1/** @file\r
2 UEFI Application to display CPUID leaf information.\r
3\r
516e3397 4 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
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6\r
7**/\r
8\r
9#include <Uefi.h>\r
10#include <Library/BaseLib.h>\r
11#include <Library/UefiLib.h>\r
01acb06c 12#include <Register/Intel/Cpuid.h>\r
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13\r
14///\r
15/// Macro used to display the value of a bit field in a register returned by CPUID.\r
16///\r
17#define PRINT_BIT_FIELD(Variable, FieldName) \\r
d2ba6f41 18 Print (L"%5a%42a: %x\n", #Variable, #FieldName, Variable.Bits.FieldName);\r
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19\r
20///\r
21/// Macro used to display the value of a register returned by CPUID.\r
22///\r
23#define PRINT_VALUE(Variable, Description) \\r
24 Print (L"%5a%42a: %x\n", #Variable, #Description, Variable);\r
25\r
26///\r
27/// Structure for cache description lookup table\r
28///\r
29typedef struct {\r
30 UINT8 CacheDescriptor;\r
31 CHAR8 *Type;\r
32 CHAR8 *Description;\r
33} CPUID_CACHE_INFO_DESCRIPTION;\r
34\r
35///\r
36/// Cache description lookup table\r
37///\r
38CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {\r
39 { 0x00 , "General" , "Null descriptor, this byte contains no information" },\r
40 { 0x01 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },\r
41 { 0x02 , "TLB" , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },\r
42 { 0x03 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },\r
43 { 0x04 , "TLB" , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },\r
44 { 0x05 , "TLB" , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },\r
45 { 0x06 , "Cache" , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },\r
46 { 0x08 , "Cache" , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
47 { 0x09 , "Cache" , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },\r
48 { 0x0A , "Cache" , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },\r
49 { 0x0B , "TLB" , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },\r
50 { 0x0C , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
51 { 0x0D , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },\r
52 { 0x0E , "Cache" , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },\r
53 { 0x1D , "Cache" , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },\r
54 { 0x21 , "Cache" , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },\r
55 { 0x22 , "Cache" , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },\r
56 { 0x23 , "Cache" , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
57 { 0x24 , "Cache" , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },\r
58 { 0x25 , "Cache" , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
59 { 0x29 , "Cache" , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
60 { 0x2C , "Cache" , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
61 { 0x30 , "Cache" , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
62 { 0x40 , "Cache" , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },\r
63 { 0x41 , "Cache" , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },\r
64 { 0x42 , "Cache" , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },\r
65 { 0x43 , "Cache" , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },\r
66 { 0x44 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },\r
67 { 0x45 , "Cache" , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },\r
68 { 0x46 , "Cache" , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },\r
69 { 0x47 , "Cache" , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },\r
70 { 0x48 , "Cache" , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },\r
71 { 0x49 , "Cache" , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
72 { 0x4A , "Cache" , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },\r
73 { 0x4B , "Cache" , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },\r
74 { 0x4C , "Cache" , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },\r
75 { 0x4D , "Cache" , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },\r
76 { 0x4E , "Cache" , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },\r
77 { 0x4F , "TLB" , "Instruction TLB: 4 KByte pages, 32 entries" },\r
78 { 0x50 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },\r
79 { 0x51 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },\r
80 { 0x52 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },\r
81 { 0x55 , "TLB" , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },\r
82 { 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
83 { 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
84 { 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r
14806d7b 85 { 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
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86 { 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
87 { 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
88 { 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
89 { 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
90 { 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r
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91 { 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },\r
92 { 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },\r
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93 { 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
94 { 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
95 { 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r
96 { 0x6A , "Cache" , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },\r
97 { 0x6B , "Cache" , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },\r
98 { 0x6C , "Cache" , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },\r
99 { 0x6D , "Cache" , "DTLB: 1 GByte pages, fully associative, 16 entries" },\r
100 { 0x70 , "Cache" , "Trace cache: 12 K-uop, 8-way set associative" },\r
101 { 0x71 , "Cache" , "Trace cache: 16 K-uop, 8-way set associative" },\r
102 { 0x72 , "Cache" , "Trace cache: 32 K-uop, 8-way set associative" },\r
103 { 0x76 , "TLB" , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },\r
104 { 0x78 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },\r
105 { 0x79 , "Cache" , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
106 { 0x7A , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
107 { 0x7B , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
108 { 0x7C , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
109 { 0x7D , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },\r
110 { 0x7F , "Cache" , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },\r
111 { 0x80 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },\r
112 { 0x82 , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },\r
113 { 0x83 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },\r
114 { 0x84 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },\r
115 { 0x85 , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },\r
116 { 0x86 , "Cache" , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
117 { 0x87 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
118 { 0xA0 , "DTLB" , "DTLB: 4k pages, fully associative, 32 entries" },\r
119 { 0xB0 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
120 { 0xB1 , "TLB" , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },\r
121 { 0xB2 , "TLB" , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },\r
122 { 0xB3 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
123 { 0xB4 , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },\r
124 { 0xB5 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },\r
125 { 0xB6 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },\r
126 { 0xBA , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },\r
127 { 0xC0 , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },\r
128 { 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
129 { 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
130 { 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r
14806d7b 131 { 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },\r
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132 { 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
133 { 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
134 { 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r
135 { 0xD2 , "Cache" , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },\r
136 { 0xD6 , "Cache" , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
137 { 0xD7 , "Cache" , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },\r
138 { 0xD8 , "Cache" , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },\r
139 { 0xDC , "Cache" , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },\r
140 { 0xDD , "Cache" , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },\r
141 { 0xDE , "Cache" , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },\r
142 { 0xE2 , "Cache" , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },\r
143 { 0xE3 , "Cache" , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
144 { 0xE4 , "Cache" , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },\r
145 { 0xEA , "Cache" , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },\r
146 { 0xEB , "Cache" , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },\r
147 { 0xEC , "Cache" , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },\r
148 { 0xF0 , "Prefetch" , "64-Byte prefetching" },\r
149 { 0xF1 , "Prefetch" , "128-Byte prefetching" },\r
56fbaecb 150 { 0xFE , "General" , "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },\r
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151 { 0xFF , "General" , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }\r
152};\r
153\r
154///\r
155/// The maximum supported CPUID leaf index starting from leaf 0x00000000.\r
156///\r
157UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;\r
158\r
159///\r
160/// The maximum supported CPUID leaf index starting from leaf 0x80000000.\r
161///\r
162UINT32 gMaximumExtendedFunction = CPUID_EXTENDED_FUNCTION;\r
163\r
164/**\r
165 Display CPUID_SIGNATURE leaf.\r
166\r
167**/\r
168VOID\r
169CpuidSignature (\r
170 VOID\r
171 )\r
172{\r
173 UINT32 Eax;\r
174 UINT32 Ebx;\r
175 UINT32 Ecx;\r
176 UINT32 Edx;\r
177 CHAR8 Signature[13];\r
178\r
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179 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
180\r
181 Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);\r
182 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
183 PRINT_VALUE (Eax, MaximumLeaf);\r
184 *(UINT32 *)(Signature + 0) = Ebx;\r
185 *(UINT32 *)(Signature + 4) = Edx;\r
186 *(UINT32 *)(Signature + 8) = Ecx;\r
187 Signature [12] = 0;\r
188 Print (L" Signature = %a\n", Signature);\r
189\r
190 gMaximumBasicFunction = Eax;\r
191}\r
192\r
193/**\r
194 Display CPUID_VERSION_INFO leaf.\r
195\r
196**/\r
197VOID\r
198CpuidVersionInfo (\r
199 VOID\r
200 )\r
201{\r
202 CPUID_VERSION_INFO_EAX Eax;\r
203 CPUID_VERSION_INFO_EBX Ebx;\r
204 CPUID_VERSION_INFO_ECX Ecx;\r
205 CPUID_VERSION_INFO_EDX Edx;\r
5a676df9
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206 UINT32 DisplayFamily;\r
207 UINT32 DisplayModel;\r
25705752 208\r
321ef72c
JF
209 if (CPUID_VERSION_INFO > gMaximumBasicFunction) {\r
210 return;\r
211 }\r
212\r
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213 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
214\r
215 Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);\r
216 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
217\r
218 DisplayFamily = Eax.Bits.FamilyId;\r
219 if (Eax.Bits.FamilyId == 0x0F) {\r
220 DisplayFamily |= (Eax.Bits.ExtendedFamilyId << 4);\r
221 }\r
222\r
223 DisplayModel = Eax.Bits.Model;\r
224 if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {\r
225 DisplayModel |= (Eax.Bits.ExtendedModelId << 4);\r
226 }\r
227\r
228 Print (L" Family = %x Model = %x Stepping = %x\n", DisplayFamily, DisplayModel, Eax.Bits.SteppingId);\r
229\r
230 PRINT_BIT_FIELD (Eax, SteppingId);\r
231 PRINT_BIT_FIELD (Eax, Model);\r
232 PRINT_BIT_FIELD (Eax, FamilyId);\r
233 PRINT_BIT_FIELD (Eax, ProcessorType);\r
234 PRINT_BIT_FIELD (Eax, ExtendedModelId);\r
235 PRINT_BIT_FIELD (Eax, ExtendedFamilyId);\r
236 PRINT_BIT_FIELD (Ebx, BrandIndex);\r
237 PRINT_BIT_FIELD (Ebx, CacheLineSize);\r
238 PRINT_BIT_FIELD (Ebx, MaximumAddressableIdsForLogicalProcessors);\r
239 PRINT_BIT_FIELD (Ebx, InitialLocalApicId);\r
240 PRINT_BIT_FIELD (Ecx, SSE3);\r
241 PRINT_BIT_FIELD (Ecx, PCLMULQDQ);\r
242 PRINT_BIT_FIELD (Ecx, DTES64);\r
243 PRINT_BIT_FIELD (Ecx, MONITOR);\r
244 PRINT_BIT_FIELD (Ecx, DS_CPL);\r
245 PRINT_BIT_FIELD (Ecx, VMX);\r
246 PRINT_BIT_FIELD (Ecx, SMX);\r
247 PRINT_BIT_FIELD (Ecx, TM2);\r
248 PRINT_BIT_FIELD (Ecx, SSSE3);\r
249 PRINT_BIT_FIELD (Ecx, CNXT_ID);\r
250 PRINT_BIT_FIELD (Ecx, SDBG);\r
251 PRINT_BIT_FIELD (Ecx, FMA);\r
252 PRINT_BIT_FIELD (Ecx, CMPXCHG16B);\r
253 PRINT_BIT_FIELD (Ecx, xTPR_Update_Control);\r
254 PRINT_BIT_FIELD (Ecx, PDCM);\r
255 PRINT_BIT_FIELD (Ecx, PCID);\r
256 PRINT_BIT_FIELD (Ecx, DCA);\r
257 PRINT_BIT_FIELD (Ecx, SSE4_1);\r
258 PRINT_BIT_FIELD (Ecx, SSE4_2);\r
259 PRINT_BIT_FIELD (Ecx, x2APIC);\r
260 PRINT_BIT_FIELD (Ecx, MOVBE);\r
261 PRINT_BIT_FIELD (Ecx, POPCNT);\r
262 PRINT_BIT_FIELD (Ecx, TSC_Deadline);\r
263 PRINT_BIT_FIELD (Ecx, AESNI);\r
264 PRINT_BIT_FIELD (Ecx, XSAVE);\r
265 PRINT_BIT_FIELD (Ecx, OSXSAVE);\r
266 PRINT_BIT_FIELD (Ecx, AVX);\r
267 PRINT_BIT_FIELD (Ecx, F16C);\r
268 PRINT_BIT_FIELD (Ecx, RDRAND);\r
269 PRINT_BIT_FIELD (Edx, FPU);\r
270 PRINT_BIT_FIELD (Edx, VME);\r
271 PRINT_BIT_FIELD (Edx, DE);\r
272 PRINT_BIT_FIELD (Edx, PSE);\r
273 PRINT_BIT_FIELD (Edx, TSC);\r
274 PRINT_BIT_FIELD (Edx, MSR);\r
275 PRINT_BIT_FIELD (Edx, PAE);\r
276 PRINT_BIT_FIELD (Edx, MCE);\r
277 PRINT_BIT_FIELD (Edx, CX8);\r
278 PRINT_BIT_FIELD (Edx, APIC);\r
279 PRINT_BIT_FIELD (Edx, SEP);\r
280 PRINT_BIT_FIELD (Edx, MTRR);\r
281 PRINT_BIT_FIELD (Edx, PGE);\r
282 PRINT_BIT_FIELD (Edx, MCA);\r
283 PRINT_BIT_FIELD (Edx, CMOV);\r
284 PRINT_BIT_FIELD (Edx, PAT);\r
285 PRINT_BIT_FIELD (Edx, PSE_36);\r
286 PRINT_BIT_FIELD (Edx, PSN);\r
287 PRINT_BIT_FIELD (Edx, CLFSH);\r
288 PRINT_BIT_FIELD (Edx, DS);\r
289 PRINT_BIT_FIELD (Edx, ACPI);\r
290 PRINT_BIT_FIELD (Edx, MMX);\r
291 PRINT_BIT_FIELD (Edx, FXSR);\r
292 PRINT_BIT_FIELD (Edx, SSE);\r
293 PRINT_BIT_FIELD (Edx, SSE2);\r
294 PRINT_BIT_FIELD (Edx, SS);\r
295 PRINT_BIT_FIELD (Edx, HTT);\r
296 PRINT_BIT_FIELD (Edx, TM);\r
297 PRINT_BIT_FIELD (Edx, PBE);\r
298}\r
299\r
300/**\r
301 Lookup a cache description string from the mCpuidCacheInfoDescription table.\r
302\r
303 @param[in] CacheDescriptor Cache descriptor value from CPUID_CACHE_INFO.\r
304\r
305**/\r
306CPUID_CACHE_INFO_DESCRIPTION *\r
307LookupCacheDescription (\r
308 UINT8 CacheDescriptor\r
309 )\r
310{\r
311 UINTN NumDescriptors;\r
312 UINTN Descriptor;\r
313\r
314 if (CacheDescriptor == 0x00) {\r
315 return NULL;\r
316 }\r
317 NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);\r
318 for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {\r
319 if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {\r
320 return &mCpuidCacheInfoDescription[Descriptor];\r
321 }\r
322 }\r
323 return NULL;\r
324}\r
325\r
326/**\r
327 Display CPUID_CACHE_INFO leaf for each supported cache descriptor.\r
328\r
329**/\r
330VOID\r
331CpuidCacheInfo (\r
332 VOID\r
333 )\r
334{\r
335 CPUID_CACHE_INFO_CACHE_TLB Eax;\r
336 CPUID_CACHE_INFO_CACHE_TLB Ebx;\r
337 CPUID_CACHE_INFO_CACHE_TLB Ecx;\r
338 CPUID_CACHE_INFO_CACHE_TLB Edx;\r
339 UINTN Index;\r
340 CPUID_CACHE_INFO_DESCRIPTION *CacheDescription;\r
341\r
342 if (CPUID_CACHE_INFO > gMaximumBasicFunction) {\r
343 return;\r
344 }\r
345\r
346 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
347\r
348 Print (L"CPUID_CACHE_INFO (Leaf %08x)\n", CPUID_CACHE_INFO);\r
349 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
350 if (Eax.Bits.NotValid == 0) {\r
351 //\r
352 // Process Eax.CacheDescriptor[1..3]. Ignore Eax.CacheDescriptor[0]\r
353 //\r
354 for (Index = 1; Index < 4; Index++) {\r
355 CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);\r
356 if (CacheDescription != NULL) {\r
357 Print (L" %-8a %a\n",\r
358 CacheDescription->Type,\r
359 CacheDescription->Description\r
360 );\r
361 }\r
362 }\r
363 }\r
364 if (Ebx.Bits.NotValid == 0) {\r
365 //\r
366 // Process Ebx.CacheDescriptor[0..3]\r
367 //\r
368 for (Index = 0; Index < 4; Index++) {\r
369 CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);\r
370 if (CacheDescription != NULL) {\r
371 Print (L" %-8a %a\n",\r
372 CacheDescription->Type,\r
373 CacheDescription->Description\r
374 );\r
375 }\r
376 }\r
377 }\r
378 if (Ecx.Bits.NotValid == 0) {\r
379 //\r
380 // Process Ecx.CacheDescriptor[0..3]\r
381 //\r
382 for (Index = 0; Index < 4; Index++) {\r
383 CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);\r
384 if (CacheDescription != NULL) {\r
385 Print (L" %-8a %a\n",\r
386 CacheDescription->Type,\r
387 CacheDescription->Description\r
388 );\r
389 }\r
390 }\r
391 }\r
392 if (Edx.Bits.NotValid == 0) {\r
393 //\r
394 // Process Edx.CacheDescriptor[0..3]\r
395 //\r
396 for (Index = 0; Index < 4; Index++) {\r
397 CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);\r
398 if (CacheDescription != NULL) {\r
399 Print (L" %-8a %a\n",\r
400 CacheDescription->Type,\r
401 CacheDescription->Description\r
402 );\r
403 }\r
404 }\r
405 }\r
406}\r
407\r
408/**\r
409 Display CPUID_SERIAL_NUMBER leaf if it is supported.\r
410\r
411**/\r
412VOID\r
413CpuidSerialNumber (\r
414 VOID\r
415 )\r
416{\r
417 CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
418 UINT32 Ecx;\r
419 UINT32 Edx;\r
420\r
421 Print (L"CPUID_SERIAL_NUMBER (Leaf %08x)\n", CPUID_SERIAL_NUMBER);\r
422\r
423 if (CPUID_SERIAL_NUMBER > gMaximumBasicFunction) {\r
424 return;\r
425 }\r
426\r
427 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
428 if (VersionInfoEdx.Bits.PSN == 0) {\r
429 Print (L" Not Supported\n");\r
430 return;\r
431 }\r
432\r
433 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r
434 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx, Edx);\r
435 Print (L" Processor Serial Number = %08x%08x%08x\n", 0, Edx, Ecx);\r
436}\r
437\r
438/**\r
439 Display CPUID_CACHE_PARAMS for all supported sub-leafs.\r
440\r
441**/\r
442VOID\r
443CpuidCacheParams (\r
444 VOID\r
445 )\r
446{\r
447 UINT32 CacheLevel;\r
448 CPUID_CACHE_PARAMS_EAX Eax;\r
449 CPUID_CACHE_PARAMS_EBX Ebx;\r
450 UINT32 Ecx;\r
451 CPUID_CACHE_PARAMS_EDX Edx;\r
452\r
453 if (CPUID_CACHE_PARAMS > gMaximumBasicFunction) {\r
454 return;\r
455 }\r
456\r
457 CacheLevel = 0;\r
458 do {\r
459 AsmCpuidEx (\r
460 CPUID_CACHE_PARAMS, CacheLevel,\r
461 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
462 );\r
463 if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {\r
464 Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);\r
465 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx, Edx.Uint32);\r
466 PRINT_BIT_FIELD (Eax, CacheType);\r
467 PRINT_BIT_FIELD (Eax, CacheLevel);\r
468 PRINT_BIT_FIELD (Eax, SelfInitializingCache);\r
469 PRINT_BIT_FIELD (Eax, FullyAssociativeCache);\r
470 PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForLogicalProcessors);\r
471 PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForProcessorCores);\r
472 PRINT_BIT_FIELD (Ebx, LineSize);\r
473 PRINT_BIT_FIELD (Ebx, LinePartitions);\r
474 PRINT_BIT_FIELD (Ebx, Ways);\r
475 PRINT_VALUE (Ecx, NumberOfSets);\r
476 PRINT_BIT_FIELD (Edx, Invalidate);\r
477 PRINT_BIT_FIELD (Edx, CacheInclusiveness);\r
478 PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);\r
479 }\r
480 CacheLevel++;\r
481 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
482}\r
483\r
484/**\r
485 Display CPUID_MONITOR_MWAIT leaf.\r
486\r
487**/\r
488VOID\r
489CpuidMonitorMwait (\r
490 VOID\r
491 )\r
492{\r
493 CPUID_MONITOR_MWAIT_EAX Eax;\r
494 CPUID_MONITOR_MWAIT_EBX Ebx;\r
495 CPUID_MONITOR_MWAIT_ECX Ecx;\r
496 CPUID_MONITOR_MWAIT_EDX Edx;\r
497\r
498 if (CPUID_MONITOR_MWAIT > gMaximumBasicFunction) {\r
499 return;\r
500 }\r
501\r
502 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
503\r
504 Print (L"CPUID_MONITOR_MWAIT (Leaf %08x)\n", CPUID_MONITOR_MWAIT);\r
505 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
506\r
507 PRINT_BIT_FIELD (Eax, SmallestMonitorLineSize);\r
508 PRINT_BIT_FIELD (Ebx, LargestMonitorLineSize);\r
509 PRINT_BIT_FIELD (Ecx, ExtensionsSupported);\r
510 PRINT_BIT_FIELD (Ecx, InterruptAsBreak);\r
511 PRINT_BIT_FIELD (Edx, C0States);\r
512 PRINT_BIT_FIELD (Edx, C1States);\r
513 PRINT_BIT_FIELD (Edx, C2States);\r
514 PRINT_BIT_FIELD (Edx, C3States);\r
515 PRINT_BIT_FIELD (Edx, C4States);\r
516 PRINT_BIT_FIELD (Edx, C5States);\r
517 PRINT_BIT_FIELD (Edx, C6States);\r
518 PRINT_BIT_FIELD (Edx, C7States);\r
519}\r
520\r
521/**\r
522 Display CPUID_THERMAL_POWER_MANAGEMENT leaf.\r
523\r
524**/\r
525VOID\r
526CpuidThermalPowerManagement (\r
527 VOID\r
528 )\r
529{\r
530 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r
531 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r
532 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r
533\r
534 if (CPUID_THERMAL_POWER_MANAGEMENT > gMaximumBasicFunction) {\r
535 return;\r
536 }\r
537\r
538 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
539\r
540 Print (L"CPUID_THERMAL_POWER_MANAGEMENT (Leaf %08x)\n", CPUID_THERMAL_POWER_MANAGEMENT);\r
541 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);\r
542\r
543 PRINT_BIT_FIELD (Eax, DigitalTemperatureSensor);\r
544 PRINT_BIT_FIELD (Eax, TurboBoostTechnology);\r
545 PRINT_BIT_FIELD (Eax, ARAT);\r
546 PRINT_BIT_FIELD (Eax, PLN);\r
547 PRINT_BIT_FIELD (Eax, ECMD);\r
548 PRINT_BIT_FIELD (Eax, PTM);\r
549 PRINT_BIT_FIELD (Eax, HWP);\r
550 PRINT_BIT_FIELD (Eax, HWP_Notification);\r
551 PRINT_BIT_FIELD (Eax, HWP_Activity_Window);\r
552 PRINT_BIT_FIELD (Eax, HWP_Energy_Performance_Preference);\r
553 PRINT_BIT_FIELD (Eax, HWP_Package_Level_Request);\r
554 PRINT_BIT_FIELD (Eax, HDC);\r
56fbaecb
ED
555 PRINT_BIT_FIELD (Eax, TurboBoostMaxTechnology30);\r
556 PRINT_BIT_FIELD (Eax, HWPCapabilities);\r
557 PRINT_BIT_FIELD (Eax, HWPPECIOverride);\r
558 PRINT_BIT_FIELD (Eax, FlexibleHWP);\r
559 PRINT_BIT_FIELD (Eax, FastAccessMode);\r
560 PRINT_BIT_FIELD (Eax, IgnoringIdleLogicalProcessorHWPRequest);\r
25705752
MK
561 PRINT_BIT_FIELD (Ebx, InterruptThresholds);\r
562 PRINT_BIT_FIELD (Ecx, HardwareCoordinationFeedback);\r
563 PRINT_BIT_FIELD (Ecx, PerformanceEnergyBias);\r
564}\r
565\r
566/**\r
567 Display CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS for all supported sub-leafs.\r
568\r
569**/\r
570VOID\r
571CpuidStructuredExtendedFeatureFlags (\r
572 VOID\r
573 )\r
574{\r
575 UINT32 Eax;\r
576 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
577 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r
56fbaecb 578 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx;\r
25705752
MK
579 UINT32 SubLeaf;\r
580\r
581 if (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > gMaximumBasicFunction) {\r
582 return;\r
583 }\r
584\r
585 AsmCpuidEx (\r
586 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
587 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
588 &Eax, NULL, NULL, NULL\r
589 );\r
590 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r
591 AsmCpuidEx (\r
592 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
593 SubLeaf,\r
56fbaecb 594 NULL, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
25705752 595 );\r
56fbaecb 596 if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0 || Edx.Uint32 != 0) {\r
25705752 597 Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);\r
56fbaecb 598 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
25705752
MK
599 PRINT_BIT_FIELD (Ebx, FSGSBASE);\r
600 PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);\r
f5a2d6f0 601 PRINT_BIT_FIELD (Ebx, SGX);\r
25705752
MK
602 PRINT_BIT_FIELD (Ebx, BMI1);\r
603 PRINT_BIT_FIELD (Ebx, HLE);\r
604 PRINT_BIT_FIELD (Ebx, AVX2);\r
605 PRINT_BIT_FIELD (Ebx, FDP_EXCPTN_ONLY);\r
606 PRINT_BIT_FIELD (Ebx, SMEP);\r
607 PRINT_BIT_FIELD (Ebx, BMI2);\r
608 PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);\r
609 PRINT_BIT_FIELD (Ebx, INVPCID);\r
610 PRINT_BIT_FIELD (Ebx, RTM);\r
14806d7b 611 PRINT_BIT_FIELD (Ebx, RDT_M);\r
25705752
MK
612 PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);\r
613 PRINT_BIT_FIELD (Ebx, MPX);\r
14806d7b 614 PRINT_BIT_FIELD (Ebx, RDT_A);\r
56fbaecb
ED
615 PRINT_BIT_FIELD (Ebx, AVX512F);\r
616 PRINT_BIT_FIELD (Ebx, AVX512DQ);\r
25705752
MK
617 PRINT_BIT_FIELD (Ebx, RDSEED);\r
618 PRINT_BIT_FIELD (Ebx, ADX);\r
619 PRINT_BIT_FIELD (Ebx, SMAP);\r
56fbaecb 620 PRINT_BIT_FIELD (Ebx, AVX512_IFMA);\r
25705752 621 PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);\r
14806d7b 622 PRINT_BIT_FIELD (Ebx, CLWB);\r
25705752 623 PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);\r
56fbaecb
ED
624 PRINT_BIT_FIELD (Ebx, AVX512PF);\r
625 PRINT_BIT_FIELD (Ebx, AVX512ER);\r
626 PRINT_BIT_FIELD (Ebx, AVX512CD);\r
14806d7b 627 PRINT_BIT_FIELD (Ebx, SHA);\r
56fbaecb
ED
628 PRINT_BIT_FIELD (Ebx, AVX512BW);\r
629 PRINT_BIT_FIELD (Ebx, AVX512VL);\r
630\r
25705752 631 PRINT_BIT_FIELD (Ecx, PREFETCHWT1);\r
56fbaecb 632 PRINT_BIT_FIELD (Ecx, AVX512_VBMI);\r
14806d7b 633 PRINT_BIT_FIELD (Ecx, UMIP);\r
25705752
MK
634 PRINT_BIT_FIELD (Ecx, PKU);\r
635 PRINT_BIT_FIELD (Ecx, OSPKE);\r
56fbaecb 636 PRINT_BIT_FIELD (Ecx, AVX512_VPOPCNTDQ);\r
14806d7b
HW
637 PRINT_BIT_FIELD (Ecx, MAWAU);\r
638 PRINT_BIT_FIELD (Ecx, RDPID);\r
639 PRINT_BIT_FIELD (Ecx, SGX_LC);\r
56fbaecb
ED
640\r
641 PRINT_BIT_FIELD (Edx, AVX512_4VNNIW);\r
642 PRINT_BIT_FIELD (Edx, AVX512_4FMAPS);\r
643 PRINT_BIT_FIELD (Edx, EnumeratesSupportForIBRSAndIBPB);\r
644 PRINT_BIT_FIELD (Edx, EnumeratesSupportForSTIBP);\r
645 PRINT_BIT_FIELD (Edx, EnumeratesSupportForL1D_FLUSH);\r
646 PRINT_BIT_FIELD (Edx, EnumeratesSupportForCapability);\r
647 PRINT_BIT_FIELD (Edx, EnumeratesSupportForSSBD);\r
25705752 648 }\r
d93a10c0 649 }\r
25705752
MK
650}\r
651\r
652/**\r
653 Display CPUID_DIRECT_CACHE_ACCESS_INFO leaf.\r
654\r
655**/\r
656VOID\r
657CpuidDirectCacheAccessInfo (\r
658 VOID\r
659 )\r
660{\r
661 UINT32 Eax;\r
662\r
663 if (CPUID_DIRECT_CACHE_ACCESS_INFO > gMaximumBasicFunction) {\r
664 return;\r
665 }\r
666\r
667 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r
668 Print (L"CPUID_DIRECT_CACHE_ACCESS_INFO (Leaf %08x)\n", CPUID_DIRECT_CACHE_ACCESS_INFO);\r
669 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r
670}\r
671\r
672/**\r
673 Display CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING leaf.\r
674\r
675**/\r
676VOID\r
677CpuidArchitecturalPerformanceMonitoring (\r
678 VOID\r
679 )\r
680{\r
681 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r
682 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r
683 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r
684\r
685 if (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING > gMaximumBasicFunction) {\r
686 return;\r
687 }\r
688\r
689 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r
690 Print (L"CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (Leaf %08x)\n", CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING);\r
691 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, Edx.Uint32);\r
692 PRINT_BIT_FIELD (Eax, ArchPerfMonVerID);\r
693 PRINT_BIT_FIELD (Eax, PerformanceMonitorCounters);\r
694 PRINT_BIT_FIELD (Eax, PerformanceMonitorCounterWidth);\r
695 PRINT_BIT_FIELD (Eax, EbxBitVectorLength);\r
696 PRINT_BIT_FIELD (Ebx, UnhaltedCoreCycles);\r
697 PRINT_BIT_FIELD (Ebx, InstructionsRetired);\r
698 PRINT_BIT_FIELD (Ebx, UnhaltedReferenceCycles);\r
699 PRINT_BIT_FIELD (Ebx, LastLevelCacheReferences);\r
700 PRINT_BIT_FIELD (Ebx, LastLevelCacheMisses);\r
701 PRINT_BIT_FIELD (Ebx, BranchInstructionsRetired);\r
702 PRINT_BIT_FIELD (Ebx, AllBranchMispredictRetired);\r
703 PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounters);\r
704 PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounterWidth);\r
56fbaecb 705 PRINT_BIT_FIELD (Edx, AnyThreadDeprecation);\r
25705752
MK
706}\r
707\r
708/**\r
709 Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.\r
710\r
501de814 711 @param[in] LeafFunction Leaf function index for CPUID_EXTENDED_TOPOLOGY.\r
d1904080 712\r
25705752
MK
713**/\r
714VOID\r
715CpuidExtendedTopology (\r
079141eb 716 UINT32 LeafFunction\r
25705752
MK
717 )\r
718{\r
719 CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r
720 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r
721 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r
722 UINT32 Edx;\r
723 UINT32 LevelNumber;\r
724\r
079141eb
RN
725 if (LeafFunction > gMaximumBasicFunction) {\r
726 return;\r
727 }\r
728 if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {\r
25705752
MK
729 return;\r
730 }\r
731\r
732 LevelNumber = 0;\r
079141eb 733 for (LevelNumber = 0; ; LevelNumber++) {\r
25705752 734 AsmCpuidEx (\r
079141eb 735 LeafFunction, LevelNumber,\r
25705752
MK
736 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r
737 );\r
079141eb
RN
738 if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
739 break;\r
25705752 740 }\r
079141eb
RN
741 Print (\r
742 L"%a (Leaf %08x, Sub-Leaf %08x)\n",\r
743 LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",\r
744 LeafFunction, LevelNumber\r
745 );\r
746 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);\r
747 PRINT_BIT_FIELD (Eax, ApicIdShift);\r
748 PRINT_BIT_FIELD (Ebx, LogicalProcessors);\r
749 PRINT_BIT_FIELD (Ecx, LevelNumber);\r
750 PRINT_BIT_FIELD (Ecx, LevelType);\r
751 PRINT_VALUE (Edx, x2APIC_ID);\r
752 }\r
25705752
MK
753}\r
754\r
755/**\r
756 Display CPUID_EXTENDED_STATE sub-leaf.\r
757\r
758**/\r
759VOID\r
760CpuidExtendedStateSubLeaf (\r
761 VOID\r
762 )\r
763{\r
764 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r
765 UINT32 Ebx;\r
766 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r
767 UINT32 Edx;\r
768\r
769 AsmCpuidEx (\r
770 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r
771 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r
772 );\r
773 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);\r
774 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);\r
775 PRINT_BIT_FIELD (Eax, XSAVEOPT);\r
776 PRINT_BIT_FIELD (Eax, XSAVEC);\r
777 PRINT_BIT_FIELD (Eax, XGETBV);\r
778 PRINT_BIT_FIELD (Eax, XSAVES);\r
779 PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);\r
780 PRINT_BIT_FIELD (Ecx, XCR0);\r
56fbaecb 781 PRINT_BIT_FIELD (Ecx, HWPState);\r
25705752
MK
782 PRINT_BIT_FIELD (Ecx, PT);\r
783 PRINT_BIT_FIELD (Ecx, XCR0_1);\r
784 PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);\r
785}\r
786\r
787/**\r
788 Display CPUID_EXTENDED_STATE size and offset information sub-leaf.\r
789\r
790**/\r
791VOID\r
792CpuidExtendedStateSizeOffset (\r
793 VOID\r
794 )\r
795{\r
796 UINT32 Eax;\r
797 UINT32 Ebx;\r
798 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r
799 UINT32 Edx;\r
800 UINT32 SubLeaf;\r
801\r
802 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
803 AsmCpuidEx (\r
804 CPUID_EXTENDED_STATE, SubLeaf,\r
805 &Eax, &Ebx, &Ecx.Uint32, &Edx\r
806 );\r
807 if (Edx != 0) {\r
808 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);\r
809 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);\r
810 PRINT_VALUE (Eax, FeatureSaveStateSize);\r
811 PRINT_VALUE (Ebx, FeatureSaveStateOffset);\r
812 PRINT_BIT_FIELD (Ecx, XSS);\r
813 PRINT_BIT_FIELD (Ecx, Compacted);\r
814 }\r
815 }\r
816}\r
817\r
818/**\r
819 Display CPUID_EXTENDED_STATE main leaf and sub-leafs.\r
820\r
821**/\r
822VOID\r
823CpuidExtendedStateMainLeaf (\r
824 VOID\r
825 )\r
826{\r
827 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r
828 UINT32 Ebx;\r
829 UINT32 Ecx;\r
830 UINT32 Edx;\r
831\r
832 if (CPUID_EXTENDED_STATE > gMaximumBasicFunction) {\r
833 return;\r
834 }\r
835\r
836 AsmCpuidEx (\r
837 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r
838 &Eax.Uint32, &Ebx, &Ecx, &Edx\r
839 );\r
840 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);\r
841 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);\r
842 PRINT_BIT_FIELD (Eax, x87);\r
843 PRINT_BIT_FIELD (Eax, SSE);\r
844 PRINT_BIT_FIELD (Eax, AVX);\r
845 PRINT_BIT_FIELD (Eax, MPX);\r
846 PRINT_BIT_FIELD (Eax, AVX_512);\r
847 PRINT_BIT_FIELD (Eax, IA32_XSS);\r
848 PRINT_BIT_FIELD (Eax, PKRU);\r
56fbaecb 849 PRINT_BIT_FIELD (Eax, IA32_XSS_2);\r
25705752
MK
850 PRINT_VALUE (Ebx, EnabledSaveStateSize);\r
851 PRINT_VALUE (Ecx, SupportedSaveStateSize);\r
852 PRINT_VALUE (Edx, XCR0_Supported_32_63);\r
853\r
854 CpuidExtendedStateSubLeaf ();\r
855 CpuidExtendedStateSizeOffset ();\r
856}\r
857\r
858/**\r
14806d7b 859 Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.\r
25705752
MK
860\r
861**/\r
862VOID\r
14806d7b 863CpuidIntelRdtMonitoringEnumerationSubLeaf (\r
25705752
MK
864 VOID\r
865 )\r
866{\r
867 UINT32 Ebx;\r
14806d7b 868 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
25705752 869\r
14806d7b 870 if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
25705752
MK
871 return;\r
872 }\r
873\r
874 AsmCpuidEx (\r
14806d7b 875 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
25705752
MK
876 NULL, &Ebx, NULL, &Edx.Uint32\r
877 );\r
14806d7b 878 Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);\r
25705752
MK
879 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r
880 PRINT_VALUE (Ebx, Maximum_RMID_Range);\r
14806d7b 881 PRINT_BIT_FIELD (Edx, L3CacheRDT_M);\r
25705752
MK
882}\r
883\r
884/**\r
14806d7b 885 Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.\r
25705752
MK
886\r
887**/\r
888VOID\r
14806d7b 889CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (\r
25705752
MK
890 VOID\r
891 )\r
892{\r
893 UINT32 Ebx;\r
894 UINT32 Ecx;\r
14806d7b 895 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
25705752 896\r
14806d7b 897 if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
25705752
MK
898 return;\r
899 }\r
900\r
901 AsmCpuidEx (\r
14806d7b 902 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
25705752
MK
903 NULL, &Ebx, &Ecx, &Edx.Uint32\r
904 );\r
14806d7b 905 Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);\r
25705752
MK
906 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r
907 PRINT_VALUE (Ebx, OccupancyConversionFactor);\r
908 PRINT_VALUE (Ecx, Maximum_RMID_Range);\r
909 PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r
14806d7b
HW
910 PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);\r
911 PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);\r
25705752
MK
912}\r
913\r
56fbaecb
ED
914/**\r
915 Display CPUID_INTEL_RDT_ALLOCATION memory bandwidth allocation technology enumeration\r
916 sub-leaf.\r
917\r
918**/\r
919VOID\r
920CpuidIntelRdtAllocationMemoryBandwidthSubLeaf (\r
921 VOID\r
922 )\r
923{\r
924 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;\r
925 UINT32 Ebx;\r
926 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;\r
927 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;\r
928\r
929 AsmCpuidEx (\r
930 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,\r
931 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
932 );\r
933 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);\r
934 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
935 PRINT_BIT_FIELD (Eax, MaximumMBAThrottling);\r
936 PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
937 PRINT_BIT_FIELD (Ecx, Liner);\r
938 PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
939}\r
940\r
25705752 941/**\r
14806d7b
HW
942 Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration\r
943 sub-leaf.\r
25705752
MK
944\r
945**/\r
946VOID\r
14806d7b 947CpuidIntelRdtAllocationL3CacheSubLeaf (\r
25705752
MK
948 VOID\r
949 )\r
950{\r
14806d7b 951 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r
25705752 952 UINT32 Ebx;\r
14806d7b
HW
953 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r
954 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r
25705752
MK
955\r
956 AsmCpuidEx (\r
14806d7b 957 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
25705752
MK
958 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
959 );\r
14806d7b 960 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);\r
25705752
MK
961 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
962 PRINT_BIT_FIELD (Eax, CapacityLength);\r
963 PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
25705752
MK
964 PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);\r
965 PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
966}\r
967\r
968/**\r
14806d7b
HW
969 Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration\r
970 sub-leaf.\r
25705752
MK
971\r
972**/\r
973VOID\r
14806d7b 974CpuidIntelRdtAllocationL2CacheSubLeaf (\r
25705752
MK
975 VOID\r
976 )\r
977{\r
14806d7b
HW
978 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r
979 UINT32 Ebx;\r
980 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
981\r
982 AsmCpuidEx (\r
983 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
984 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
985 );\r
986 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);\r
987 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
988 PRINT_BIT_FIELD (Eax, CapacityLength);\r
989 PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
990 PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
991}\r
992\r
993/**\r
994 Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.\r
995\r
996**/\r
997VOID\r
998CpuidIntelRdtAllocationMainLeaf (\r
999 VOID\r
1000 )\r
1001{\r
1002 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r
25705752 1003\r
14806d7b 1004 if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {\r
25705752
MK
1005 return;\r
1006 }\r
1007\r
1008 AsmCpuidEx (\r
14806d7b 1009 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
25705752
MK
1010 NULL, &Ebx.Uint32, NULL, NULL\r
1011 );\r
14806d7b 1012 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);\r
25705752 1013 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r
14806d7b
HW
1014 PRINT_BIT_FIELD (Ebx, L3CacheAllocation);\r
1015 PRINT_BIT_FIELD (Ebx, L2CacheAllocation);\r
56fbaecb
ED
1016 PRINT_BIT_FIELD (Ebx, MemoryBandwidth);\r
1017 CpuidIntelRdtAllocationMemoryBandwidthSubLeaf ();\r
14806d7b
HW
1018 CpuidIntelRdtAllocationL3CacheSubLeaf ();\r
1019 CpuidIntelRdtAllocationL2CacheSubLeaf ();\r
25705752
MK
1020}\r
1021\r
f5a2d6f0
JF
1022/**\r
1023 Display Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
1024\r
1025**/\r
1026VOID\r
1027CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (\r
1028 VOID\r
1029 )\r
1030{\r
1031 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
1032 UINT32 Ebx;\r
1033 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
1034\r
1035 AsmCpuidEx (\r
1036 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
1037 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
1038 );\r
1039 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);\r
1040 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
1041 PRINT_BIT_FIELD (Eax, SGX1);\r
1042 PRINT_BIT_FIELD (Eax, SGX2);\r
56fbaecb
ED
1043 PRINT_BIT_FIELD (Eax, ENCLV);\r
1044 PRINT_BIT_FIELD (Eax, ENCLS);\r
f5a2d6f0
JF
1045 PRINT_BIT_FIELD (Edx, MaxEnclaveSize_Not64);\r
1046 PRINT_BIT_FIELD (Edx, MaxEnclaveSize_64);\r
1047}\r
1048\r
1049/**\r
1050 Display Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
1051\r
1052**/\r
1053VOID\r
1054CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (\r
1055 VOID\r
1056 )\r
1057{\r
1058 UINT32 Eax;\r
1059 UINT32 Ebx;\r
1060 UINT32 Ecx;\r
1061 UINT32 Edx;\r
1062\r
1063 AsmCpuidEx (\r
1064 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
1065 &Eax, &Ebx, &Ecx, &Edx\r
1066 );\r
1067 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);\r
1068 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
1069}\r
1070\r
1071/**\r
1072 Display Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
1073\r
1074**/\r
1075VOID\r
1076CpuidEnumerationOfIntelSgxResourcesSubLeaf (\r
1077 VOID\r
1078 )\r
1079{\r
1080 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
1081 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
1082 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
1083 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
1084 UINT32 SubLeaf;\r
7367cc6c 1085\r
f5a2d6f0
JF
1086 SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;\r
1087 do {\r
1088 AsmCpuidEx (\r
1089 CPUID_INTEL_SGX, SubLeaf,\r
1090 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
1091 );\r
1092 if (Eax.Bits.SubLeafType == 0x1) {\r
1093 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);\r
1094 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1095 PRINT_BIT_FIELD (Eax, SubLeafType);\r
1096 PRINT_BIT_FIELD (Eax, LowAddressOfEpcSection);\r
1097 PRINT_BIT_FIELD (Ebx, HighAddressOfEpcSection);\r
1098 PRINT_BIT_FIELD (Ecx, EpcSection);\r
1099 PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);\r
1100 PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);\r
1101 }\r
1102 SubLeaf++;\r
1103 } while (Eax.Bits.SubLeafType == 0x1);\r
1104}\r
1105\r
1106/**\r
1107 Display Intel SGX Resource Enumeration.\r
1108\r
1109**/\r
1110VOID\r
1111CpuidEnumerationOfIntelSgx (\r
1112 VOID\r
1113 )\r
1114{\r
1115 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
1116\r
1117 if (CPUID_INTEL_SGX > gMaximumBasicFunction) {\r
1118 return;\r
1119 }\r
1120\r
1121 AsmCpuidEx (\r
1122 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
1123 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
1124 NULL, &Ebx.Uint32, NULL, NULL\r
1125 );\r
1126 if (Ebx.Bits.SGX != 1) {\r
1127 //\r
1128 // Only if CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support\r
1129 // for Intel SGX.\r
1130 //\r
1131 return;\r
1132 }\r
7367cc6c 1133\r
f5a2d6f0
JF
1134 CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();\r
1135 CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();\r
1136 CpuidEnumerationOfIntelSgxResourcesSubLeaf ();\r
1137}\r
1138\r
25705752
MK
1139/**\r
1140 Display CPUID_INTEL_PROCESSOR_TRACE sub-leafs.\r
1141\r
1142 @param[in] MaximumSubLeaf Maximum sub-leaf index for CPUID_INTEL_PROCESSOR_TRACE.\r
1143\r
1144**/\r
1145VOID\r
1146CpuidIntelProcessorTraceSubLeaf (\r
1147 UINT32 MaximumSubLeaf\r
1148 )\r
1149{\r
1150 UINT32 SubLeaf;\r
1151 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r
1152 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r
1153\r
1154 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
1155 AsmCpuidEx (\r
1156 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r
1157 &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r
1158 );\r
1159 Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);\r
1160 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);\r
1161 PRINT_BIT_FIELD (Eax, ConfigurableAddressRanges);\r
1162 PRINT_BIT_FIELD (Eax, MtcPeriodEncodings);\r
1163 PRINT_BIT_FIELD (Ebx, CycleThresholdEncodings);\r
1164 PRINT_BIT_FIELD (Ebx, PsbFrequencyEncodings);\r
1165 }\r
1166}\r
1167\r
1168/**\r
1169 Display CPUID_INTEL_PROCESSOR_TRACE main leaf and sub-leafs.\r
1170\r
1171**/\r
1172VOID\r
1173CpuidIntelProcessorTraceMainLeaf (\r
1174 VOID\r
1175 )\r
1176{\r
1177 UINT32 Eax;\r
1178 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r
1179 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r
1180\r
1181 if (CPUID_INTEL_PROCESSOR_TRACE > gMaximumBasicFunction) {\r
1182 return;\r
1183 }\r
1184\r
1185 AsmCpuidEx (\r
1186 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
1187 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r
1188 );\r
1189 Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);\r
1190 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r
1191 PRINT_VALUE (Eax, MaximumSubLeaf);\r
1192 PRINT_BIT_FIELD (Ebx, Cr3Filter);\r
1193 PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r
1194 PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r
1195 PRINT_BIT_FIELD (Ebx, Mtc);\r
14806d7b
HW
1196 PRINT_BIT_FIELD (Ebx, PTWrite);\r
1197 PRINT_BIT_FIELD (Ebx, PowerEventTrace);\r
25705752
MK
1198 PRINT_BIT_FIELD (Ecx, RTIT);\r
1199 PRINT_BIT_FIELD (Ecx, ToPA);\r
1200 PRINT_BIT_FIELD (Ecx, SingleRangeOutput);\r
1201 PRINT_BIT_FIELD (Ecx, TraceTransportSubsystem);\r
1202 PRINT_BIT_FIELD (Ecx, LIP);\r
1203\r
1204 CpuidIntelProcessorTraceSubLeaf (Eax);\r
1205}\r
1206\r
1207/**\r
1208 Display CPUID_TIME_STAMP_COUNTER leaf.\r
1209\r
1210**/\r
1211VOID\r
1212CpuidTimeStampCounter (\r
1213 VOID\r
1214 )\r
1215{\r
1216 UINT32 Eax;\r
1217 UINT32 Ebx;\r
14806d7b 1218 UINT32 Ecx;\r
25705752
MK
1219\r
1220 if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {\r
1221 return;\r
1222 }\r
1223\r
14806d7b 1224 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
25705752 1225 Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);\r
14806d7b 1226 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0);\r
25705752
MK
1227}\r
1228\r
1229/**\r
1230 Display CPUID_PROCESSOR_FREQUENCY leaf.\r
1231\r
1232**/\r
1233VOID\r
1234CpuidProcessorFrequency (\r
1235 VOID\r
1236 )\r
1237{\r
1238 CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r
1239 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r
1240 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r
1241\r
1242 if (CPUID_PROCESSOR_FREQUENCY > gMaximumBasicFunction) {\r
1243 return;\r
1244 }\r
1245\r
1246 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
1247 Print (L"CPUID_PROCESSOR_FREQUENCY (Leaf %08x)\n", CPUID_PROCESSOR_FREQUENCY);\r
1248 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);\r
1249 PRINT_BIT_FIELD (Eax, ProcessorBaseFrequency);\r
1250 PRINT_BIT_FIELD (Ebx, MaximumFrequency);\r
1251 PRINT_BIT_FIELD (Ecx, BusFrequency);\r
1252}\r
1253\r
1254/**\r
1255 Display CPUID_SOC_VENDOR sub-leafs that contain the SoC Vendor Brand String.\r
1256 Also display these sub-leafs as a single SoC Vendor Brand String.\r
1257\r
1258**/\r
1259VOID\r
1260CpuidSocVendorBrandString (\r
1261 VOID\r
1262 )\r
1263{\r
1264 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
1265 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
1266 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
1267 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
1268 //\r
1269 // Array to store brand string from 3 brand string leafs with\r
1270 // 4 32-bit brand string values per leaf and an extra value to\r
1271 // null terminate the string.\r
1272 //\r
1273 UINT32 BrandString[3 * 4 + 1];\r
1274\r
1275 AsmCpuidEx (\r
1276 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r
1277 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
1278 );\r
1279 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);\r
1280 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1281 BrandString[0] = Eax.Uint32;\r
1282 BrandString[1] = Ebx.Uint32;\r
1283 BrandString[2] = Ecx.Uint32;\r
1284 BrandString[3] = Edx.Uint32;\r
1285\r
1286 AsmCpuidEx (\r
1287 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r
1288 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
1289 );\r
1290 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);\r
1291 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1292 BrandString[4] = Eax.Uint32;\r
1293 BrandString[5] = Ebx.Uint32;\r
1294 BrandString[6] = Ecx.Uint32;\r
1295 BrandString[7] = Edx.Uint32;\r
1296\r
1297 AsmCpuidEx (\r
1298 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r
1299 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
1300 );\r
1301 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);\r
1302 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1303 BrandString[8] = Eax.Uint32;\r
1304 BrandString[9] = Ebx.Uint32;\r
1305 BrandString[10] = Ecx.Uint32;\r
1306 BrandString[11] = Edx.Uint32;\r
1307\r
1308 BrandString[12] = 0;\r
1309\r
1310 Print (L"Vendor Brand String = %a\n", (CHAR8 *)BrandString);\r
1311}\r
1312\r
1313/**\r
1314 Display CPUID_SOC_VENDOR main leaf and sub-leafs.\r
1315\r
1316**/\r
1317VOID\r
1318CpuidSocVendor (\r
1319 VOID\r
1320 )\r
1321{\r
1322 UINT32 Eax;\r
1323 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r
1324 UINT32 Ecx;\r
1325 UINT32 Edx;\r
1326\r
1327 if (CPUID_SOC_VENDOR > gMaximumBasicFunction) {\r
1328 return;\r
1329 }\r
1330\r
1331 AsmCpuidEx (\r
1332 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r
1333 &Eax, &Ebx.Uint32, &Ecx, &Edx\r
1334 );\r
1335 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);\r
1336 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);\r
1337 if (Eax < 3) {\r
1338 Print (L" Not Supported\n");\r
1339 return;\r
1340 }\r
1341 PRINT_VALUE (Eax, MaxSOCID_Index);\r
1342 PRINT_BIT_FIELD (Ebx, SocVendorId);\r
1343 PRINT_BIT_FIELD (Ebx, IsVendorScheme);\r
1344 PRINT_VALUE (Ecx, ProjectID);\r
1345 PRINT_VALUE (Edx, SteppingID);\r
1346 CpuidSocVendorBrandString ();\r
1347}\r
1348\r
56fbaecb
ED
1349/**\r
1350 Display CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS main leaf and sub-leafs.\r
1351\r
1352**/\r
1353VOID\r
1354CpuidDeterministicAddressTranslationParameters (\r
1355 VOID\r
1356 )\r
1357{\r
1358 UINT32 Eax;\r
1359 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;\r
1360 UINT32 Ecx;\r
1361 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;\r
1362\r
1363 if (CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS > gMaximumBasicFunction) {\r
1364 return;\r
1365 }\r
1366\r
1367 AsmCpuidEx (\r
1368 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,\r
1369 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,\r
1370 &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
1371 );\r
1372 Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);\r
1373 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);\r
1374\r
1375 PRINT_VALUE (Eax, MaxID_Index);\r
1376 PRINT_BIT_FIELD (Ebx, Page4K);\r
1377 PRINT_BIT_FIELD (Ebx, Page2M);\r
1378 PRINT_BIT_FIELD (Ebx, Page4M);\r
1379 PRINT_BIT_FIELD (Ebx, Page1G);\r
1380 PRINT_BIT_FIELD (Ebx, Partitioning);\r
1381 PRINT_BIT_FIELD (Ebx, Way);\r
1382\r
1383 PRINT_VALUE (Ecx, NumberOfSets);\r
1384\r
1385 PRINT_BIT_FIELD (Edx, TranslationCacheType);\r
1386 PRINT_BIT_FIELD (Edx, TranslationCacheLevel);\r
1387 PRINT_BIT_FIELD (Edx, FullyAssociative);\r
1388 PRINT_BIT_FIELD (Edx, MaximumNum);\r
1389}\r
1390\r
25705752
MK
1391/**\r
1392 Display CPUID_EXTENDED_FUNCTION leaf.\r
1393\r
1394**/\r
1395VOID\r
1396CpuidExtendedFunction (\r
1397 VOID\r
1398 )\r
1399{\r
1400 UINT32 Eax;\r
1401\r
1402 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
1403 Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);\r
1404 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r
1405 PRINT_VALUE (Eax, MaximumExtendedFunction);\r
1406\r
1407 gMaximumExtendedFunction = Eax;\r
1408}\r
1409\r
1410/**\r
1411 Display CPUID_EXTENDED_CPU_SIG leaf.\r
1412\r
1413**/\r
1414VOID\r
1415CpuidExtendedCpuSig (\r
1416 VOID\r
1417 )\r
1418{\r
1419 UINT32 Eax;\r
1420 CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r
1421 CPUID_EXTENDED_CPU_SIG_EDX Edx;\r
1422\r
1423 if (CPUID_EXTENDED_CPU_SIG > gMaximumExtendedFunction) {\r
1424 return;\r
1425 }\r
1426\r
1427 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r
1428 Print (L"CPUID_EXTENDED_CPU_SIG (Leaf %08x)\n", CPUID_EXTENDED_CPU_SIG);\r
1429 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, Ecx.Uint32, Edx.Uint32);\r
1430 PRINT_BIT_FIELD (Ecx, LAHF_SAHF);\r
1431 PRINT_BIT_FIELD (Ecx, LZCNT);\r
1432 PRINT_BIT_FIELD (Ecx, PREFETCHW);\r
1433 PRINT_BIT_FIELD (Edx, SYSCALL_SYSRET);\r
1434 PRINT_BIT_FIELD (Edx, NX);\r
1435 PRINT_BIT_FIELD (Edx, Page1GB);\r
1436 PRINT_BIT_FIELD (Edx, RDTSCP);\r
1437 PRINT_BIT_FIELD (Edx, LM);\r
1438}\r
1439\r
1440/**\r
1441 Display CPUID_BRAND_STRING1, CPUID_BRAND_STRING2 and CPUID_BRAND_STRING3\r
1442 leafs. Also display these three leafs as a single brand string.\r
1443\r
1444**/\r
1445VOID\r
1446CpuidProcessorBrandString (\r
1447 VOID\r
1448 )\r
1449{\r
1450 CPUID_BRAND_STRING_DATA Eax;\r
1451 CPUID_BRAND_STRING_DATA Ebx;\r
1452 CPUID_BRAND_STRING_DATA Ecx;\r
1453 CPUID_BRAND_STRING_DATA Edx;\r
1454 //\r
1455 // Array to store brand string from 3 brand string leafs with\r
1456 // 4 32-bit brand string values per leaf and an extra value to\r
1457 // null terminate the string.\r
1458 //\r
1459 UINT32 BrandString[3 * 4 + 1];\r
1460\r
1461 if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {\r
1462 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1463 Print (L"CPUID_BRAND_STRING1 (Leaf %08x)\n", CPUID_BRAND_STRING1);\r
1464 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1465 BrandString[0] = Eax.Uint32;\r
1466 BrandString[1] = Ebx.Uint32;\r
1467 BrandString[2] = Ecx.Uint32;\r
1468 BrandString[3] = Edx.Uint32;\r
1469 }\r
1470\r
1471 if (CPUID_BRAND_STRING2 <= gMaximumExtendedFunction) {\r
1472 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1473 Print (L"CPUID_BRAND_STRING2 (Leaf %08x)\n", CPUID_BRAND_STRING2);\r
1474 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1475 BrandString[4] = Eax.Uint32;\r
1476 BrandString[5] = Ebx.Uint32;\r
1477 BrandString[6] = Ecx.Uint32;\r
1478 BrandString[7] = Edx.Uint32;\r
1479 }\r
1480\r
1481 if (CPUID_BRAND_STRING3 <= gMaximumExtendedFunction) {\r
1482 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1483 Print (L"CPUID_BRAND_STRING3 (Leaf %08x)\n", CPUID_BRAND_STRING3);\r
1484 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1485 BrandString[8] = Eax.Uint32;\r
1486 BrandString[9] = Ebx.Uint32;\r
1487 BrandString[10] = Ecx.Uint32;\r
1488 BrandString[11] = Edx.Uint32;\r
1489 }\r
1490\r
1491 BrandString[12] = 0;\r
1492\r
1493 Print (L"Brand String = %a\n", (CHAR8 *)BrandString);\r
1494}\r
1495\r
1496/**\r
1497 Display CPUID_EXTENDED_CACHE_INFO leaf.\r
1498\r
1499**/\r
1500VOID\r
1501CpuidExtendedCacheInfo (\r
1502 VOID\r
1503 )\r
1504{\r
1505 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r
1506\r
1507 if (CPUID_EXTENDED_CACHE_INFO > gMaximumExtendedFunction) {\r
1508 return;\r
1509 }\r
1510\r
1511 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r
1512 Print (L"CPUID_EXTENDED_CACHE_INFO (Leaf %08x)\n", CPUID_EXTENDED_CACHE_INFO);\r
1513 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx.Uint32, 0);\r
1514 PRINT_BIT_FIELD (Ecx, CacheLineSize);\r
1515 PRINT_BIT_FIELD (Ecx, L2Associativity);\r
1516 PRINT_BIT_FIELD (Ecx, CacheSize);\r
1517}\r
1518\r
1519/**\r
1520 Display CPUID_EXTENDED_TIME_STAMP_COUNTER leaf.\r
1521\r
1522**/\r
1523VOID\r
1524CpuidExtendedTimeStampCounter (\r
1525 VOID\r
1526 )\r
1527{\r
1528 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;\r
1529\r
1530 if (CPUID_EXTENDED_TIME_STAMP_COUNTER > gMaximumExtendedFunction) {\r
1531 return;\r
1532 }\r
1533\r
1534 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r
1535 Print (L"CPUID_EXTENDED_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_EXTENDED_TIME_STAMP_COUNTER);\r
1536 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, 0, Edx.Uint32);\r
1537 PRINT_BIT_FIELD (Edx, InvariantTsc);\r
1538}\r
1539\r
1540/**\r
1541 Display CPUID_VIR_PHY_ADDRESS_SIZE leaf.\r
1542\r
1543**/\r
1544VOID\r
1545CpuidVirPhyAddressSize (\r
1546 VOID\r
1547 )\r
1548{\r
1549 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;\r
1550\r
1551 if (CPUID_VIR_PHY_ADDRESS_SIZE > gMaximumExtendedFunction) {\r
1552 return;\r
1553 }\r
1554\r
1555 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r
1556 Print (L"CPUID_VIR_PHY_ADDRESS_SIZE (Leaf %08x)\n", CPUID_VIR_PHY_ADDRESS_SIZE);\r
1557 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, 0, 0, 0);\r
1558 PRINT_BIT_FIELD (Eax, PhysicalAddressBits);\r
1559 PRINT_BIT_FIELD (Eax, LinearAddressBits);\r
1560}\r
1561\r
1562/**\r
1563 The user Entry Point for Application. The user code starts with this function\r
1564 as the real entry point for the application.\r
1565\r
1566 @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
1567 @param[in] SystemTable A pointer to the EFI System Table.\r
1568\r
1569 @retval EFI_SUCCESS The entry point is executed successfully.\r
1570 @retval other Some error occurs when executing this entry point.\r
1571\r
1572**/\r
1573EFI_STATUS\r
1574EFIAPI\r
1575UefiMain (\r
1576 IN EFI_HANDLE ImageHandle,\r
1577 IN EFI_SYSTEM_TABLE *SystemTable\r
1578 )\r
1579{\r
1580 Print (L"UEFI CPUID Version 0.5\n");\r
1581\r
1582 CpuidSignature ();\r
1583 CpuidVersionInfo ();\r
1584 CpuidCacheInfo ();\r
1585 CpuidSerialNumber ();\r
1586 CpuidCacheParams();\r
1587 CpuidMonitorMwait ();\r
1588 CpuidThermalPowerManagement ();\r
1589 CpuidStructuredExtendedFeatureFlags ();\r
1590 CpuidDirectCacheAccessInfo();\r
1591 CpuidArchitecturalPerformanceMonitoring ();\r
079141eb 1592 CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY);\r
25705752 1593 CpuidExtendedStateMainLeaf ();\r
14806d7b
HW
1594 CpuidIntelRdtMonitoringEnumerationSubLeaf ();\r
1595 CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();\r
1596 CpuidIntelRdtAllocationMainLeaf ();\r
f5a2d6f0 1597 CpuidEnumerationOfIntelSgx ();\r
25705752
MK
1598 CpuidIntelProcessorTraceMainLeaf ();\r
1599 CpuidTimeStampCounter ();\r
1600 CpuidProcessorFrequency ();\r
1601 CpuidSocVendor ();\r
56fbaecb 1602 CpuidDeterministicAddressTranslationParameters ();\r
079141eb 1603 CpuidExtendedTopology (CPUID_V2_EXTENDED_TOPOLOGY);\r
25705752
MK
1604 CpuidExtendedFunction ();\r
1605 CpuidExtendedCpuSig ();\r
1606 CpuidProcessorBrandString ();\r
1607 CpuidExtendedCacheInfo ();\r
1608 CpuidExtendedTimeStampCounter ();\r
1609 CpuidVirPhyAddressSize ();\r
1610\r
1611 return EFI_SUCCESS;\r
1612}\r