UefiCpuPkg/CpuDxe: Enable protection for newly added page table
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.h
CommitLineData
a47463f2 1/** @file\r
7fadaacd 2 CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.\r
a47463f2 3\r
7537f8c0 4 Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc 5 This program and the accompanying materials\r
a47463f2 6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
430fbbe0 15#ifndef _CPU_DXE_H_\r
16#define _CPU_DXE_H_\r
a47463f2 17\r
18#include <PiDxe.h>\r
19\r
20#include <Protocol/Cpu.h>\r
7fadaacd 21#include <Protocol/MpService.h>\r
b1bd0d74 22#include <Register/Msr.h>\r
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23\r
24#include <Ppi/SecPlatformInformation.h>\r
25#include <Ppi/SecPlatformInformation2.h>\r
a47463f2 26\r
27#include <Library/UefiDriverEntryPoint.h>\r
28#include <Library/UefiBootServicesTableLib.h>\r
29#include <Library/DxeServicesTableLib.h>\r
30#include <Library/BaseLib.h>\r
31#include <Library/CpuLib.h>\r
32#include <Library/BaseMemoryLib.h>\r
33#include <Library/MemoryAllocationLib.h>\r
34#include <Library/DebugLib.h>\r
35#include <Library/MtrrLib.h>\r
d4605c23 36#include <Library/LocalApicLib.h>\r
661cab5d 37#include <Library/UefiCpuLib.h>\r
e41aad15
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38#include <Library/UefiLib.h>\r
39#include <Library/CpuExceptionHandlerLib.h>\r
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40#include <Library/HobLib.h>\r
41#include <Library/ReportStatusCodeLib.h>\r
42#include <Library/MpInitLib.h>\r
7537f8c0 43#include <Library/TimerLib.h>\r
7fadaacd 44\r
32394027 45#include <Guid/IdleLoopEvent.h>\r
e41aad15 46#include <Guid/VectorHandoffTable.h>\r
a47463f2 47\r
48#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \\r
49 EFI_MEMORY_WC | \\r
50 EFI_MEMORY_WT | \\r
51 EFI_MEMORY_WB | \\r
52 EFI_MEMORY_UCE \\r
53 )\r
54\r
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55#define EFI_MEMORY_PAGETYPE_MASK (EFI_MEMORY_RP | \\r
56 EFI_MEMORY_XP | \\r
57 EFI_MEMORY_RO \\r
58 )\r
a47463f2 59\r
430fbbe0 60/**\r
61 Flush CPU data cache. If the instruction cache is fully coherent\r
62 with all DMA operations then function can just return EFI_SUCCESS.\r
63\r
64 @param This Protocol instance structure\r
65 @param Start Physical address to start flushing from.\r
66 @param Length Number of bytes to flush. Round up to chipset\r
67 granularity.\r
68 @param FlushType Specifies the type of flush operation to perform.\r
69\r
70 @retval EFI_SUCCESS If cache was flushed\r
71 @retval EFI_UNSUPPORTED If flush type is not supported.\r
72 @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
73\r
74**/\r
a47463f2 75EFI_STATUS\r
76EFIAPI\r
77CpuFlushCpuDataCache (\r
78 IN EFI_CPU_ARCH_PROTOCOL *This,\r
79 IN EFI_PHYSICAL_ADDRESS Start,\r
80 IN UINT64 Length,\r
81 IN EFI_CPU_FLUSH_TYPE FlushType\r
82 );\r
83\r
430fbbe0 84/**\r
85 Enables CPU interrupts.\r
86\r
87 @param This Protocol instance structure\r
88\r
89 @retval EFI_SUCCESS If interrupts were enabled in the CPU\r
90 @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
91\r
92**/\r
a47463f2 93EFI_STATUS\r
94EFIAPI\r
95CpuEnableInterrupt (\r
96 IN EFI_CPU_ARCH_PROTOCOL *This\r
97 );\r
98\r
430fbbe0 99/**\r
100 Disables CPU interrupts.\r
101\r
102 @param This Protocol instance structure\r
103\r
104 @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
105 @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
106\r
107**/\r
a47463f2 108EFI_STATUS\r
109EFIAPI\r
110CpuDisableInterrupt (\r
111 IN EFI_CPU_ARCH_PROTOCOL *This\r
112 );\r
113\r
430fbbe0 114/**\r
115 Return the state of interrupts.\r
116\r
117 @param This Protocol instance structure\r
118 @param State Pointer to the CPU's current interrupt state\r
119\r
120 @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
121 @retval EFI_INVALID_PARAMETER State is NULL.\r
122\r
123**/\r
a47463f2 124EFI_STATUS\r
125EFIAPI\r
126CpuGetInterruptState (\r
127 IN EFI_CPU_ARCH_PROTOCOL *This,\r
128 OUT BOOLEAN *State\r
129 );\r
130\r
430fbbe0 131/**\r
132 Generates an INIT to the CPU.\r
133\r
134 @param This Protocol instance structure\r
135 @param InitType Type of CPU INIT to perform\r
136\r
137 @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
138 seen.\r
139 @retval EFI_DEVICE_ERROR If CPU INIT failed.\r
140 @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
141\r
142**/\r
a47463f2 143EFI_STATUS\r
144EFIAPI\r
145CpuInit (\r
146 IN EFI_CPU_ARCH_PROTOCOL *This,\r
147 IN EFI_CPU_INIT_TYPE InitType\r
148 );\r
149\r
430fbbe0 150/**\r
151 Registers a function to be called from the CPU interrupt handler.\r
152\r
153 @param This Protocol instance structure\r
154 @param InterruptType Defines which interrupt to hook. IA-32\r
155 valid range is 0x00 through 0xFF\r
156 @param InterruptHandler A pointer to a function of type\r
157 EFI_CPU_INTERRUPT_HANDLER that is called\r
158 when a processor interrupt occurs. A null\r
159 pointer is an error condition.\r
160\r
161 @retval EFI_SUCCESS If handler installed or uninstalled.\r
162 @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
163 for InterruptType was previously installed.\r
164 @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
165 InterruptType was not previously installed.\r
166 @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
167 is not supported.\r
168\r
169**/\r
a47463f2 170EFI_STATUS\r
171EFIAPI\r
172CpuRegisterInterruptHandler (\r
173 IN EFI_CPU_ARCH_PROTOCOL *This,\r
174 IN EFI_EXCEPTION_TYPE InterruptType,\r
175 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
176 );\r
177\r
430fbbe0 178/**\r
179 Returns a timer value from one of the CPU's internal timers. There is no\r
180 inherent time interval between ticks but is a function of the CPU frequency.\r
181\r
182 @param This - Protocol instance structure.\r
183 @param TimerIndex - Specifies which CPU timer is requested.\r
184 @param TimerValue - Pointer to the returned timer value.\r
185 @param TimerPeriod - A pointer to the amount of time that passes\r
186 in femtoseconds (10-15) for each increment\r
187 of TimerValue. If TimerValue does not\r
188 increment at a predictable rate, then 0 is\r
189 returned. The amount of time that has\r
190 passed between two calls to GetTimerValue()\r
191 can be calculated with the formula\r
192 (TimerValue2 - TimerValue1) * TimerPeriod.\r
193 This parameter is optional and may be NULL.\r
194\r
195 @retval EFI_SUCCESS - If the CPU timer count was returned.\r
196 @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
197 @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
198 @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
199\r
200**/\r
a47463f2 201EFI_STATUS\r
202EFIAPI\r
203CpuGetTimerValue (\r
204 IN EFI_CPU_ARCH_PROTOCOL *This,\r
205 IN UINT32 TimerIndex,\r
206 OUT UINT64 *TimerValue,\r
207 OUT UINT64 *TimerPeriod OPTIONAL\r
208 );\r
209\r
430fbbe0 210/**\r
211 Set memory cacheability attributes for given range of memeory.\r
212\r
213 @param This Protocol instance structure\r
214 @param BaseAddress Specifies the start address of the\r
215 memory range\r
216 @param Length Specifies the length of the memory range\r
217 @param Attributes The memory cacheability for the memory range\r
218\r
219 @retval EFI_SUCCESS If the cacheability of that memory range is\r
220 set successfully\r
221 @retval EFI_UNSUPPORTED If the desired operation cannot be done\r
222 @retval EFI_INVALID_PARAMETER The input parameter is not correct,\r
223 such as Length = 0\r
224\r
225**/\r
a47463f2 226EFI_STATUS\r
227EFIAPI\r
228CpuSetMemoryAttributes (\r
229 IN EFI_CPU_ARCH_PROTOCOL *This,\r
230 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
231 IN UINT64 Length,\r
232 IN UINT64 Attributes\r
233 );\r
234\r
430fbbe0 235/**\r
236 Initialize Global Descriptor Table.\r
237\r
238**/\r
a47463f2 239VOID\r
240InitGlobalDescriptorTable (\r
241 VOID\r
242 );\r
243\r
430fbbe0 244/**\r
245 Sets the code selector (CS).\r
246\r
247 @param Selector Value of code selector.\r
248\r
249**/\r
a47463f2 250VOID\r
251EFIAPI\r
252SetCodeSelector (\r
253 UINT16 Selector\r
254 );\r
255\r
430fbbe0 256/**\r
257 Sets the data selector (DS).\r
258\r
259 @param Selector Value of data selector.\r
260\r
261**/\r
a47463f2 262VOID\r
263EFIAPI\r
264SetDataSelectors (\r
265 UINT16 Selector\r
266 );\r
267\r
cbd7300c
DB
268/**\r
269 Update GCD memory space attributes according to current page table setup.\r
270**/\r
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271VOID\r
272RefreshGcdMemoryAttributesFromPaging (\r
273 VOID\r
274 );\r
275\r
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276extern BOOLEAN mIsAllocatingPageTable;\r
277\r
a47463f2 278#endif\r
279\r