[mirror_edk2.git] / UefiCpuPkg / Include / Library / LocalApicLib.h

/** @file\r
  Public include file for Local APIC library.\r
\r
  Local APIC library assumes local APIC is enabled. It does not\r
  handles cases where local APIC is disabled.\r
\r
  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __LOCAL_APIC_LIB_H__\r
#define __LOCAL_APIC_LIB_H__\r
\r
#define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.\r
#define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.\r
\r
/**\r
  Retrieve the base address of local APIC.\r
\r
  @return The base address of local APIC.\r
\r
**/\r
UINTN\r
EFIAPI\r
GetLocalApicBaseAddress (\r
  VOID\r
  );\r
\r
/**\r
  Set the base address of local APIC.\r
\r
  If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
\r
  @param[in] BaseAddress   Local APIC base address to be set.\r
\r
**/\r
VOID\r
EFIAPI\r
SetLocalApicBaseAddress (\r
  IN UINTN                BaseAddress\r
  );\r
\r
/**\r
  Get the current local APIC mode.\r
\r
  If local APIC is disabled, then ASSERT.\r
\r
  @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.\r
  @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
**/\r
UINTN\r
EFIAPI\r
GetApicMode (\r
  VOID\r
  );\r
\r
/**\r
  Set the current local APIC mode.\r
\r
  If the specified local APIC mode is not valid, then ASSERT.\r
  If the specified local APIC mode can't be set as current, then ASSERT.\r
\r
  @param ApicMode APIC mode to be set.\r
\r
  @note  This API must not be called from an interrupt handler or SMI handler.\r
         It may result in unpredictable behavior.\r
**/\r
VOID\r
EFIAPI\r
SetApicMode (\r
  IN UINTN  ApicMode\r
  );\r
\r
/**\r
  Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
  In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
  the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
  @return  32-bit initial local APIC ID of the executing processor.\r
**/\r
UINT32\r
EFIAPI\r
GetInitialApicId (\r
  VOID\r
  );\r
\r
/**\r
  Get the local APIC ID of the executing processor.\r
\r
  @return  32-bit local APIC ID of the executing processor.\r
**/\r
UINT32\r
EFIAPI\r
GetApicId (\r
  VOID\r
  );\r
\r
/**\r
  Get the value of the local APIC version register.\r
\r
  @return  the value of the local APIC version register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicVersion (\r
  VOID\r
  );\r
\r
/**\r
  Send a Fixed IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   The local APIC ID of the target processor.\r
  @param  Vector   The vector number of the interrupt being sent.\r
**/\r
VOID\r
EFIAPI\r
SendFixedIpi (\r
  IN UINT32          ApicId,\r
  IN UINT8           Vector\r
  );\r
\r
/**\r
  Send a Fixed IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
\r
  @param  Vector   The vector number of the interrupt being sent.\r
**/\r
VOID\r
EFIAPI\r
SendFixedIpiAllExcludingSelf (\r
  IN UINT8           Vector\r
  );\r
\r
/**\r
  Send a SMI IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   Specify the local APIC ID of the target processor.\r
**/\r
VOID\r
EFIAPI\r
SendSmiIpi (\r
  IN UINT32          ApicId\r
  );\r
\r
/**\r
  Send a SMI IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
**/\r
VOID\r
EFIAPI\r
SendSmiIpiAllExcludingSelf (\r
  VOID\r
  );\r
\r
/**\r
  Send an INIT IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   Specify the local APIC ID of the target processor.\r
**/\r
VOID\r
EFIAPI\r
SendInitIpi (\r
  IN UINT32          ApicId\r
  );\r
\r
/**\r
  Send an INIT IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
**/\r
VOID\r
EFIAPI\r
SendInitIpiAllExcludingSelf (\r
  VOID\r
  );\r
\r
/**\r
  Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  if StartupRoutine >= 1M, then ASSERT.\r
  if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
  @param  ApicId          Specify the local APIC ID of the target processor.\r
  @param  StartupRoutine  Points to a start-up routine which is below 1M physical\r
                          address and 4K aligned.\r
**/\r
VOID\r
EFIAPI\r
SendInitSipiSipi (\r
  IN UINT32          ApicId,\r
  IN UINT32          StartupRoutine\r
  );\r
\r
/**\r
  Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
\r
  if StartupRoutine >= 1M, then ASSERT.\r
  if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
  @param  StartupRoutine    Points to a start-up routine which is below 1M physical\r
                            address and 4K aligned.\r
**/\r
VOID\r
EFIAPI\r
SendInitSipiSipiAllExcludingSelf (\r
  IN UINT32          StartupRoutine\r
  );\r
\r
/**\r
  Programming Virtual Wire Mode.\r
\r
  This function programs the local APIC for virtual wire mode following\r
  the example described in chapter A.3 of the MP 1.4 spec.\r
\r
  IOxAPIC is not involved in this type of virtual wire mode.\r
**/\r
VOID\r
EFIAPI\r
ProgramVirtualWireMode (\r
  VOID\r
  );\r
\r
/**\r
  Disable LINT0 & LINT1 interrupts.\r
\r
  This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
**/\r
VOID\r
EFIAPI\r
DisableLvtInterrupts (\r
  VOID\r
  );\r
\r
/**\r
  Read the initial count value from the init-count register.\r
\r
  @return The initial count value read from the init-count register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicTimerInitCount (\r
  VOID\r
  );\r
\r
/**\r
  Read the current count value from the current-count register.\r
\r
  @return The current count value read from the current-count register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicTimerCurrentCount (\r
  VOID\r
  );\r
\r
/**\r
  Initialize the local APIC timer.\r
\r
  The local APIC timer is initialized and enabled.\r
\r
  @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
                       If it is 0, then use the current divide value in the DCR.\r
  @param InitCount     The initial count value.\r
  @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
  @param Vector        The timer interrupt vector number.\r
**/\r
VOID\r
EFIAPI\r
InitializeApicTimer (\r
  IN UINTN   DivideValue,\r
  IN UINT32  InitCount,\r
  IN BOOLEAN PeriodicMode,\r
  IN UINT8   Vector\r
  );\r
\r
/**\r
  Get the state of the local APIC timer.\r
\r
  @param DivideValue   Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
  @param PeriodicMode  Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
  @param Vector        Return the timer interrupt vector number.\r
**/\r
VOID\r
EFIAPI\r
GetApicTimerState (\r
  OUT UINTN    *DivideValue  OPTIONAL,\r
  OUT BOOLEAN  *PeriodicMode  OPTIONAL,\r
  OUT UINT8    *Vector  OPTIONAL\r
  );\r
\r
/**\r
  Enable the local APIC timer interrupt.\r
**/\r
VOID\r
EFIAPI\r
EnableApicTimerInterrupt (\r
  VOID\r
  );\r
\r
/**\r
  Disable the local APIC timer interrupt.\r
**/\r
VOID\r
EFIAPI\r
DisableApicTimerInterrupt (\r
  VOID\r
  );\r
\r
/**\r
  Get the local APIC timer interrupt state.\r
\r
  @retval TRUE  The local APIC timer interrupt is enabled.\r
  @retval FALSE The local APIC timer interrupt is disabled.\r
**/\r
BOOLEAN\r
EFIAPI\r
GetApicTimerInterruptState (\r
  VOID\r
  );\r
\r
/**\r
  Send EOI to the local APIC.\r
**/\r
VOID\r
EFIAPI\r
SendApicEoi (\r
  VOID\r
  );\r
\r
/**\r
  Get the 32-bit address that a device should use to send a Message Signaled \r
  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
  @return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
EFIAPI    \r
GetApicMsiAddress (\r
  VOID\r
  );\r
    \r
/**\r
  Get the 64-bit data value that a device should use to send a Message Signaled \r
  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
  If Vector is not in range 0x10..0xFE, then ASSERT().\r
  If DeliveryMode is not supported, then ASSERT().\r
  \r
  @param  Vector          The 8-bit interrupt vector associated with the MSI.  \r
                          Must be in the range 0x10..0xFE\r
  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI \r
                          is handled.  The only supported values are:\r
                            0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
                            1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
                            2: LOCAL_APIC_DELIVERY_MODE_SMI\r
                            4: LOCAL_APIC_DELIVERY_MODE_NMI\r
                            5: LOCAL_APIC_DELIVERY_MODE_INIT\r
                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
                          \r
  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  \r
                          FALSE specifies an edge triggered interrupt.\r
  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.\r
                          TRUE specifies a level triggered interrupt that active \r
                          when the interrupt line is asserted.\r
                          FALSE specifies a level triggered interrupt that active \r
                          when the interrupt line is deasserted.\r
\r
  @return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
EFIAPI    \r
GetApicMsiValue (\r
  IN UINT8    Vector,\r
  IN UINTN    DeliveryMode,\r
  IN BOOLEAN  LevelTriggered,\r
  IN BOOLEAN  AssertionLevel\r
  );\r
  \r
#endif\r
\r
Commit	Line	Data
bf73cc4b	1	/** @file\r
	2	Public include file for Local APIC library.\r
	3	\r
	4	Local APIC library assumes local APIC is enabled. It does not\r
	5	handles cases where local APIC is disabled.\r
	6	\r
9c71e1e0	7	Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
bf73cc4b	8	This program and the accompanying materials\r
	9	are licensed and made available under the terms and conditions of the BSD License\r
	10	which accompanies this distribution. The full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	**/\r
	17	\r
	18	#ifndef __LOCAL_APIC_LIB_H__\r
	19	#define __LOCAL_APIC_LIB_H__\r
	20	\r
	21	#define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.\r
	22	#define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.\r
	23	\r
a66e0c7d	24	/**\r
	25	Retrieve the base address of local APIC.\r
	26	\r
	27	@return The base address of local APIC.\r
	28	\r
	29	**/\r
	30	UINTN\r
	31	EFIAPI\r
	32	GetLocalApicBaseAddress (\r
	33	VOID\r
	34	);\r
	35	\r
	36	/**\r
	37	Set the base address of local APIC.\r
	38	\r
	39	If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
	40	\r
	41	@param[in] BaseAddress Local APIC base address to be set.\r
	42	\r
	43	**/\r
	44	VOID\r
	45	EFIAPI\r
	46	SetLocalApicBaseAddress (\r
	47	IN UINTN BaseAddress\r
	48	);\r
	49	\r
bf73cc4b	50	/**\r
	51	Get the current local APIC mode.\r
	52	\r
	53	If local APIC is disabled, then ASSERT.\r
	54	\r
	55	@retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
	56	@retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
	57	**/\r
	58	UINTN\r
	59	EFIAPI\r
	60	GetApicMode (\r
	61	VOID\r
	62	);\r
	63	\r
	64	/**\r
	65	Set the current local APIC mode.\r
	66	\r
	67	If the specified local APIC mode is not valid, then ASSERT.\r
	68	If the specified local APIC mode can't be set as current, then ASSERT.\r
	69	\r
	70	@param ApicMode APIC mode to be set.\r
9c71e1e0 JF	71	\r
	72	@note This API must not be called from an interrupt handler or SMI handler.\r
	73	It may result in unpredictable behavior.\r
bf73cc4b	74	**/\r
	75	VOID\r
	76	EFIAPI\r
	77	SetApicMode (\r
	78	IN UINTN ApicMode\r
	79	);\r
	80	\r
	81	/**\r
	82	Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
	83	\r
6e3e4d70	84	In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
bf73cc4b	85	In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
	86	the 32-bit local APIC ID is returned as initial APIC ID.\r
	87	\r
	88	@return 32-bit initial local APIC ID of the executing processor.\r
	89	**/\r
	90	UINT32\r
	91	EFIAPI\r
	92	GetInitialApicId (\r
	93	VOID\r
	94	);\r
	95	\r
	96	/**\r
	97	Get the local APIC ID of the executing processor.\r
	98	\r
	99	@return 32-bit local APIC ID of the executing processor.\r
	100	**/\r
	101	UINT32\r
	102	EFIAPI\r
	103	GetApicId (\r
	104	VOID\r
	105	);\r
	106	\r
ae40aef1	107	/**\r
	108	Get the value of the local APIC version register.\r
	109	\r
	110	@return the value of the local APIC version register.\r
	111	**/\r
	112	UINT32\r
	113	EFIAPI\r
	114	GetApicVersion (\r
	115	VOID\r
	116	);\r
	117	\r
	118	/**\r
	119	Send a Fixed IPI to a specified target processor.\r
	120	\r
	121	This function returns after the IPI has been accepted by the target processor. \r
	122	\r
	123	@param ApicId The local APIC ID of the target processor.\r
	124	@param Vector The vector number of the interrupt being sent.\r
	125	**/\r
	126	VOID\r
	127	EFIAPI\r
	128	SendFixedIpi (\r
	129	IN UINT32 ApicId,\r
	130	IN UINT8 Vector\r
	131	);\r
	132	\r
	133	/**\r
	134	Send a Fixed IPI to all processors excluding self.\r
	135	\r
	136	This function returns after the IPI has been accepted by the target processors. \r
	137	\r
	138	@param Vector The vector number of the interrupt being sent.\r
	139	**/\r
	140	VOID\r
	141	EFIAPI\r
	142	SendFixedIpiAllExcludingSelf (\r
	143	IN UINT8 Vector\r
	144	);\r
	145	\r
bf73cc4b	146	/**\r
	147	Send a SMI IPI to a specified target processor.\r
	148	\r
	149	This function returns after the IPI has been accepted by the target processor. \r
	150	\r
	151	@param ApicId Specify the local APIC ID of the target processor.\r
	152	**/\r
	153	VOID\r
	154	EFIAPI\r
	155	SendSmiIpi (\r
	156	IN UINT32 ApicId\r
	157	);\r
	158	\r
	159	/**\r
	160	Send a SMI IPI to all processors excluding self.\r
	161	\r
	162	This function returns after the IPI has been accepted by the target processors. \r
	163	**/\r
	164	VOID\r
	165	EFIAPI\r
	166	SendSmiIpiAllExcludingSelf (\r
	167	VOID\r
	168	);\r
	169	\r
	170	/**\r
	171	Send an INIT IPI to a specified target processor.\r
	172	\r
	173	This function returns after the IPI has been accepted by the target processor. \r
	174	\r
	175	@param ApicId Specify the local APIC ID of the target processor.\r
	176	**/\r
	177	VOID\r
	178	EFIAPI\r
	179	SendInitIpi (\r
	180	IN UINT32 ApicId\r
	181	);\r
	182	\r
	183	/**\r
	184	Send an INIT IPI to all processors excluding self.\r
	185	\r
	186	This function returns after the IPI has been accepted by the target processors. \r
	187	**/\r
	188	VOID\r
	189	EFIAPI\r
	190	SendInitIpiAllExcludingSelf (\r
	191	VOID\r
	192	);\r
	193	\r
	194	/**\r
	195	Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
	196	\r
	197	This function returns after the IPI has been accepted by the target processor. \r
	198	\r
	199	if StartupRoutine >= 1M, then ASSERT.\r
	200	if StartupRoutine is not multiple of 4K, then ASSERT.\r
	201	\r
	202	@param ApicId Specify the local APIC ID of the target processor.\r
	203	@param StartupRoutine Points to a start-up routine which is below 1M physical\r
	204	address and 4K aligned.\r
	205	**/\r
	206	VOID\r
	207	EFIAPI\r
	208	SendInitSipiSipi (\r
	209	IN UINT32 ApicId,\r
210	IN UINT32 StartupRoutine\r
211	);\r
212	\r
213	/**\r
214	Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
215	\r
216	This function returns after the IPI has been accepted by the target processors. \r
217	\r
218	if StartupRoutine >= 1M, then ASSERT.\r
219	if StartupRoutine is not multiple of 4K, then ASSERT.\r
220	\r
221	@param StartupRoutine Points to a start-up routine which is below 1M physical\r
222	address and 4K aligned.\r
223	**/\r
224	VOID\r
225	EFIAPI\r
226	SendInitSipiSipiAllExcludingSelf (\r
227	IN UINT32 StartupRoutine\r
228	);\r
229	\r
230	/**\r
231	Programming Virtual Wire Mode.\r
232	\r
233	This function programs the local APIC for virtual wire mode following\r
234	the example described in chapter A.3 of the MP 1.4 spec.\r
235	\r
236	IOxAPIC is not involved in this type of virtual wire mode.\r
237	**/\r
238	VOID\r
239	EFIAPI\r
240	ProgramVirtualWireMode (\r
241	VOID\r
242	);\r
243	\r
b1b8c631	244	/**\r
	245	Disable LINT0 & LINT1 interrupts.\r
	246	\r
	247	This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
	248	**/\r
	249	VOID\r
	250	EFIAPI\r
	251	DisableLvtInterrupts (\r
	252	VOID\r
	253	);\r
	254	\r
bf73cc4b	255	/**\r
	256	Read the initial count value from the init-count register.\r
	257	\r
	258	@return The initial count value read from the init-count register.\r
	259	**/\r
	260	UINT32\r
	261	EFIAPI\r
	262	GetApicTimerInitCount (\r
	263	VOID\r
	264	);\r
	265	\r
	266	/**\r
	267	Read the current count value from the current-count register.\r
	268	\r
	269	@return The current count value read from the current-count register.\r
	270	**/\r
	271	UINT32\r
	272	EFIAPI\r
	273	GetApicTimerCurrentCount (\r
	274	VOID\r
	275	);\r
	276	\r
	277	/**\r
	278	Initialize the local APIC timer.\r
	279	\r
	280	The local APIC timer is initialized and enabled.\r
	281	\r
	282	@param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
	283	If it is 0, then use the current divide value in the DCR.\r
	284	@param InitCount The initial count value.\r
	285	@param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
	286	@param Vector The timer interrupt vector number.\r
	287	**/\r
	288	VOID\r
	289	EFIAPI\r
	290	InitializeApicTimer (\r
	291	IN UINTN DivideValue,\r
	292	IN UINT32 InitCount,\r
	293	IN BOOLEAN PeriodicMode,\r
	294	IN UINT8 Vector\r
	295	);\r
	296	\r
ae40aef1	297	/**\r
	298	Get the state of the local APIC timer.\r
	299	\r
	300	@param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
	301	@param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
	302	@param Vector Return the timer interrupt vector number.\r
	303	**/\r
	304	VOID\r
	305	EFIAPI\r
	306	GetApicTimerState (\r
	307	OUT UINTN *DivideValue OPTIONAL,\r
	308	OUT BOOLEAN *PeriodicMode OPTIONAL,\r
	309	OUT UINT8 *Vector OPTIONAL\r
	310	);\r
	311	\r
bf73cc4b	312	/**\r
	313	Enable the local APIC timer interrupt.\r
	314	**/\r
	315	VOID\r
	316	EFIAPI\r
	317	EnableApicTimerInterrupt (\r
	318	VOID\r
	319	);\r
	320	\r
	321	/**\r
	322	Disable the local APIC timer interrupt.\r
	323	**/\r
	324	VOID\r
	325	EFIAPI\r
	326	DisableApicTimerInterrupt (\r
	327	VOID\r
	328	);\r
	329	\r
	330	/**\r
	331	Get the local APIC timer interrupt state.\r
	332	\r
	333	@retval TRUE The local APIC timer interrupt is enabled.\r
	334	@retval FALSE The local APIC timer interrupt is disabled.\r
	335	**/\r
	336	BOOLEAN\r
	337	EFIAPI\r
	338	GetApicTimerInterruptState (\r
	339	VOID\r
	340	);\r
	341	\r
	342	/**\r
	343	Send EOI to the local APIC.\r
	344	**/\r
	345	VOID\r
	346	EFIAPI\r
	347	SendApicEoi (\r
	348	VOID\r
	349	);\r
	350	\r
5f867ad0	351	/**\r
	352	Get the 32-bit address that a device should use to send a Message Signaled \r
	353	Interrupt (MSI) to the Local APIC of the currently executing processor.\r
	354	\r
	355	@return 32-bit address used to send an MSI to the Local APIC.\r
	356	**/\r
	357	UINT32\r
	358	EFIAPI \r
	359	GetApicMsiAddress (\r
	360	VOID\r
	361	);\r
	362	\r
	363	/**\r
	364	Get the 64-bit data value that a device should use to send a Message Signaled \r
	365	Interrupt (MSI) to the Local APIC of the currently executing processor.\r
	366	\r
	367	If Vector is not in range 0x10..0xFE, then ASSERT().\r
	368	If DeliveryMode is not supported, then ASSERT().\r
	369	\r
	370	@param Vector The 8-bit interrupt vector associated with the MSI. \r
	371	Must be in the range 0x10..0xFE\r
	372	@param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
	373	is handled. The only supported values are:\r
	374	0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
	375	1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
	376	2: LOCAL_APIC_DELIVERY_MODE_SMI\r
	377	4: LOCAL_APIC_DELIVERY_MODE_NMI\r
	378	5: LOCAL_APIC_DELIVERY_MODE_INIT\r
	379	7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
	380	\r
	381	@param LevelTriggered TRUE specifies a level triggered interrupt. \r
	382	FALSE specifies an edge triggered interrupt.\r
	383	@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
	384	TRUE specifies a level triggered interrupt that active \r
	385	when the interrupt line is asserted.\r
	386	FALSE specifies a level triggered interrupt that active \r
	387	when the interrupt line is deasserted.\r
	388	\r
	389	@return 64-bit data value used to send an MSI to the Local APIC.\r
	390	**/\r
	391	UINT64\r
	392	EFIAPI \r
	393	GetApicMsiValue (\r
	394	IN UINT8 Vector,\r
	395	IN UINTN DeliveryMode,\r
	396	IN BOOLEAN LevelTriggered,\r
	397	IN BOOLEAN AssertionLevel\r
	398	);\r
	399	\r
bf73cc4b	400	#endif\r
bf73cc4b	401	\r