UefiCpuPkg/Cpuid: Remove wrong while-loop check after for-loop
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Cpuid.h
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28a7ddf0 1/** @file\r
57d16ba1 2 CPUID leaf definitions.\r
28a7ddf0 3\r
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4 Provides defines for CPUID leaf indexes. Data structures are provided for\r
5 registers returned by a CPUID leaf that contain one or more bit fields.\r
6 If a register returned is a single 32-bit value, then a data structure is\r
7 not provided for that register.\r
28a7ddf0 8\r
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9 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials are licensed and made available under\r
11 the terms and conditions of the BSD License which accompanies this distribution.\r
12 The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
28a7ddf0 14\r
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15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r
20 December 2015, CPUID instruction.\r
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21\r
22**/\r
23\r
24#ifndef __CPUID_H__\r
25#define __CPUID_H__\r
26\r
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27/**\r
28 CPUID Signature Information\r
29\r
30 @param EAX CPUID_SIGNATURE (0x00)\r
31\r
32 @retval EAX Returns the highest value the CPUID instruction recognizes for\r
33 returning basic processor information. The value is returned is\r
34 processor specific.\r
35 @retval EBX First 4 characters of a vendor identification string.\r
36 @retval ECX Last 4 characters of a vendor identification string.\r
37 @retval EDX Middle 4 characters of a vendor identification string.\r
38\r
39 <b>Example usage</b>\r
40 @code\r
41 UINT32 Eax;\r
42 UINT32 Ebx;\r
43 UINT32 Ecx;\r
44 UINT32 Edx;\r
45\r
46 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
47 @endcode\r
48**/\r
49#define CPUID_SIGNATURE 0x00\r
50\r
51///\r
52/// @{ CPUID signature values returned by Intel processors\r
53///\r
54#define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')\r
55#define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')\r
56#define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')\r
57///\r
58/// @}\r
59///\r
60\r
61\r
62/**\r
63 CPUID Version Information\r
64\r
65 @param EAX CPUID_VERSION_INFO (0x01)\r
66\r
67 @retval EAX Returns Model, Family, Stepping Information described by the\r
68 type CPUID_VERSION_INFO_EAX.\r
69 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by\r
70 the type CPUID_VERSION_INFO_EBX.\r
71 @retval ECX CPU Feature Information described by the type\r
72 CPUID_VERSION_INFO_ECX.\r
73 @retval EDX CPU Feature Information described by the type\r
74 CPUID_VERSION_INFO_EDX.\r
75\r
76 <b>Example usage</b>\r
77 @code\r
78 CPUID_VERSION_INFO_EAX Eax;\r
79 CPUID_VERSION_INFO_EBX Ebx;\r
80 CPUID_VERSION_INFO_ECX Ecx;\r
81 CPUID_VERSION_INFO_EDX Edx;\r
82\r
83 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
84 @endcode\r
85**/\r
86#define CPUID_VERSION_INFO 0x01\r
87\r
88/**\r
89 CPUID Version Information returned in EAX for CPUID leaf\r
90 #CPUID_VERSION_INFO.\r
91**/\r
92typedef union {\r
93 ///\r
94 /// Individual bit fields\r
95 ///\r
96 struct {\r
97 UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID\r
98 UINT32 Model:4; ///< [Bits 7:4] Model\r
99 UINT32 FamilyId:4; ///< [Bits 11:8] Family\r
100 UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type\r
101 UINT32 Reserved1:2; ///< [Bits 15:14] Reserved\r
102 UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID\r
103 UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID\r
104 UINT32 Reserved2:4; ///< Reserved\r
105 } Bits;\r
106 ///\r
107 /// All bit fields as a 32-bit value\r
108 ///\r
109 UINT32 Uint32;\r
110} CPUID_VERSION_INFO_EAX;\r
111\r
112///\r
113/// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType\r
114///\r
115#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00\r
116#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01\r
117#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02\r
118///\r
119/// @}\r
120///\r
121\r
122/**\r
123 CPUID Version Information returned in EBX for CPUID leaf\r
124 #CPUID_VERSION_INFO.\r
125**/\r
126typedef union {\r
127 ///\r
128 /// Individual bit fields\r
129 ///\r
130 struct {\r
131 ///\r
132 /// [Bits 7:0] Provides an entry into a brand string table that contains\r
133 /// brand strings for IA-32 processors.\r
134 ///\r
135 UINT32 BrandIndex:8;\r
136 ///\r
137 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH\r
138 /// and CLFLUSHOPT instructions in 8-byte increments. This field was\r
139 /// introduced in the Pentium 4 processor.\r
140 ///\r
141 UINT32 CacheLineSize:8;\r
142 ///\r
143 /// [Bits 23:16] Maximum number of addressable IDs for logical processors\r
144 /// in this physical package.\r
145 ///\r
146 /// @note\r
147 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is\r
148 /// the number of unique initial APICIDs reserved for addressing different\r
149 /// logical processors in a physical package. This field is only valid if\r
150 /// CPUID.1.EDX.HTT[bit 28]= 1.\r
151 ///\r
152 UINT32 MaximumAddressableIdsForLogicalProcessors:8;\r
153 ///\r
154 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the\r
155 /// processor during power up. This field was introduced in the Pentium 4\r
156 /// processor.\r
157 ///\r
158 UINT32 InitialLocalApicId:8;\r
159 } Bits;\r
160 ///\r
161 /// All bit fields as a 32-bit value\r
162 ///\r
163 UINT32 Uint32;\r
164} CPUID_VERSION_INFO_EBX;\r
165\r
166/**\r
167 CPUID Version Information returned in ECX for CPUID leaf\r
168 #CPUID_VERSION_INFO.\r
169**/\r
170typedef union {\r
171 ///\r
172 /// Individual bit fields\r
173 ///\r
174 struct {\r
175 ///\r
176 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the\r
177 /// processor supports this technology\r
178 ///\r
179 UINT32 SSE3:1;\r
180 ///\r
181 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ\r
182 /// instruction. Carryless Multiplication\r
183 ///\r
184 UINT32 PCLMULQDQ:1;\r
185 ///\r
186 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports\r
187 /// DS area using 64-bit layout.\r
188 ///\r
189 UINT32 DTES64:1;\r
190 ///\r
191 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports\r
192 /// this feature.\r
193 ///\r
194 UINT32 MONITOR:1;\r
195 ///\r
196 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor\r
197 /// supports the extensions to the Debug Store feature to allow for branch\r
198 /// message storage qualified by CPL\r
199 ///\r
200 UINT32 DS_CPL:1;\r
201 ///\r
202 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the\r
203 /// processor supports this technology.\r
204 ///\r
205 UINT32 VMX:1;\r
206 ///\r
207 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor\r
208 /// supports this technology\r
209 ///\r
210 UINT32 SMX:1;\r
211 ///\r
212 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates\r
213 /// that the processor supports this technology\r
214 ///\r
215 UINT32 EIST:1;\r
216 ///\r
217 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor\r
218 /// supports this technology\r
219 ///\r
220 UINT32 TM2:1;\r
221 ///\r
222 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming\r
223 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction\r
224 /// extensions are not present in the processor.\r
225 ///\r
226 UINT32 SSSE3:1;\r
227 ///\r
228 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode\r
229 /// can be set to either adaptive mode or shared mode. A value of 0 indicates\r
230 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR\r
231 /// Bit 24 (L1 Data Cache Context Mode) for details\r
232 ///\r
233 UINT32 CNXT_ID:1;\r
234 ///\r
235 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE\r
236 /// MSR for silicon debug\r
237 ///\r
238 UINT32 SDBG:1;\r
239 ///\r
240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple\r
241 /// Add) extensions using YMM state.\r
242 ///\r
243 UINT32 FMA:1;\r
244 ///\r
245 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature\r
246 /// is available.\r
247 ///\r
248 UINT32 CMPXCHG16B:1;\r
249 ///\r
250 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor\r
251 /// supports changing IA32_MISC_ENABLE[Bit 23].\r
252 ///\r
253 UINT32 xTPR_Update_Control:1;\r
254 ///\r
255 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the\r
256 /// processor supports the performance and debug feature indication MSR\r
257 /// IA32_PERF_CAPABILITIES.\r
258 ///\r
259 UINT32 PDCM:1;\r
260 UINT32 Reserved:1;\r
261 ///\r
262 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the\r
263 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.\r
264 ///\r
265 UINT32 PCID:1;\r
266 ///\r
267 /// [Bit 18] A value of 1 indicates the processor supports the ability to\r
268 /// prefetch data from a memory mapped device. Direct Cache Access.\r
269 ///\r
270 UINT32 DCA:1;\r
271 ///\r
272 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.\r
273 ///\r
274 UINT32 SSE4_1:1;\r
275 ///\r
276 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.\r
277 ///\r
278 UINT32 SSE4_2:1;\r
279 ///\r
280 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC\r
281 /// feature.\r
282 ///\r
283 UINT32 x2APIC:1;\r
284 ///\r
285 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE\r
286 /// instruction.\r
287 ///\r
288 UINT32 MOVBE:1;\r
289 ///\r
290 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT\r
291 /// instruction.\r
292 ///\r
293 UINT32 POPCNT:1;\r
294 ///\r
295 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer\r
296 /// supports one-shot operation using a TSC deadline value.\r
297 ///\r
298 UINT32 TSC_Deadline:1;\r
299 ///\r
300 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI\r
301 /// instruction extensions.\r
302 ///\r
303 UINT32 AESNI:1;\r
304 ///\r
305 /// [Bit 26] A value of 1 indicates that the processor supports the\r
306 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV\r
307 /// instructions, and XCR0.\r
308 ///\r
309 UINT32 XSAVE:1;\r
310 ///\r
311 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]\r
312 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support\r
313 /// processor extended state management using XSAVE/XRSTOR.\r
314 ///\r
315 UINT32 OSXSAVE:1;\r
316 ///\r
317 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction\r
318 /// extensions.\r
319 ///\r
320 UINT32 AVX:1;\r
321 ///\r
322 /// [Bit 29] A value of 1 indicates that processor supports 16-bit\r
323 /// floating-point conversion instructions.\r
324 ///\r
325 UINT32 F16C:1;\r
326 ///\r
327 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.\r
328 ///\r
329 UINT32 RDRAND:1;\r
330 ///\r
331 /// [Bit 31] Always returns 0.\r
332 ///\r
333 UINT32 NotUsed:1;\r
334 } Bits;\r
335 ///\r
336 /// All bit fields as a 32-bit value\r
337 ///\r
338 UINT32 Uint32;\r
339} CPUID_VERSION_INFO_ECX;\r
340\r
341/**\r
342 CPUID Version Information returned in EDX for CPUID leaf\r
343 #CPUID_VERSION_INFO.\r
344**/\r
345typedef union {\r
346 ///\r
347 /// Individual bit fields\r
348 ///\r
349 struct {\r
350 ///\r
351 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.\r
352 ///\r
353 UINT32 FPU:1;\r
354 ///\r
355 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,\r
356 /// including CR4.VME for controlling the feature, CR4.PVI for protected\r
357 /// mode virtual interrupts, software interrupt indirection, expansion of\r
358 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and\r
359 /// EFLAGS.VIP flags.\r
360 ///\r
361 UINT32 VME:1;\r
362 ///\r
363 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including\r
364 /// CR4.DE for controlling the feature, and optional trapping of accesses to\r
365 /// DR4 and DR5.\r
366 ///\r
367 UINT32 DE:1;\r
368 ///\r
369 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,\r
370 /// including CR4.PSE for controlling the feature, the defined dirty bit in\r
371 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,\r
372 /// PDEs, and PTEs.\r
373 ///\r
374 UINT32 PSE:1;\r
375 ///\r
376 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,\r
377 /// including CR4.TSD for controlling privilege.\r
378 ///\r
379 UINT32 TSC:1;\r
380 ///\r
381 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The\r
382 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are\r
383 /// implementation dependent.\r
384 ///\r
385 UINT32 MSR:1;\r
386 ///\r
387 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32\r
388 /// bits are supported: extended page table entry formats, an extra level in\r
389 /// the page translation tables is defined, 2-MByte pages are supported\r
390 /// instead of 4 Mbyte pages if PAE bit is 1.\r
391 ///\r
392 UINT32 PAE:1;\r
393 ///\r
394 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine\r
395 /// Checks, including CR4.MCE for controlling the feature. This feature does\r
396 /// not define the model-specific implementations of machine-check error\r
397 /// logging, reporting, and processor shutdowns. Machine Check exception\r
398 /// handlers may have to depend on processor version to do model specific\r
399 /// processing of the exception, or test for the presence of the Machine\r
400 /// Check feature.\r
401 ///\r
402 UINT32 MCE:1;\r
403 ///\r
404 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)\r
405 /// instruction is supported (implicitly locked and atomic).\r
406 ///\r
407 UINT32 CX8:1;\r
408 ///\r
409 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable\r
410 /// Interrupt Controller (APIC), responding to memory mapped commands in the\r
411 /// physical address range FFFE0000H to FFFE0FFFH (by default - some\r
412 /// processors permit the APIC to be relocated).\r
413 ///\r
414 UINT32 APIC:1;\r
415 UINT32 Reserved1:1;\r
416 ///\r
417 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT\r
418 /// and associated MSRs are supported.\r
419 ///\r
420 UINT32 SEP:1;\r
421 ///\r
422 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap\r
423 /// MSR contains feature bits that describe what memory types are supported,\r
424 /// how many variable MTRRs are supported, and whether fixed MTRRs are\r
425 /// supported.\r
426 ///\r
427 UINT32 MTRR:1;\r
428 ///\r
429 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure\r
430 /// entries that map a page, indicating TLB entries that are common to\r
431 /// different processes and need not be flushed. The CR4.PGE bit controls\r
432 /// this feature.\r
433 ///\r
434 UINT32 PGE:1;\r
435 ///\r
436 /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,\r
437 /// which provides a compatible mechanism for error reporting in P6 family,\r
438 /// Pentium 4, Intel Xeon processors, and future processors, is supported.\r
439 /// The MCG_CAP MSR contains feature bits describing how many banks of error\r
440 /// reporting MSRs are supported.\r
441 ///\r
442 UINT32 MCA:1;\r
443 ///\r
444 /// [Bit 15] Conditional Move Instructions. The conditional move instruction\r
445 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the\r
446 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.\r
447 ///\r
448 UINT32 CMOV:1;\r
449 ///\r
450 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This\r
451 /// feature augments the Memory Type Range Registers (MTRRs), allowing an\r
452 /// operating system to specify attributes of memory accessed through a\r
453 /// linear address on a 4KB granularity.\r
454 ///\r
455 UINT32 PAT:1;\r
456 ///\r
457 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical\r
458 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature\r
459 /// indicates that upper bits of the physical address of a 4-MByte page are\r
460 /// encoded in bits 20:13 of the page-directory entry. Such physical\r
461 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.\r
462 ///\r
463 UINT32 PSE_36:1;\r
464 ///\r
465 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit\r
466 /// processor identification number feature and the feature is enabled.\r
467 ///\r
468 UINT32 PSN:1;\r
469 ///\r
470 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.\r
471 ///\r
472 UINT32 CLFSH:1;\r
473 UINT32 Reserved2:1;\r
474 ///\r
475 /// [Bit 21] Debug Store. The processor supports the ability to write debug\r
476 /// information into a memory resident buffer. This feature is used by the\r
477 /// branch trace store (BTS) and precise event-based sampling (PEBS)\r
478 /// facilities.\r
479 ///\r
480 UINT32 DS:1;\r
481 ///\r
482 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The\r
483 /// processor implements internal MSRs that allow processor temperature to\r
484 /// be monitored and processor performance to be modulated in predefined\r
485 /// duty cycles under software control.\r
486 ///\r
487 UINT32 ACPI:1;\r
488 ///\r
489 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX\r
490 /// technology.\r
491 ///\r
492 UINT32 MMX:1;\r
493 ///\r
494 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR\r
495 /// instructions are supported for fast save and restore of the floating\r
496 /// point context. Presence of this bit also indicates that CR4.OSFXSR is\r
497 /// available for an operating system to indicate that it supports the\r
498 /// FXSAVE and FXRSTOR instructions.\r
499 ///\r
500 UINT32 FXSR:1;\r
501 ///\r
502 /// [Bit 25] SSE. The processor supports the SSE extensions.\r
503 ///\r
504 UINT32 SSE:1;\r
505 ///\r
506 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.\r
507 ///\r
508 UINT32 SSE2:1;\r
509 ///\r
510 /// [Bit 27] Self Snoop. The processor supports the management of\r
511 /// conflicting memory types by performing a snoop of its own cache\r
512 /// structure for transactions issued to the bus.\r
513 ///\r
514 UINT32 SS:1;\r
515 ///\r
516 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT\r
517 /// indicates there is only a single logical processor in the package and\r
518 /// software should assume only a single APIC ID is reserved. A value of 1\r
519 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of\r
520 /// addressable IDs for logical processors in this package) is valid for the\r
521 /// package.\r
522 ///\r
523 UINT32 HTT:1;\r
524 ///\r
525 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor\r
526 /// automatic thermal control circuitry (TCC).\r
527 ///\r
528 UINT32 TM:1;\r
529 UINT32 Reserved3:1;\r
530 ///\r
531 /// [Bit 31] Pending Break Enable. The processor supports the use of the\r
532 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is\r
533 /// asserted) to signal the processor that an interrupt is pending and that\r
534 /// the processor should return to normal operation to handle the interrupt.\r
535 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.\r
536 ///\r
537 UINT32 PBE:1;\r
538 } Bits;\r
539 ///\r
540 /// All bit fields as a 32-bit value\r
541 ///\r
542 UINT32 Uint32;\r
543} CPUID_VERSION_INFO_EDX;\r
544\r
545\r
546/**\r
547 CPUID Cache and TLB Information\r
548\r
549 @param EAX CPUID_CACHE_INFO (0x02)\r
550\r
551 @retval EAX Cache and TLB Information described by the type\r
552 CPUID_CACHE_INFO_CACHE_TLB.\r
553 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns\r
554 0x01 and must be ignored. Only valid if\r
555 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
556 @retval EBX Cache and TLB Information described by the type\r
557 CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
558 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
559 @retval ECX Cache and TLB Information described by the type\r
560 CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
561 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
562 @retval EDX Cache and TLB Information described by the type\r
563 CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
564 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
565\r
566 <b>Example usage</b>\r
567 @code\r
568 CPUID_CACHE_INFO_CACHE_TLB Eax;\r
569 CPUID_CACHE_INFO_CACHE_TLB Ebx;\r
570 CPUID_CACHE_INFO_CACHE_TLB Ecx;\r
571 CPUID_CACHE_INFO_CACHE_TLB Edx;\r
572\r
573 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
574 @endcode\r
575\r
576 <b>Cache Descriptor values</b>\r
577 <table>\r
578 <tr><th>Value </th><th> Type </th><th> Description </th></tr>\r
579 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>\r
580 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>\r
581 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>\r
582 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>\r
583 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>\r
584 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
585 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,\r
586 32 byte line size</td></tr>\r
587 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,\r
588 32 byte line size</td></tr>\r
589 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,\r
590 64 byte line size</td></tr>\r
591 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>\r
592 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>\r
593 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
594 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>\r
595 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>\r
596 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>\r
597 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>\r
598 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,\r
599 2 lines per sector</td></tr>\r
600 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,\r
601 2 lines per sector</td></tr>\r
602 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>\r
603 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,\r
604 2 lines per sector</td></tr>\r
605 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,\r
606 2 lines per sector</td></tr>\r
607 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,\r
608 64 byte line size</td></tr>\r
609 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,\r
610 64 byte line size</td></tr>\r
611 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,\r
612 no 3rd-level cache</td></tr>\r
613 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
614 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
615 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
616 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>\r
617 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>\r
618 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>\r
619 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>\r
620 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>\r
621 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size\r
622 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>\r
623 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r
624 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>\r
625 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>\r
626 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>\r
627 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>\r
628 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>\r
629 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>\r
630 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>\r
631 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>\r
632 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>\r
633 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>\r
634 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r
635 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r
636 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r
637 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
638 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r
639 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r
640 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r
641 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r
642 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r
643 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>\r
644 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r
645 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r
646 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r
647 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>\r
648 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>\r
649 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>\r
650 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>\r
651 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>\r
652 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>\r
653 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>\r
654 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>\r
655 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>\r
656 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,\r
657 2 lines per sector</td></tr>\r
658 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,\r
659 2 lines per sector</td></tr>\r
660 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,\r
661 2 lines per sector</td></tr>\r
662 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,\r
663 2 lines per sector</td></tr>\r
664 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>\r
665 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>\r
666 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>\r
667 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>\r
668 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>\r
669 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>\r
670 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>\r
671 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
672 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r
673 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>\r
674 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r
675 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>\r
676 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>\r
677 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r
678 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>\r
679 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>\r
680 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,\r
681 128 entries</td></tr>\r
682 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>\r
683 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>\r
684 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,\r
685 1024 entries</td></tr>\r
686 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r
687 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r
688 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r
689 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r
690 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
691 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r
692 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>\r
693 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r
694 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>\r
695 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>\r
696 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>\r
697 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>\r
698 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>\r
699 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>\r
700 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r
701 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>\r
702 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>\r
703 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>\r
704 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>\r
705 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>\r
706 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>\r
707 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,\r
708 use CPUID leaf 4 to query cache parameters</td></tr>\r
709 </table>\r
710**/\r
711#define CPUID_CACHE_INFO 0x02\r
712\r
713/**\r
714 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID\r
715 leaf #CPUID_CACHE_INFO.\r
716**/\r
717typedef union {\r
718 ///\r
719 /// Individual bit fields\r
720 ///\r
721 struct {\r
722 UINT32 Reserved:31;\r
723 ///\r
724 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.\r
725 /// if 1, then none of the cache descriptor bytes in the register are valid.\r
726 ///\r
727 UINT32 NotValid:1;\r
728 } Bits;\r
729 ///\r
730 /// Array of Cache and TLB descriptor bytes\r
731 ///\r
732 UINT8 CacheDescriptor[4];\r
733 ///\r
734 /// All bit fields as a 32-bit value\r
735 ///\r
736 UINT32 Uint32;\r
737} CPUID_CACHE_INFO_CACHE_TLB;\r
738\r
739\r
740/**\r
741 CPUID Processor Serial Number\r
742\r
743 Processor serial number (PSN) is not supported in the Pentium 4 processor\r
744 or later. On all models, use the PSN flag (returned using CPUID) to check\r
745 for PSN support before accessing the feature.\r
746\r
747 @param EAX CPUID_SERIAL_NUMBER (0x03)\r
748\r
749 @retval EAX Reserved.\r
750 @retval EBX Reserved.\r
751 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in\r
752 Pentium III processor only; otherwise, the value in this\r
753 register is reserved.)\r
754 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in\r
755 Pentium III processor only; otherwise, the value in this\r
756 register is reserved.)\r
757\r
758 <b>Example usage</b>\r
759 @code\r
760 UINT32 Ecx;\r
761 UINT32 Edx;\r
762\r
763 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r
764 @endcode\r
765**/\r
766#define CPUID_SERIAL_NUMBER 0x03\r
767\r
768\r
769/**\r
770 CPUID Cache Parameters\r
771\r
772 @param EAX CPUID_CACHE_PARAMS (0x04)\r
773 @param ECX Cache Level. Valid values start at 0. Software can enumerate\r
774 the deterministic cache parameters for each level of the cache\r
775 hierarchy starting with an index value of 0, until the\r
776 parameters report the value associated with the CacheType\r
777 field in CPUID_CACHE_PARAMS_EAX is 0.\r
778\r
779 @retval EAX Returns cache type information described by the type\r
780 CPUID_CACHE_PARAMS_EAX.\r
781 @retval EBX Returns cache line and associativity information described by\r
782 the type CPUID_CACHE_PARAMS_EBX.\r
783 @retval ECX Returns the number of sets in the cache.\r
784 @retval EDX Returns cache WINVD/INVD behavior described by the type\r
785 CPUID_CACHE_PARAMS_EDX.\r
786\r
787 <b>Example usage</b>\r
788 @code\r
789 UINT32 CacheLevel;\r
790 CPUID_CACHE_PARAMS_EAX Eax;\r
791 CPUID_CACHE_PARAMS_EBX Ebx;\r
792 UINT32 Ecx;\r
793 CPUID_CACHE_PARAMS_EDX Edx;\r
794\r
795 CacheLevel = 0;\r
796 do {\r
797 AsmCpuidEx (\r
798 CPUID_CACHE_PARAMS, CacheLevel,\r
799 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
800 );\r
801 CacheLevel++;\r
802 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
803 @endcode\r
804**/\r
805#define CPUID_CACHE_PARAMS 0x04\r
806\r
807/**\r
808 CPUID Cache Parameters Information returned in EAX for CPUID leaf\r
809 #CPUID_CACHE_PARAMS.\r
810**/\r
811typedef union {\r
812 ///\r
813 /// Individual bit fields\r
814 ///\r
815 struct {\r
816 ///\r
817 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,\r
818 /// then there is no information for the requested cache level.\r
819 ///\r
820 UINT32 CacheType:5;\r
821 ///\r
822 /// [Bits 7:5] Cache level (Starts at 1).\r
823 ///\r
824 UINT32 CacheLevel:3;\r
825 ///\r
826 /// [Bit 8] Self Initializing cache level (does not need SW initialization).\r
827 ///\r
828 UINT32 SelfInitializingCache:1;\r
829 ///\r
830 /// [Bit 9] Fully Associative cache.\r
831 ///\r
832 UINT32 FullyAssociativeCache:1;\r
833 ///\r
834 /// [Bits 13:10] Reserved.\r
835 ///\r
836 UINT32 Reserved:4;\r
837 ///\r
838 /// [Bits 25:14] Maximum number of addressable IDs for logical processors\r
839 /// sharing this cache.\r
840 ///\r
841 /// Add one to the return value to get the result.\r
842 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])\r
843 /// is the number of unique initial APIC IDs reserved for addressing\r
844 /// different logical processors sharing this cache.\r
845 ///\r
846 UINT32 MaximumAddressableIdsForLogicalProcessors:12;\r
847 ///\r
848 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in\r
849 /// the physical package.\r
850 ///\r
851 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])\r
852 /// is the number of unique Core_IDs reserved for addressing different\r
853 /// processor cores in a physical package. Core ID is a subset of bits of\r
854 /// the initial APIC ID.\r
855 /// The returned value is constant for valid initial values in ECX. Valid\r
856 /// ECX values start from 0.\r
857 ///\r
858 UINT32 MaximumAddressableIdsForProcessorCores:6;\r
859 } Bits;\r
860 ///\r
861 /// All bit fields as a 32-bit value\r
862 ///\r
863 UINT32 Uint32;\r
864} CPUID_CACHE_PARAMS_EAX;\r
865\r
866///\r
867/// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType\r
868///\r
869#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00\r
870#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01\r
871#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02\r
872#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03\r
873///\r
874/// @}\r
875///\r
876\r
877/**\r
878 CPUID Cache Parameters Information returned in EBX for CPUID leaf\r
879 #CPUID_CACHE_PARAMS.\r
880**/\r
881typedef union {\r
882 ///\r
883 /// Individual bit fields\r
884 ///\r
885 struct {\r
886 ///\r
887 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to\r
888 /// get the result.\r
889 ///\r
890 UINT32 LineSize:12;\r
891 ///\r
892 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to\r
893 /// get the result.\r
894 ///\r
895 UINT32 LinePartitions:10;\r
896 ///\r
897 /// [Bits 31:22] Ways of associativity. Add one to the return value to get\r
898 /// the result.\r
899 ///\r
900 UINT32 Ways:10;\r
901 } Bits;\r
902 ///\r
903 /// All bit fields as a 32-bit value\r
904 ///\r
905 UINT32 Uint32;\r
906} CPUID_CACHE_PARAMS_EBX;\r
907\r
908/**\r
909 CPUID Cache Parameters Information returned in EDX for CPUID leaf\r
910 #CPUID_CACHE_PARAMS.\r
911**/\r
912typedef union {\r
913 ///\r
914 /// Individual bit fields\r
915 ///\r
916 struct {\r
917 ///\r
918 /// [Bit 0] Write-Back Invalidate/Invalidate.\r
919 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level\r
920 /// caches for threads sharing this cache.\r
921 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of\r
922 /// non-originating threads sharing this cache.\r
923 ///\r
924 UINT32 Invalidate:1;\r
925 ///\r
926 /// [Bit 1] Cache Inclusiveness.\r
927 /// 0 = Cache is not inclusive of lower cache levels.\r
928 /// 1 = Cache is inclusive of lower cache levels.\r
929 ///\r
930 UINT32 CacheInclusiveness:1;\r
931 ///\r
932 /// [Bit 2] Complex Cache Indexing.\r
933 /// 0 = Direct mapped cache.\r
934 /// 1 = A complex function is used to index the cache, potentially using all\r
935 /// address bits.\r
936 ///\r
937 UINT32 ComplexCacheIndexing:1;\r
938 UINT32 Reserved:29;\r
939 } Bits;\r
940 ///\r
941 /// All bit fields as a 32-bit value\r
942 ///\r
943 UINT32 Uint32;\r
944} CPUID_CACHE_PARAMS_EDX;\r
945\r
946\r
947/**\r
948 CPUID MONITOR/MWAIT Information\r
949\r
950 @param EAX CPUID_MONITOR_MWAIT (0x05)\r
951\r
952 @retval EAX Smallest monitor-line size in bytes described by the type\r
953 CPUID_MONITOR_MWAIT_EAX.\r
954 @retval EBX Largest monitor-line size in bytes described by the type\r
955 CPUID_MONITOR_MWAIT_EBX.\r
956 @retval ECX Enumeration of Monitor-Mwait extensions support described by\r
957 the type CPUID_MONITOR_MWAIT_ECX.\r
958 @retval EDX Sub C-states supported described by the type\r
959 CPUID_MONITOR_MWAIT_EDX.\r
960\r
961 <b>Example usage</b>\r
962 @code\r
963 CPUID_MONITOR_MWAIT_EAX Eax;\r
964 CPUID_MONITOR_MWAIT_EBX Ebx;\r
965 CPUID_MONITOR_MWAIT_ECX Ecx;\r
966 CPUID_MONITOR_MWAIT_EDX Edx;\r
967\r
968 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
969 @endcode\r
970**/\r
971#define CPUID_MONITOR_MWAIT 0x05\r
972\r
973/**\r
974 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf\r
975 #CPUID_MONITOR_MWAIT.\r
976**/\r
977typedef union {\r
978 ///\r
979 /// Individual bit fields\r
980 ///\r
981 struct {\r
982 ///\r
983 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's\r
984 /// monitor granularity).\r
985 ///\r
986 UINT32 SmallestMonitorLineSize:16;\r
987 UINT32 Reserved:16;\r
988 } Bits;\r
989 ///\r
990 /// All bit fields as a 32-bit value\r
991 ///\r
992 UINT32 Uint32;\r
993} CPUID_MONITOR_MWAIT_EAX;\r
994\r
995/**\r
996 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf\r
997 #CPUID_MONITOR_MWAIT.\r
998**/\r
999typedef union {\r
1000 ///\r
1001 /// Individual bit fields\r
1002 ///\r
1003 struct {\r
1004 ///\r
1005 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's\r
1006 /// monitor granularity).\r
1007 ///\r
1008 UINT32 LargestMonitorLineSize:16;\r
1009 UINT32 Reserved:16;\r
1010 } Bits;\r
1011 ///\r
1012 /// All bit fields as a 32-bit value\r
1013 ///\r
1014 UINT32 Uint32;\r
1015} CPUID_MONITOR_MWAIT_EBX;\r
1016\r
1017/**\r
1018 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf\r
1019 #CPUID_MONITOR_MWAIT.\r
1020**/\r
1021typedef union {\r
1022 ///\r
1023 /// Individual bit fields\r
1024 ///\r
1025 struct {\r
1026 ///\r
1027 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,\r
1028 /// and EDX are valid.\r
1029 ///\r
1030 UINT32 ExtensionsSupported:1;\r
1031 ///\r
1032 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when\r
1033 /// interrupts disabled.\r
1034 ///\r
1035 UINT32 InterruptAsBreak:1;\r
1036 UINT32 Reserved:30;\r
1037 } Bits;\r
1038 ///\r
1039 /// All bit fields as a 32-bit value\r
1040 ///\r
1041 UINT32 Uint32;\r
1042} CPUID_MONITOR_MWAIT_ECX;\r
1043\r
1044/**\r
1045 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf\r
1046 #CPUID_MONITOR_MWAIT.\r
1047\r
1048 @note\r
1049 The definition of C0 through C7 states for MWAIT extension are\r
1050 processor-specific C-states, not ACPI C-states.\r
1051**/\r
1052typedef union {\r
1053 ///\r
1054 /// Individual bit fields\r
1055 ///\r
1056 struct {\r
1057 ///\r
1058 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.\r
1059 ///\r
1060 UINT32 C0States:4;\r
1061 ///\r
1062 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.\r
1063 ///\r
1064 UINT32 C1States:4;\r
1065 ///\r
1066 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.\r
1067 ///\r
1068 UINT32 C2States:4;\r
1069 ///\r
1070 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.\r
1071 ///\r
1072 UINT32 C3States:4;\r
1073 ///\r
1074 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.\r
1075 ///\r
1076 UINT32 C4States:4;\r
1077 ///\r
1078 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.\r
1079 ///\r
1080 UINT32 C5States:4;\r
1081 ///\r
1082 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.\r
1083 ///\r
1084 UINT32 C6States:4;\r
1085 ///\r
1086 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.\r
1087 ///\r
1088 UINT32 C7States:4;\r
1089 } Bits;\r
1090 ///\r
1091 /// All bit fields as a 32-bit value\r
1092 ///\r
1093 UINT32 Uint32;\r
1094} CPUID_MONITOR_MWAIT_EDX;\r
1095\r
1096\r
1097/**\r
1098 CPUID Thermal and Power Management\r
1099\r
1100 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)\r
1101\r
1102 @retval EAX Thermal and power management features described by the type\r
1103 CPUID_THERMAL_POWER_MANAGEMENT_EAX.\r
1104 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor\r
1105 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.\r
1106 @retval ECX Performance features described by the type\r
1107 CPUID_THERMAL_POWER_MANAGEMENT_ECX.\r
1108 @retval EDX Reserved.\r
1109\r
1110 <b>Example usage</b>\r
1111 @code\r
1112 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r
1113 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r
1114 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r
1115\r
1116 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
1117 @endcode\r
1118**/\r
1119#define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r
1120\r
1121/**\r
1122 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf\r
1123 #CPUID_THERMAL_POWER_MANAGEMENT.\r
1124**/\r
1125typedef union {\r
1126 ///\r
1127 /// Individual bit fields\r
1128 ///\r
1129 struct {\r
1130 ///\r
1131 /// [Bit 0] Digital temperature sensor is supported if set.\r
1132 ///\r
1133 UINT32 DigitalTemperatureSensor:1;\r
1134 ///\r
1135 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).\r
1136 ///\r
1137 UINT32 TurboBoostTechnology:1;\r
1138 ///\r
1139 /// [Bit 2] APIC-Timer-always-running feature is supported if set.\r
1140 ///\r
1141 UINT32 ARAT:1;\r
1142 UINT32 Reserved1:1;\r
1143 ///\r
1144 /// [Bit 4] Power limit notification controls are supported if set.\r
1145 ///\r
1146 UINT32 PLN:1;\r
1147 ///\r
1148 /// [Bit 5] Clock modulation duty cycle extension is supported if set.\r
1149 ///\r
1150 UINT32 ECMD:1;\r
1151 ///\r
1152 /// [Bit 6] Package thermal management is supported if set.\r
1153 ///\r
1154 UINT32 PTM:1;\r
1155 ///\r
1156 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,\r
1157 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.\r
1158 ///\r
1159 UINT32 HWP:1;\r
1160 ///\r
1161 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.\r
1162 ///\r
1163 UINT32 HWP_Notification:1;\r
1164 ///\r
1165 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.\r
1166 ///\r
1167 UINT32 HWP_Activity_Window:1;\r
1168 ///\r
1169 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.\r
1170 ///\r
1171 UINT32 HWP_Energy_Performance_Preference:1;\r
1172 ///\r
1173 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.\r
1174 ///\r
1175 UINT32 HWP_Package_Level_Request:1;\r
1176 UINT32 Reserved2:1;\r
1177 ///\r
1178 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,\r
1179 /// IA32_THREAD_STALL MSRs are supported if set.\r
1180 ///\r
1181 UINT32 HDC:1;\r
1182 UINT32 Reserved3:18;\r
1183 } Bits;\r
1184 ///\r
1185 /// All bit fields as a 32-bit value\r
1186 ///\r
1187 UINT32 Uint32;\r
1188} CPUID_THERMAL_POWER_MANAGEMENT_EAX;\r
1189\r
1190/**\r
1191 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf\r
1192 #CPUID_THERMAL_POWER_MANAGEMENT.\r
1193**/\r
1194typedef union {\r
1195 ///\r
1196 /// Individual bit fields\r
1197 ///\r
1198 struct {\r
1199 ///\r
1200 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.\r
1201 ///\r
1202 UINT32 InterruptThresholds:4;\r
1203 UINT32 Reserved:28;\r
1204 } Bits;\r
1205 ///\r
1206 /// All bit fields as a 32-bit value\r
1207 ///\r
1208 UINT32 Uint32;\r
1209} CPUID_THERMAL_POWER_MANAGEMENT_EBX;\r
1210\r
1211/**\r
1212 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf\r
1213 #CPUID_THERMAL_POWER_MANAGEMENT.\r
1214**/\r
1215typedef union {\r
1216 ///\r
1217 /// Individual bit fields\r
1218 ///\r
1219 struct {\r
1220 ///\r
1221 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF\r
1222 /// and IA32_APERF). The capability to provide a measure of delivered\r
1223 /// processor performance (since last reset of the counters), as a percentage\r
1224 /// of the expected processor performance when running at the TSC frequency.\r
1225 ///\r
1226 UINT32 HardwareCoordinationFeedback:1;\r
1227 UINT32 Reserved1:2;\r
1228 ///\r
1229 /// [Bit 3] If this bit is set, then the processor supports performance-energy\r
1230 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS\r
1231 /// (1B0H).\r
1232 ///\r
1233 UINT32 PerformanceEnergyBias:1;\r
1234 UINT32 Reserved2:28;\r
1235 } Bits;\r
1236 ///\r
1237 /// All bit fields as a 32-bit value\r
1238 ///\r
1239 UINT32 Uint32;\r
1240} CPUID_THERMAL_POWER_MANAGEMENT_ECX;\r
1241\r
1242\r
1243/**\r
1244 CPUID Structured Extended Feature Flags Enumeration\r
1245\r
1246 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)\r
1247 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).\r
1248\r
1249 @note\r
1250 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r
1251 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.\r
1252\r
1253 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.\r
1254 @retval EBX Structured Extended Feature Flags described by the type\r
1255 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.\r
1256 @retval EBX Structured Extended Feature Flags described by the type\r
1257 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.\r
1258 @retval EDX Reserved.\r
1259\r
1260 <b>Example usage</b>\r
1261 @code\r
1262 UINT32 Eax;\r
1263 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
1264 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r
1265 UINT32 SubLeaf;\r
1266\r
1267 AsmCpuidEx (\r
1268 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
1269 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
1270 &Eax, NULL, NULL, NULL\r
1271 );\r
1272 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r
1273 AsmCpuidEx (\r
1274 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
1275 SubLeaf,\r
1276 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r
1277 );\r
d93a10c0 1278 }\r
57d16ba1
MK
1279 @endcode\r
1280**/\r
1281#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
1282\r
1283///\r
1284/// CPUID Structured Extended Feature Flags Enumeration sub-leaf\r
1285///\r
1286#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00\r
1287\r
1288/**\r
1289 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf\r
1290 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r
1291 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r
1292**/\r
1293typedef union {\r
1294 ///\r
1295 /// Individual bit fields\r
1296 ///\r
1297 struct {\r
1298 ///\r
1299 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.\r
1300 ///\r
1301 UINT32 FSGSBASE:1;\r
1302 ///\r
1303 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.\r
1304 ///\r
1305 UINT32 IA32_TSC_ADJUST:1;\r
c606a9a5
JF
1306 ///\r
1307 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT\r
1308 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".\r
1309 ///\r
1310 UINT32 SGX:1;\r
57d16ba1
MK
1311 ///\r
1312 /// [Bit 3] If 1 indicates the processor supports the first group of advanced\r
1313 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)\r
1314 ///\r
1315 UINT32 BMI1:1;\r
1316 ///\r
1317 /// [Bit 4] Hardware Lock Elision\r
1318 ///\r
1319 UINT32 HLE:1;\r
1320 ///\r
1321 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.\r
1322 ///\r
1323 UINT32 AVX2:1;\r
1324 ///\r
1325 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.\r
1326 ///\r
1327 UINT32 FDP_EXCPTN_ONLY:1;\r
1328 ///\r
1329 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.\r
1330 ///\r
1331 UINT32 SMEP:1;\r
1332 ///\r
1333 /// [Bit 8] If 1 indicates the processor supports the second group of\r
1334 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,\r
1335 /// SARX, SHLX, SHRX)\r
1336 ///\r
1337 UINT32 BMI2:1;\r
1338 ///\r
1339 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.\r
1340 ///\r
1341 UINT32 EnhancedRepMovsbStosb:1;\r
1342 ///\r
1343 /// [Bit 10] If 1, supports INVPCID instruction for system software that\r
1344 /// manages process-context identifiers.\r
1345 ///\r
1346 UINT32 INVPCID:1;\r
1347 ///\r
1348 /// [Bit 11] Restricted Transactional Memory\r
1349 ///\r
1350 UINT32 RTM:1;\r
1351 ///\r
1352 /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)\r
1353 /// capability if 1.\r
1354 ///\r
1355 UINT32 PQM:1;\r
1356 ///\r
1357 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
1358 ///\r
1359 UINT32 DeprecateFpuCsDs:1;\r
1360 ///\r
1361 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.\r
1362 ///\r
1363 UINT32 MPX:1;\r
1364 ///\r
1365 /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)\r
1366 /// capability if 1.\r
1367 ///\r
1368 UINT32 PQE:1;\r
1369 UINT32 Reserved2:2;\r
1370 ///\r
1371 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r
1372 ///\r
1373 UINT32 RDSEED:1;\r
1374 ///\r
1375 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX\r
1376 /// instructions.\r
1377 ///\r
1378 UINT32 ADX:1;\r
1379 ///\r
1380 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC\r
1381 /// instructions) if 1.\r
1382 ///\r
1383 UINT32 SMAP:1;\r
1384 UINT32 Reserved3:2;\r
1385 ///\r
1386 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
1387 ///\r
1388 UINT32 CLFLUSHOPT:1;\r
1389 UINT32 Reserved4:1;\r
1390 ///\r
1391 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
1392 /// extensions.\r
1393 ///\r
1394 UINT32 IntelProcessorTrace:1;\r
1395 UINT32 Reserved5:6;\r
1396 } Bits;\r
1397 ///\r
1398 /// All bit fields as a 32-bit value\r
1399 ///\r
1400 UINT32 Uint32;\r
1401} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;\r
1402\r
1403/**\r
1404 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf\r
1405 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r
1406 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r
1407**/\r
1408typedef union {\r
1409 ///\r
1410 /// Individual bit fields\r
1411 ///\r
1412 struct {\r
1413 ///\r
1414 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
1415 ///\r
1416 UINT32 PREFETCHWT1:1;\r
1417 UINT32 Reserved1:2;\r
1418 ///\r
1419 /// [Bit 3] Supports protection keys for user-mode pages if 1.\r
1420 ///\r
1421 UINT32 PKU:1;\r
1422 ///\r
1423 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the\r
1424 /// RDPKRU/WRPKRU instructions).\r
1425 ///\r
1426 UINT32 OSPKE:1;\r
1427 UINT32 Reserved2:27;\r
1428 } Bits;\r
1429 ///\r
1430 /// All bit fields as a 32-bit value\r
1431 ///\r
1432 UINT32 Uint32;\r
1433} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;\r
1434\r
1435\r
1436/**\r
1437 CPUID Direct Cache Access Information\r
1438\r
1439 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)\r
1440\r
1441 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).\r
1442 @retval EBX Reserved.\r
1443 @retval ECX Reserved.\r
1444 @retval EDX Reserved.\r
1445\r
1446 <b>Example usage</b>\r
1447 @code\r
1448 UINT32 Eax;\r
1449\r
1450 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r
1451 @endcode\r
1452**/\r
1453#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r
1454\r
1455\r
1456/**\r
1457 CPUID Architectural Performance Monitoring\r
1458\r
1459 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)\r
1460\r
1461 @retval EAX Architectural Performance Monitoring information described by\r
1462 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.\r
1463 @retval EBX Architectural Performance Monitoring information described by\r
1464 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.\r
1465 @retval ECX Reserved.\r
1466 @retval EDX Architectural Performance Monitoring information described by\r
1467 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.\r
1468\r
1469 <b>Example usage</b>\r
1470 @code\r
1471 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r
1472 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r
1473 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r
1474\r
1475 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r
1476 @endcode\r
1477**/\r
1478#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A\r
1479\r
1480/**\r
1481 CPUID Architectural Performance Monitoring EAX for CPUID leaf\r
1482 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
1483**/\r
1484typedef union {\r
1485 ///\r
1486 /// Individual bit fields\r
1487 ///\r
1488 struct {\r
1489 ///\r
1490 /// [Bit 7:0] Version ID of architectural performance monitoring.\r
1491 ///\r
1492 UINT32 ArchPerfMonVerID:8;\r
1493 ///\r
1494 /// [Bits 15:8] Number of general-purpose performance monitoring counter\r
1495 /// per logical processor.\r
1496 ///\r
1497 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous\r
1498 /// block of MSR address space. Each performance event select register is\r
1499 /// paired with a corresponding performance counter in the 0C1H address\r
1500 /// block.\r
1501 ///\r
1502 UINT32 PerformanceMonitorCounters:8;\r
1503 ///\r
1504 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.\r
1505 ///\r
1506 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for\r
1507 /// read operation. On write operations, the lower-order 32 bits of the MSR\r
1508 /// may be written with any value, and the high-order bits are sign-extended\r
1509 /// from the value of bit 31.\r
1510 ///\r
1511 UINT32 PerformanceMonitorCounterWidth:8;\r
1512 ///\r
1513 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural\r
1514 /// performance monitoring events.\r
1515 ///\r
1516 UINT32 EbxBitVectorLength:8;\r
1517 } Bits;\r
1518 ///\r
1519 /// All bit fields as a 32-bit value\r
1520 ///\r
1521 UINT32 Uint32;\r
1522} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;\r
1523\r
1524/**\r
1525 CPUID Architectural Performance Monitoring EBX for CPUID leaf\r
1526 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
1527**/\r
1528typedef union {\r
1529 ///\r
1530 /// Individual bit fields\r
1531 ///\r
1532 struct {\r
1533 ///\r
1534 /// [Bit 0] Core cycle event not available if 1.\r
1535 ///\r
1536 UINT32 UnhaltedCoreCycles:1;\r
1537 ///\r
1538 /// [Bit 1] Instruction retired event not available if 1.\r
1539 ///\r
1540 UINT32 InstructionsRetired:1;\r
1541 ///\r
1542 /// [Bit 2] Reference cycles event not available if 1.\r
1543 ///\r
1544 UINT32 UnhaltedReferenceCycles:1;\r
1545 ///\r
1546 /// [Bit 3] Last-level cache reference event not available if 1.\r
1547 ///\r
1548 UINT32 LastLevelCacheReferences:1;\r
1549 ///\r
1550 /// [Bit 4] Last-level cache misses event not available if 1.\r
1551 ///\r
1552 UINT32 LastLevelCacheMisses:1;\r
1553 ///\r
1554 /// [Bit 5] Branch instruction retired event not available if 1.\r
1555 ///\r
1556 UINT32 BranchInstructionsRetired:1;\r
1557 ///\r
1558 /// [Bit 6] Branch mispredict retired event not available if 1.\r
1559 ///\r
1560 UINT32 AllBranchMispredictRetired:1;\r
1561 UINT32 Reserved:25;\r
1562 } Bits;\r
1563 ///\r
1564 /// All bit fields as a 32-bit value\r
1565 ///\r
1566 UINT32 Uint32;\r
1567} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;\r
1568\r
1569/**\r
1570 CPUID Architectural Performance Monitoring EDX for CPUID leaf\r
1571 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
1572**/\r
1573typedef union {\r
1574 ///\r
1575 /// Individual bit fields\r
1576 ///\r
1577 struct {\r
1578 ///\r
1579 /// [Bits 4:0] Number of fixed-function performance counters\r
1580 /// (if Version ID > 1).\r
1581 ///\r
1582 UINT32 FixedFunctionPerformanceCounters:5;\r
1583 ///\r
1584 /// [Bits 12:5] Bit width of fixed-function performance counters\r
1585 /// (if Version ID > 1).\r
1586 ///\r
1587 UINT32 FixedFunctionPerformanceCounterWidth:8;\r
1588 UINT32 Reserved:19;\r
1589 } Bits;\r
1590 ///\r
1591 /// All bit fields as a 32-bit value\r
1592 ///\r
1593 UINT32 Uint32;\r
1594} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;\r
1595\r
1596\r
1597/**\r
1598 CPUID Extended Topology Information\r
1599\r
1600 @note\r
1601 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output\r
1602 of leaf 0BH is always valid and does not vary with input value in ECX. Output\r
1603 value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that\r
1604 return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If\r
1605 an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],\r
1606 other input values with ECX > n also return 0 in ECX[15:8].\r
1607\r
1608 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)\r
1609 @param ECX Level number\r
1610\r
1611 @retval EAX Extended topology information described by the type\r
1612 CPUID_EXTENDED_TOPOLOGY_EAX.\r
1613 @retval EBX Extended topology information described by the type\r
1614 CPUID_EXTENDED_TOPOLOGY_EBX.\r
1615 @retval ECX Extended topology information described by the type\r
1616 CPUID_EXTENDED_TOPOLOGY_ECX.\r
1617 @retval EDX x2APIC ID the current logical processor.\r
1618\r
1619 <b>Example usage</b>\r
1620 @code\r
1621 CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r
1622 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r
1623 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r
1624 UINT32 Edx;\r
1625 UINT32 LevelNumber;\r
1626\r
1627 LevelNumber = 0;\r
1628 do {\r
1629 AsmCpuidEx (\r
1630 CPUID_EXTENDED_TOPOLOGY, LevelNumber,\r
1631 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r
1632 );\r
1633 LevelNumber++;\r
1634 } while (Eax.Bits.ApicIdShift != 0);\r
1635 @endcode\r
1636**/\r
1637#define CPUID_EXTENDED_TOPOLOGY 0x0B\r
1638\r
1639/**\r
1640 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
1641**/\r
1642typedef union {\r
1643 ///\r
1644 /// Individual bit fields\r
1645 ///\r
1646 struct {\r
1647 ///\r
1648 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique\r
1649 /// topology ID of the next level type. All logical processors with the\r
1650 /// same next level ID share current level.\r
1651 ///\r
1652 /// @note\r
1653 /// Software should use this field (EAX[4:0]) to enumerate processor\r
1654 /// topology of the system.\r
1655 ///\r
1656 UINT32 ApicIdShift:5;\r
1657 UINT32 Reserved:27;\r
1658 } Bits;\r
1659 ///\r
1660 /// All bit fields as a 32-bit value\r
1661 ///\r
1662 UINT32 Uint32;\r
1663} CPUID_EXTENDED_TOPOLOGY_EAX;\r
1664\r
1665/**\r
1666 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
1667**/\r
1668typedef union {\r
1669 ///\r
1670 /// Individual bit fields\r
1671 ///\r
1672 struct {\r
1673 ///\r
1674 /// [Bits 15:0] Number of logical processors at this level type. The number\r
1675 /// reflects configuration as shipped by Intel.\r
1676 ///\r
1677 /// @note\r
1678 /// Software must not use EBX[15:0] to enumerate processor topology of the\r
1679 /// system. This value in this field (EBX[15:0]) is only intended for\r
1680 /// display/diagnostic purposes. The actual number of logical processors\r
1681 /// available to BIOS/OS/Applications may be different from the value of\r
1682 /// EBX[15:0], depending on software and platform hardware configurations.\r
1683 ///\r
1684 UINT32 LogicalProcessors:16;\r
1685 UINT32 Reserved:16;\r
1686 } Bits;\r
1687 ///\r
1688 /// All bit fields as a 32-bit value\r
1689 ///\r
1690 UINT32 Uint32;\r
1691} CPUID_EXTENDED_TOPOLOGY_EBX;\r
1692\r
1693/**\r
1694 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
1695**/\r
1696typedef union {\r
1697 ///\r
1698 /// Individual bit fields\r
1699 ///\r
1700 struct {\r
1701 ///\r
1702 /// [Bits 7:0] Level number. Same value in ECX input.\r
1703 ///\r
1704 UINT32 LevelNumber:8;\r
1705 ///\r
1706 /// [Bits 15:8] Level type.\r
1707 ///\r
1708 /// @note\r
1709 /// The value of the "level type" field is not related to level numbers in\r
1710 /// any way, higher "level type" values do not mean higher levels.\r
1711 ///\r
1712 UINT32 LevelType:8;\r
1713 UINT32 Reserved:16;\r
1714 } Bits;\r
1715 ///\r
1716 /// All bit fields as a 32-bit value\r
1717 ///\r
1718 UINT32 Uint32;\r
1719} CPUID_EXTENDED_TOPOLOGY_ECX;\r
1720\r
1721///\r
1722/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
1723///\r
1724#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r
1725#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r
1726#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r
1727///\r
1728/// @}\r
1729///\r
1730\r
1731\r
1732/**\r
1733 CPUID Extended State Information\r
1734\r
1735 @param EAX CPUID_EXTENDED_STATE (0x0D)\r
1736 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).\r
1737 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).\r
1738 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).\r
1739 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.\r
1740**/\r
1741#define CPUID_EXTENDED_STATE 0x0D\r
1742\r
1743/**\r
1744 CPUID Extended State Information Main Leaf\r
1745\r
1746 @param EAX CPUID_EXTENDED_STATE (0x0D)\r
1747 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)\r
1748\r
1749 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]\r
1750 can be set to 1 only if EAX[n] is 1. The format of the extended\r
1751 state main leaf is described by the type\r
1752 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.\r
1753 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
1754 area) required by enabled features in XCR0. May be different than\r
1755 ECX if some features at the end of the XSAVE save area are not\r
1756 enabled.\r
1757 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
1758 area) of the XSAVE/XRSTOR save area required by all supported\r
1759 features in the processor, i.e all the valid bit fields in XCR0.\r
1760 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.\r
1761 XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r
1762\r
1763 <b>Example usage</b>\r
1764 @code\r
1765 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r
1766 UINT32 Ebx;\r
1767 UINT32 Ecx;\r
1768 UINT32 Edx;\r
1769\r
1770 AsmCpuidEx (\r
1771 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r
1772 &Eax.Uint32, &Ebx, &Ecx, &Edx\r
1773 );\r
1774 @endcode\r
1775**/\r
1776#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r
1777\r
1778/**\r
1779 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
1780 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.\r
1781**/\r
1782typedef union {\r
1783 ///\r
1784 /// Individual bit fields\r
1785 ///\r
1786 struct {\r
1787 ///\r
1788 /// [Bit 0] x87 state.\r
1789 ///\r
1790 UINT32 x87:1;\r
1791 ///\r
1792 /// [Bit 1] SSE state.\r
1793 ///\r
1794 UINT32 SSE:1;\r
1795 ///\r
1796 /// [Bit 2] AVX state.\r
1797 ///\r
1798 UINT32 AVX:1;\r
1799 ///\r
1800 /// [Bits 4:3] MPX state.\r
1801 ///\r
1802 UINT32 MPX:2;\r
1803 ///\r
1804 /// [Bits 7:5] AVX-512 state.\r
1805 ///\r
1806 UINT32 AVX_512:3;\r
1807 ///\r
1808 /// [Bit 8] Used for IA32_XSS.\r
1809 ///\r
1810 UINT32 IA32_XSS:1;\r
1811 ///\r
1812 /// [Bit 9] PKRU state.\r
1813 ///\r
1814 UINT32 PKRU:1;\r
1815 UINT32 Reserved:22;\r
1816 } Bits;\r
1817 ///\r
1818 /// All bit fields as a 32-bit value\r
1819 ///\r
1820 UINT32 Uint32;\r
1821} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;\r
1822\r
1823/**\r
1824 CPUID Extended State Information Sub Leaf\r
1825\r
1826 @param EAX CPUID_EXTENDED_STATE (0x0D)\r
1827 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)\r
1828\r
1829 @retval EAX The format of the extended state sub-leaf is described by the\r
1830 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.\r
1831 @retval EBX The size in bytes of the XSAVE area containing all states\r
1832 enabled by XCRO | IA32_XSS.\r
1833 @retval ECX The format of the extended state sub-leaf is described by the\r
1834 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.\r
1835 @retval EDX Reports the supported bits of the upper 32 bits of the\r
1836 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.\r
1837\r
1838 <b>Example usage</b>\r
1839 @code\r
1840 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r
1841 UINT32 Ebx;\r
1842 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r
1843 UINT32 Edx;\r
1844\r
1845 AsmCpuidEx (\r
1846 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r
1847 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r
1848 );\r
1849 @endcode\r
1850**/\r
1851#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r
1852\r
1853/**\r
1854 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
1855 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r
1856**/\r
1857typedef union {\r
1858 ///\r
1859 /// Individual bit fields\r
1860 ///\r
1861 struct {\r
1862 ///\r
1863 /// [Bit 0] XSAVEOPT is available.\r
1864 ///\r
1865 UINT32 XSAVEOPT:1;\r
1866 ///\r
1867 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.\r
1868 ///\r
1869 UINT32 XSAVEC:1;\r
1870 ///\r
1871 /// [Bit 2] Supports XGETBV with ECX = 1 if set.\r
1872 ///\r
1873 UINT32 XGETBV:1;\r
1874 ///\r
1875 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.\r
1876 ///\r
1877 UINT32 XSAVES:1;\r
1878 UINT32 Reserved:28;\r
1879 } Bits;\r
1880 ///\r
1881 /// All bit fields as a 32-bit value\r
1882 ///\r
1883 UINT32 Uint32;\r
1884} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;\r
1885\r
1886/**\r
1887 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
1888 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r
1889**/\r
1890typedef union {\r
1891 ///\r
1892 /// Individual bit fields\r
1893 ///\r
1894 struct {\r
1895 ///\r
1896 /// [Bits 7:0] Used for XCR0.\r
1897 ///\r
1898 UINT32 XCR0:1;\r
1899 ///\r
1900 /// [Bit 8] PT STate.\r
1901 ///\r
1902 UINT32 PT:1;\r
1903 ///\r
1904 /// [Bit 9] Used for XCR0.\r
1905 ///\r
1906 UINT32 XCR0_1:1;\r
1907 UINT32 Reserved:22;\r
1908 } Bits;\r
1909 ///\r
1910 /// All bit fields as a 32-bit value\r
1911 ///\r
1912 UINT32 Uint32;\r
1913} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;\r
1914\r
1915/**\r
1916 CPUID Extended State Information Size and Offset Sub Leaf\r
1917\r
1918 @note\r
1919 Leaf 0DH output depends on the initial value in ECX.\r
1920 Each sub-leaf index (starting at position 2) is supported if it corresponds to\r
1921 a supported bit in either the XCR0 register or the IA32_XSS MSR.\r
1922 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r
1923 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1\r
1924 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0\r
1925 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].\r
1926\r
1927 @param EAX CPUID_EXTENDED_STATE (0x0D)\r
1928 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based\r
1929 on supported bits in XCR0 or IA32_XSS_MSR.\r
1930\r
1931 @retval EAX The size in bytes (from the offset specified in EBX) of the save\r
1932 area for an extended state feature associated with a valid\r
1933 sub-leaf index, n.\r
1934 @retval EBX The offset in bytes of this extended state component's save area\r
1935 from the beginning of the XSAVE/XRSTOR area. This field reports\r
1936 0 if the sub-leaf index, n, does not map to a valid bit in the\r
1937 XCR0 register.\r
1938 @retval ECX The format of the extended state components's save area as\r
1939 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.\r
1940 This field reports 0 if the sub-leaf index, n, is invalid.\r
1941 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;\r
1942 otherwise it is reserved.\r
1943\r
1944 <b>Example usage</b>\r
1945 @code\r
1946 UINT32 Eax;\r
1947 UINT32 Ebx;\r
1948 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r
1949 UINT32 Edx;\r
1950 UINTN SubLeaf;\r
1951\r
1952 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
1953 AsmCpuidEx (\r
1954 CPUID_EXTENDED_STATE, SubLeaf,\r
1955 &Eax, &Ebx, &Ecx.Uint32, &Edx\r
1956 );\r
1957 }\r
1958 @endcode\r
1959**/\r
1960#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r
1961\r
1962/**\r
1963 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
1964 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.\r
1965**/\r
1966typedef union {\r
1967 ///\r
1968 /// Individual bit fields\r
1969 ///\r
1970 struct {\r
1971 ///\r
1972 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is\r
1973 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported\r
1974 /// in XCR0.\r
1975 ///\r
1976 UINT32 XSS:1;\r
1977 ///\r
1978 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,\r
1979 /// this extended state component located on the next 64-byte boundary\r
1980 /// following the preceding state component (otherwise, it is located\r
1981 /// immediately following the preceding state component).\r
1982 ///\r
1983 UINT32 Compacted:1;\r
1984 UINT32 Reserved:30;\r
1985 } Bits;\r
1986 ///\r
1987 /// All bit fields as a 32-bit value\r
1988 ///\r
1989 UINT32 Uint32;\r
1990} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;\r
1991\r
1992\r
1993/**\r
1994 CPUID Platform QoS Monitoring Information\r
1995\r
1996 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
1997 @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
1998 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).\r
1999\r
2000**/\r
2001#define CPUID_PLATFORM_QOS_MONITORING 0x0F\r
2002\r
2003/**\r
2004 CPUID Platform QoS Monitoring Information Enumeration Sub-leaf\r
2005\r
2006 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
2007 @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
2008\r
2009 @retval EAX Reserved.\r
2010 @retval EBX Maximum range (zero-based) of RMID within this physical\r
2011 processor of all types.\r
2012 @retval ECX Reserved.\r
2013 @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the\r
2014 type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
2015\r
2016 <b>Example usage</b>\r
2017 @code\r
2018 UINT32 Ebx;\r
2019 CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
2020\r
2021 AsmCpuidEx (\r
2022 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r
2023 NULL, &Ebx, NULL, &Edx.Uint32\r
2024 );\r
2025 @endcode\r
2026**/\r
2027#define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
2028\r
2029/**\r
2030 CPUID Platform QoS Monitoring Information EDX for CPUID leaf\r
2031 #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
2032 #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.\r
2033**/\r
2034typedef union {\r
2035 ///\r
2036 /// Individual bit fields\r
2037 ///\r
2038 struct {\r
2039 UINT32 Reserved1:1;\r
2040 ///\r
2041 /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.\r
2042 ///\r
2043 UINT32 L3CacheQosEnforcement:1;\r
2044 UINT32 Reserved2:30;\r
2045 } Bits;\r
2046 ///\r
2047 /// All bit fields as a 32-bit value\r
2048 ///\r
2049 UINT32 Uint32;\r
2050} CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
2051\r
2052/**\r
2053 CPUID Platform QoS Monitoring Information Capability Sub-leaf\r
2054\r
2055 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
2056 @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)\r
2057\r
2058 @retval EAX Reserved.\r
2059 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r
2060 @retval ECX Maximum range (zero-based) of RMID of this resource type.\r
2061 @retval EDX L3 Cache QoS Monitoring Capability information described by the\r
2062 type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.\r
2063\r
2064 <b>Example usage</b>\r
2065 @code\r
2066 UINT32 Ebx;\r
2067 UINT32 Ecx;\r
2068 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;\r
2069\r
2070 AsmCpuidEx (\r
2071 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r
2072 NULL, &Ebx, &Ecx, &Edx.Uint32\r
2073 );\r
2074 @endcode\r
2075**/\r
2076#define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01\r
2077\r
2078/**\r
2079 CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf\r
2080 #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
2081 #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.\r
2082**/\r
2083typedef union {\r
2084 ///\r
2085 /// Individual bit fields\r
2086 ///\r
2087 struct {\r
2088 ///\r
2089 /// [Bit 0] Supports L3 occupancy monitoring if 1.\r
2090 ///\r
2091 UINT32 L3CacheOccupancyMonitoring:1;\r
2092 UINT32 Reserved:31;\r
2093 } Bits;\r
2094 ///\r
2095 /// All bit fields as a 32-bit value\r
2096 ///\r
2097 UINT32 Uint32;\r
2098} CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;\r
2099\r
2100\r
2101/**\r
2102 CPUID Platform QoS Enforcement Information\r
2103\r
2104 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).\r
2105 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
2106 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).\r
2107 Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
2108**/\r
2109#define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10\r
2110\r
2111/**\r
2112 CPUID Platform QoS Enforcement Information\r
2113\r
2114 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
2115 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
2116\r
2117 @retval EAX Reserved.\r
2118 @retval EBX L3 Cache QoS Enforcement information described by the\r
2119 type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.\r
2120 @retval ECX Reserved.\r
2121 @retval EDX Reserved.\r
2122\r
2123 <b>Example usage</b>\r
2124 @code\r
2125 CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;\r
2126\r
2127 AsmCpuidEx (\r
2128 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r
2129 NULL, &Ebx.Uint32, NULL, NULL\r
2130 );\r
2131 @endcode\r
2132**/\r
2133#define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00\r
2134\r
2135/**\r
2136 CPUID Platform QoS Enforcement Information EBX for CPUID leaf\r
2137 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
2138 #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.\r
2139**/\r
2140typedef union {\r
2141 ///\r
2142 /// Individual bit fields\r
2143 ///\r
2144 struct {\r
2145 UINT32 Reserved1:1;\r
2146 ///\r
2147 /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.\r
2148 ///\r
2149 UINT32 L3CacheQosEnforcement:1;\r
2150 UINT32 Reserved2:30;\r
2151 } Bits;\r
2152 ///\r
2153 /// All bit fields as a 32-bit value\r
2154 ///\r
2155 UINT32 Uint32;\r
2156} CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;\r
2157\r
2158\r
2159/**\r
2160 CPUID Platform QoS Enforcement Information\r
2161\r
2162 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
2163 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)\r
2164 Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
2165\r
2166 @retval EAX RESID L3 Cache3 QoS Enforcement information described by the\r
2167 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.\r
2168 @retval EBX Bit-granular map of isolation/contention of allocation units.\r
2169 @retval ECX RESID L3 Cache3 QoS Enforcement information described by the\r
2170 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.\r
2171 @retval EDX RESID L3 Cache3 QoS Enforcement information described by the\r
2172 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.\r
2173\r
2174 <b>Example usage</b>\r
2175 @code\r
2176 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r
2177 UINT32 Ebx;\r
2178 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r
2179 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r
2180\r
2181 AsmCpuidEx (\r
2182 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r
2183 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
2184 );\r
2185 @endcode\r
2186**/\r
2187#define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01\r
2188\r
2189/**\r
2190 CPUID Platform QoS Enforcement Information EAX for CPUID leaf\r
2191 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
2192 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
2193**/\r
2194typedef union {\r
2195 ///\r
2196 /// Individual bit fields\r
2197 ///\r
2198 struct {\r
2199 ///\r
2200 /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.\r
2201 ///\r
2202 UINT32 CapacityLength:4;\r
2203 UINT32 Reserved:28;\r
2204 } Bits;\r
2205 ///\r
2206 /// All bit fields as a 32-bit value\r
2207 ///\r
2208 UINT32 Uint32;\r
2209} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;\r
2210\r
2211/**\r
2212 CPUID Platform QoS Enforcement Information ECX for CPUID leaf\r
2213 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
2214 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
2215**/\r
2216typedef union {\r
2217 ///\r
2218 /// Individual bit fields\r
2219 ///\r
2220 struct {\r
2221 UINT32 Reserved1:1;\r
2222 ///\r
2223 /// [Bit 1] Updates of COS should be infrequent if 1.\r
2224 ///\r
2225 UINT32 CosUpdatesInfrequent:1;\r
2226 ///\r
2227 /// [Bit 2] Code and Data Prioritization Technology supported if 1.\r
2228 ///\r
2229 UINT32 CodeDataPrioritization:1;\r
2230 UINT32 Reserved2:29;\r
2231 } Bits;\r
2232 ///\r
2233 /// All bit fields as a 32-bit value\r
2234 ///\r
2235 UINT32 Uint32;\r
2236} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;\r
2237\r
2238/**\r
2239 CPUID Platform QoS Enforcement Information EDX for CPUID leaf\r
2240 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
2241 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
2242**/\r
2243typedef union {\r
2244 ///\r
2245 /// Individual bit fields\r
2246 ///\r
2247 struct {\r
2248 ///\r
2249 /// [Bits 15:0] Highest COS number supported for this ResID.\r
2250 ///\r
2251 UINT32 HighestCosNumber:16;\r
2252 UINT32 Reserved:16;\r
2253 } Bits;\r
2254 ///\r
2255 /// All bit fields as a 32-bit value\r
2256 ///\r
2257 UINT32 Uint32;\r
2258} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;\r
2259\r
2260\r
c606a9a5
JF
2261/**\r
2262 Intel SGX resource capability and configuration.\r
2263 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".\r
2264\r
2265 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying\r
2266 CPUID with EAX=12H on Intel SGX resource capability and configuration.\r
2267\r
2268 @param EAX CPUID_INTEL_SGX (0x12)\r
2269 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).\r
2270 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).\r
2271 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).\r
2272 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])\r
2273 until the sub-leaf type is invalid.\r
2274\r
2275**/\r
2276#define CPUID_INTEL_SGX 0x12\r
2277\r
2278/**\r
2279 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
2280 Enumerates Intel SGX capability, including enclave instruction opcode support.\r
2281\r
2282 @param EAX CPUID_INTEL_SGX (0x12)\r
2283 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)\r
2284\r
2285 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
2286 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.\r
2287 @retval EBX MISCSELECT: Reports the bit vector of supported extended features\r
2288 that can be written to the MISC region of the SSA.\r
2289 @retval ECX Reserved.\r
2290 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r
2291 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.\r
2292\r
2293 <b>Example usage</b>\r
2294 @code\r
2295 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
2296 UINT32 Ebx;\r
2297 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
2298\r
2299 AsmCpuidEx (\r
2300 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
2301 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
2302 );\r
2303 @endcode\r
2304**/\r
2305#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
2306\r
2307/**\r
2308 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r
2309 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
2310**/\r
2311typedef union {\r
2312 ///\r
2313 /// Individual bit fields\r
2314 ///\r
2315 struct {\r
2316 ///\r
2317 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r
2318 ///\r
2319 UINT32 SGX1:1;\r
2320 ///\r
2321 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r
2322 ///\r
2323 UINT32 SGX2:1;\r
2324 UINT32 Reserved:30;\r
2325 } Bits;\r
2326 ///\r
2327 /// All bit fields as a 32-bit value\r
2328 ///\r
2329 UINT32 Uint32;\r
2330} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r
2331\r
2332/**\r
2333 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,\r
2334 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r
2335**/\r
2336typedef union {\r
2337 ///\r
2338 /// Individual bit fields\r
2339 ///\r
2340 struct {\r
2341 ///\r
2342 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r
2343 /// when not in 64-bit mode.\r
2344 ///\r
2345 UINT32 MaxEnclaveSize_Not64:8;\r
2346 ///\r
2347 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r
2348 /// when operating in 64-bit mode.\r
2349 ///\r
2350 UINT32 MaxEnclaveSize_64:8;\r
2351 UINT32 Reserved:16;\r
2352 } Bits;\r
2353 ///\r
2354 /// All bit fields as a 32-bit value\r
2355 ///\r
2356 UINT32 Uint32;\r
2357} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r
2358\r
2359\r
2360/**\r
2361 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
2362 Enumerates Intel SGX capability of processor state configuration and enclave\r
2363 configuration in the SECS structure.\r
2364\r
2365 @param EAX CPUID_INTEL_SGX (0x12)\r
2366 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)\r
2367\r
2368 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can\r
2369 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE\r
2370 only if EAX[n] is 1, where n < 32.\r
2371 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can\r
2372 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE\r
2373 only if EBX[n] is 1, where n < 32.\r
2374 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can\r
2375 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE\r
2376 only if ECX[n] is 1, where n < 32.\r
2377 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can\r
2378 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE\r
2379 only if EDX[n] is 1, where n < 32.\r
2380\r
2381 <b>Example usage</b>\r
2382 @code\r
2383 UINT32 Eax;\r
2384 UINT32 Ebx;\r
2385 UINT32 Ecx;\r
2386 UINT32 Edx;\r
2387\r
2388 AsmCpuidEx (\r
2389 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
2390 &Eax, &Ebx, &Ecx, &Edx\r
2391 );\r
2392 @endcode\r
2393**/\r
2394#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
2395\r
2396\r
2397/**\r
2398 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
2399 Enumerates available EPC resources.\r
2400\r
2401 @param EAX CPUID_INTEL_SGX (0x12)\r
2402 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)\r
2403\r
2404 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
2405 Resources is described by the type\r
2406 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.\r
2407 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
2408 Resources is described by the type\r
2409 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.\r
2410 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
2411 Resources is described by the type\r
2412 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.\r
2413 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r
2414 Resources is described by the type\r
2415 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.\r
2416\r
2417 <b>Example usage</b>\r
2418 @code\r
2419 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
2420 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
2421 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
2422 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
2423\r
2424 AsmCpuidEx (\r
2425 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,\r
2426 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
2427 );\r
2428 @endcode\r
2429**/\r
2430#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02\r
2431\r
2432/**\r
2433 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID\r
2434 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
2435**/\r
2436typedef union {\r
2437 ///\r
2438 /// Individual bit fields\r
2439 ///\r
2440 struct {\r
2441 ///\r
2442 /// [Bit 3:0] Sub-leaf-type encoding.\r
2443 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.\r
2444 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)\r
2445 /// in EBX:EAX and EDX:ECX.\r
2446 /// All other encoding are reserved.\r
2447 ///\r
2448 UINT32 SubLeafType:4;\r
2449 UINT32 Reserved:8;\r
2450 ///\r
2451 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r
2452 /// the base of the EPC section.\r
2453 ///\r
2454 UINT32 LowAddressOfEpcSection:20;\r
2455 } Bits;\r
2456 ///\r
2457 /// All bit fields as a 32-bit value\r
2458 ///\r
2459 UINT32 Uint32;\r
2460} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r
2461\r
2462/**\r
2463 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID\r
2464 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
2465**/\r
2466typedef union {\r
2467 ///\r
2468 /// Individual bit fields\r
2469 ///\r
2470 struct {\r
2471 ///\r
2472 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r
2473 /// the base of the EPC section.\r
2474 ///\r
2475 UINT32 HighAddressOfEpcSection:20;\r
2476 UINT32 Reserved:12;\r
2477 } Bits;\r
2478 ///\r
2479 /// All bit fields as a 32-bit value\r
2480 ///\r
2481 UINT32 Uint32;\r
2482} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r
2483\r
2484/**\r
2485 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID\r
2486 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
2487**/\r
2488typedef union {\r
2489 ///\r
2490 /// Individual bit fields\r
2491 ///\r
2492 struct {\r
2493 ///\r
2494 /// [Bit 3:0] The EPC section encoding.\r
2495 /// 0000b: Not valid.\r
2496 /// 0001b: The EPC section is confidentiality, integrity and replay protected.\r
2497 /// All other encoding are reserved.\r
2498 ///\r
2499 UINT32 EpcSection:4;\r
2500 UINT32 Reserved:8;\r
2501 ///\r
2502 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r
2503 /// corresponding EPC section within the Processor Reserved Memory.\r
2504 ///\r
2505 UINT32 LowSizeOfEpcSection:20;\r
2506 } Bits;\r
2507 ///\r
2508 /// All bit fields as a 32-bit value\r
2509 ///\r
2510 UINT32 Uint32;\r
2511} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r
2512\r
2513/**\r
2514 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID\r
2515 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r
2516**/\r
2517typedef union {\r
2518 ///\r
2519 /// Individual bit fields\r
2520 ///\r
2521 struct {\r
2522 ///\r
2523 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r
2524 /// corresponding EPC section within the Processor Reserved Memory.\r
2525 ///\r
2526 UINT32 HighSizeOfEpcSection:20;\r
2527 UINT32 Reserved:12;\r
2528 } Bits;\r
2529 ///\r
2530 /// All bit fields as a 32-bit value\r
2531 ///\r
2532 UINT32 Uint32;\r
2533} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r
2534\r
2535\r
57d16ba1
MK
2536/**\r
2537 CPUID Intel Processor Trace Information\r
2538\r
2539 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)\r
2540 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).\r
2541 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).\r
2542\r
2543**/\r
2544#define CPUID_INTEL_PROCESSOR_TRACE 0x14\r
2545\r
2546/**\r
2547 CPUID Intel Processor Trace Information Main Leaf\r
2548\r
2549 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r
2550 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)\r
2551\r
2552 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.\r
2553 @retval EBX Returns Intel processor trace information described by the\r
2554 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.\r
2555 @retval ECX Returns Intel processor trace information described by the\r
2556 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.\r
2557 @retval EDX Reserved.\r
2558\r
2559 <b>Example usage</b>\r
2560 @code\r
2561 UINT32 Eax;\r
2562 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r
2563 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r
2564\r
2565 AsmCpuidEx (\r
2566 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
2567 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r
2568 );\r
2569 @endcode\r
2570**/\r
2571#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r
2572\r
2573/**\r
2574 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
2575 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r
2576**/\r
2577typedef union {\r
2578 ///\r
2579 /// Individual bit fields\r
2580 ///\r
2581 struct {\r
2582 ///\r
2583 /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
2584 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
2585 ///\r
2586 UINT32 Cr3Filter:1;\r
2587 ///\r
2588 /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate\r
2589 /// Mode.\r
2590 ///\r
2591 UINT32 ConfigurablePsb:1;\r
2592 ///\r
2593 /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,\r
2594 /// and preservation of Intel PT MSRs across warm reset.\r
2595 ///\r
2596 UINT32 IpTraceStopFiltering:1;\r
2597 ///\r
2598 /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of\r
2599 /// COFI-based packets.\r
2600 ///\r
2601 UINT32 Mtc:1;\r
2602 UINT32 Reserved:28;\r
2603 } Bits;\r
2604 ///\r
2605 /// All bit fields as a 32-bit value\r
2606 ///\r
2607 UINT32 Uint32;\r
2608} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;\r
2609\r
2610/**\r
2611 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
2612 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r
2613**/\r
2614typedef union {\r
2615 ///\r
2616 /// Individual bit fields\r
2617 ///\r
2618 struct {\r
2619 ///\r
2620 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence\r
2621 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and\r
2622 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r
2623 ///\r
2624 UINT32 RTIT:1;\r
2625 ///\r
2626 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to\r
2627 /// the maximum allowed by the MaskOrTableOffset field of\r
2628 /// IA32_RTIT_OUTPUT_MASK_PTRS.\r
2629 ///\r
2630 UINT32 ToPA:1;\r
2631 ///\r
2632 /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.\r
2633 ///\r
2634 UINT32 SingleRangeOutput:1;\r
2635 ///\r
2636 /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.\r
2637 ///\r
2638 UINT32 TraceTransportSubsystem:1;\r
2639 UINT32 Reserved:27;\r
2640 ///\r
2641 /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP\r
2642 /// values, which include the CS base component.\r
2643 ///\r
2644 UINT32 LIP:1;\r
2645 } Bits;\r
2646 ///\r
2647 /// All bit fields as a 32-bit value\r
2648 ///\r
2649 UINT32 Uint32;\r
2650} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;\r
2651\r
2652\r
2653/**\r
2654 CPUID Intel Processor Trace Information Sub-leaf\r
2655\r
2656 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r
2657 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)\r
2658\r
2659 @retval EAX Returns Intel processor trace information described by the\r
2660 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.\r
2661 @retval EBX Returns Intel processor trace information described by the\r
2662 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.\r
2663 @retval ECX Reserved.\r
2664 @retval EDX Reserved.\r
2665\r
2666 <b>Example usage</b>\r
2667 @code\r
2668 UINT32 MaximumSubLeaf;\r
2669 UINT32 SubLeaf;\r
2670 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r
2671 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r
2672\r
2673 AsmCpuidEx (\r
2674 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
2675 &MaximumSubLeaf, NULL, NULL, NULL\r
2676 );\r
2677\r
2678 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
2679 AsmCpuidEx (\r
2680 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r
2681 &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r
2682 );\r
2683 }\r
2684 @endcode\r
2685**/\r
2686#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r
2687\r
2688/**\r
2689 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
2690 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r
2691**/\r
2692typedef union {\r
2693 ///\r
2694 /// Individual bit fields\r
2695 ///\r
2696 struct {\r
2697 ///\r
2698 /// [Bits 2:0] Number of configurable Address Ranges for filtering.\r
2699 ///\r
2700 UINT32 ConfigurableAddressRanges:3;\r
2701 UINT32 Reserved:13;\r
2702 ///\r
2703 /// [Bits 31:16] Bitmap of supported MTC period encodings\r
2704 ///\r
2705 UINT32 MtcPeriodEncodings:16;\r
2706\r
2707 } Bits;\r
2708 ///\r
2709 /// All bit fields as a 32-bit value\r
2710 ///\r
2711 UINT32 Uint32;\r
2712} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;\r
2713\r
2714/**\r
2715 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
2716 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r
2717**/\r
2718typedef union {\r
2719 ///\r
2720 /// Individual bit fields\r
2721 ///\r
2722 struct {\r
2723 ///\r
2724 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.\r
2725 ///\r
2726 UINT32 CycleThresholdEncodings:16;\r
2727 ///\r
2728 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.\r
2729 ///\r
2730 UINT32 PsbFrequencyEncodings:16;\r
2731\r
2732 } Bits;\r
2733 ///\r
2734 /// All bit fields as a 32-bit value\r
2735 ///\r
2736 UINT32 Uint32;\r
2737} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;\r
2738\r
2739\r
2740/**\r
2741 CPUID Time Stamp Counter Information\r
2742\r
2743 @note\r
2744 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r
2745 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r
2746 crystal clock frequency.\r
2747 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
2748 The core crystal clock may differ from the reference clock, bus clock, or core\r
2749 clock frequencies.\r
2750\r
2751 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)\r
2752\r
2753 @retval EAX An unsigned integer which is the denominator of the\r
2754 TSC/"core crystal clock" ratio\r
2755 @retval EBX An unsigned integer which is the numerator of the\r
2756 TSC/"core crystal clock" ratio.\r
2757 @retval ECX Reserved.\r
2758 @retval EDX Reserved.\r
2759\r
2760 <b>Example usage</b>\r
2761 @code\r
2762 UINT32 Eax;\r
2763 UINT32 Ebx;\r
2764\r
2765 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r
2766 @endcode\r
2767**/\r
2768#define CPUID_TIME_STAMP_COUNTER 0x15\r
2769\r
2770\r
2771/**\r
2772 CPUID Processor Frequency Information\r
2773\r
2774 @note\r
2775 Data is returned from this interface in accordance with the processor's\r
2776 specification and does not reflect actual values. Suitable use of this data\r
2777 includes the display of processor information in like manner to the processor\r
2778 brand string and for determining the appropriate range to use when displaying\r
2779 processor information e.g. frequency history graphs. The returned information\r
2780 should not be used for any other purpose as the returned information does not\r
2781 accurately correlate to information / counters returned by other processor\r
2782 interfaces. While a processor may support the Processor Frequency Information\r
2783 leaf, fields that return a value of zero are not supported.\r
2784\r
2785 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)\r
2786\r
2787 @retval EAX Returns processor base frequency information described by the\r
2788 type CPUID_PROCESSOR_FREQUENCY_EAX.\r
2789 @retval EBX Returns maximum frequency information described by the type\r
2790 CPUID_PROCESSOR_FREQUENCY_EBX.\r
2791 @retval ECX Returns bus frequency information described by the type\r
2792 CPUID_PROCESSOR_FREQUENCY_ECX.\r
2793 @retval EDX Reserved.\r
2794\r
2795 <b>Example usage</b>\r
2796 @code\r
2797 CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r
2798 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r
2799 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r
2800\r
2801 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
2802 @endcode\r
2803**/\r
2804#define CPUID_PROCESSOR_FREQUENCY 0x16\r
2805\r
2806/**\r
2807 CPUID Processor Frequency Information EAX for CPUID leaf\r
2808 #CPUID_PROCESSOR_FREQUENCY.\r
2809**/\r
2810typedef union {\r
2811 ///\r
2812 /// Individual bit fields\r
2813 ///\r
2814 struct {\r
2815 ///\r
2816 /// [Bits 15:0] Processor Base Frequency (in MHz).\r
2817 ///\r
2818 UINT32 ProcessorBaseFrequency:16;\r
2819 UINT32 Reserved:16;\r
2820 } Bits;\r
2821 ///\r
2822 /// All bit fields as a 32-bit value\r
2823 ///\r
2824 UINT32 Uint32;\r
2825} CPUID_PROCESSOR_FREQUENCY_EAX;\r
2826\r
2827/**\r
2828 CPUID Processor Frequency Information EBX for CPUID leaf\r
2829 #CPUID_PROCESSOR_FREQUENCY.\r
2830**/\r
2831typedef union {\r
2832 ///\r
2833 /// Individual bit fields\r
2834 ///\r
2835 struct {\r
2836 ///\r
2837 /// [Bits 15:0] Maximum Frequency (in MHz).\r
2838 ///\r
2839 UINT32 MaximumFrequency:16;\r
2840 UINT32 Reserved:16;\r
2841 } Bits;\r
2842 ///\r
2843 /// All bit fields as a 32-bit value\r
2844 ///\r
2845 UINT32 Uint32;\r
2846} CPUID_PROCESSOR_FREQUENCY_EBX;\r
2847\r
2848/**\r
2849 CPUID Processor Frequency Information ECX for CPUID leaf\r
2850 #CPUID_PROCESSOR_FREQUENCY.\r
2851**/\r
2852typedef union {\r
2853 ///\r
2854 /// Individual bit fields\r
2855 ///\r
2856 struct {\r
2857 ///\r
2858 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).\r
2859 ///\r
2860 UINT32 BusFrequency:16;\r
2861 UINT32 Reserved:16;\r
2862 } Bits;\r
2863 ///\r
2864 /// All bit fields as a 32-bit value\r
2865 ///\r
2866 UINT32 Uint32;\r
2867} CPUID_PROCESSOR_FREQUENCY_ECX;\r
2868\r
28a7ddf0 2869\r
57d16ba1
MK
2870/**\r
2871 CPUID SoC Vendor Information\r
28a7ddf0 2872\r
57d16ba1
MK
2873 @param EAX CPUID_SOC_VENDOR (0x17)\r
2874 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r
2875 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r
2876 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)\r
2877 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)\r
28a7ddf0 2878\r
57d16ba1
MK
2879 @note\r
2880 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String\r
2881 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC\r
2882 Vendor Brand String is constructed by concatenating in ascending order of\r
2883 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r
28a7ddf0 2884\r
57d16ba1
MK
2885**/\r
2886#define CPUID_SOC_VENDOR 0x17\r
2887\r
2888/**\r
2889 CPUID SoC Vendor Information\r
2890\r
2891 @param EAX CPUID_SOC_VENDOR (0x17)\r
2892 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r
2893\r
2894 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported\r
2895 sub-leaf in leaf 17H.\r
2896 @retval EBX Returns SoC Vendor information described by the type\r
2897 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.\r
2898 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC\r
2899 projects.\r
2900 @retval EDX Stepping ID. A unique number within an SOC project that an SOC\r
2901 vendor assigns.\r
2902\r
2903 <b>Example usage</b>\r
2904 @code\r
2905 UINT32 Eax;\r
2906 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r
2907 UINT32 Ecx;\r
2908 UINT32 Edx;\r
2909\r
2910 AsmCpuidEx (\r
2911 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r
2912 &Eax, &Ebx.Uint32, &Ecx, &Edx\r
2913 );\r
2914 @endcode\r
2915**/\r
2916#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r
2917\r
2918/**\r
2919 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf\r
2920 #CPUID_SOC_VENDOR_MAIN_LEAF.\r
2921**/\r
2922typedef union {\r
2923 ///\r
2924 /// Individual bit fields\r
2925 ///\r
2926 struct {\r
2927 ///\r
2928 /// [Bits 15:0] SOC Vendor ID.\r
2929 ///\r
2930 UINT32 SocVendorId:16;\r
2931 ///\r
2932 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry\r
2933 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is\r
2934 /// assigned by Intel.\r
2935 ///\r
2936 UINT32 IsVendorScheme:1;\r
2937 UINT32 Reserved:15;\r
2938 } Bits;\r
2939 ///\r
2940 /// All bit fields as a 32-bit value\r
2941 ///\r
2942 UINT32 Uint32;\r
2943} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;\r
2944\r
2945/**\r
2946 CPUID SoC Vendor Information\r
2947\r
2948 @param EAX CPUID_SOC_VENDOR (0x17)\r
2949 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r
2950\r
2951 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
2952 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
2953 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
2954 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
2955 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
2956 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
2957 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
2958 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
2959\r
2960 <b>Example usage</b>\r
2961 @code\r
2962 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
2963 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
2964 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
2965 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
2966\r
2967 AsmCpuidEx (\r
2968 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r
2969 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
2970 );\r
2971 @endcode\r
2972**/\r
2973#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r
2974\r
2975/**\r
2976 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,\r
2977 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.\r
2978**/\r
2979typedef union {\r
2980 ///\r
2981 /// 4 UTF-8 characters of Soc Vendor Brand String\r
2982 ///\r
2983 CHAR8 BrandString[4];\r
2984 ///\r
2985 /// All fields as a 32-bit value\r
2986 ///\r
2987 UINT32 Uint32;\r
2988} CPUID_SOC_VENDOR_BRAND_STRING_DATA;\r
2989\r
2990/**\r
2991 CPUID SoC Vendor Information\r
2992\r
2993 @param EAX CPUID_SOC_VENDOR (0x17)\r
2994 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)\r
2995\r
2996 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
2997 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
2998 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
2999 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3000 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
3001 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3002 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
3003 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3004\r
3005 <b>Example usage</b>\r
3006 @code\r
3007 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
3008 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
3009 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
3010 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
3011\r
3012 AsmCpuidEx (\r
3013 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r
3014 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
3015 );\r
3016 @endcode\r
3017**/\r
3018#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r
3019\r
3020/**\r
3021 CPUID SoC Vendor Information\r
3022\r
3023 @param EAX CPUID_SOC_VENDOR (0x17)\r
3024 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)\r
28a7ddf0 3025\r
57d16ba1
MK
3026 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
3027 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3028 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
3029 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3030 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
3031 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3032 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
3033 CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
3034\r
3035 <b>Example usage</b>\r
3036 @code\r
3037 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
3038 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
3039 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
3040 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
3041\r
3042 AsmCpuidEx (\r
3043 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r
3044 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
3045 );\r
3046 @endcode\r
3047**/\r
3048#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
4de216c0 3049\r
28a7ddf0 3050\r
57d16ba1
MK
3051/**\r
3052 CPUID Extended Function\r
3053\r
3054 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)\r
3055\r
3056 @retval EAX Maximum Input Value for Extended Function CPUID Information.\r
3057 @retval EBX Reserved.\r
3058 @retval ECX Reserved.\r
3059 @retval EDX Reserved.\r
3060\r
3061 <b>Example usage</b>\r
3062 @code\r
3063 UINT32 Eax;\r
3064\r
3065 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
3066 @endcode\r
3067**/\r
28a7ddf0
MK
3068#define CPUID_EXTENDED_FUNCTION 0x80000000\r
3069\r
57d16ba1
MK
3070\r
3071/**\r
3072 CPUID Extended Processor Signature and Feature Bits\r
3073\r
3074 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r
3075\r
3076 @retval EAX CPUID_EXTENDED_CPU_SIG.\r
3077 @retval EBX Reserved.\r
3078 @retval ECX Extended Processor Signature and Feature Bits information\r
3079 described by the type CPUID_EXTENDED_CPU_SIG_ECX.\r
3080 @retval EDX Extended Processor Signature and Feature Bits information\r
3081 described by the type CPUID_EXTENDED_CPU_SIG_EDX.\r
3082\r
3083 <b>Example usage</b>\r
3084 @code\r
3085 UINT32 Eax;\r
3086 CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r
3087 CPUID_EXTENDED_CPU_SIG_EDX Edx;\r
3088\r
3089 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r
3090 @endcode\r
3091**/\r
28a7ddf0
MK
3092#define CPUID_EXTENDED_CPU_SIG 0x80000001\r
3093\r
57d16ba1
MK
3094/**\r
3095 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf\r
3096 #CPUID_EXTENDED_CPU_SIG.\r
3097**/\r
3098typedef union {\r
3099 ///\r
3100 /// Individual bit fields\r
3101 ///\r
3102 struct {\r
3103 ///\r
3104 /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
3105 ///\r
3106 UINT32 LAHF_SAHF:1;\r
3107 UINT32 Reserved1:4;\r
3108 ///\r
3109 /// [Bit 5] LZCNT.\r
3110 ///\r
3111 UINT32 LZCNT:1;\r
3112 UINT32 Reserved2:2;\r
3113 ///\r
3114 /// [Bit 8] PREFETCHW.\r
3115 ///\r
3116 UINT32 PREFETCHW:1;\r
3117 UINT32 Reserved3:23;\r
3118 } Bits;\r
3119 ///\r
3120 /// All bit fields as a 32-bit value\r
3121 ///\r
3122 UINT32 Uint32;\r
3123} CPUID_EXTENDED_CPU_SIG_ECX;\r
3124\r
3125/**\r
3126 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf\r
3127 #CPUID_EXTENDED_CPU_SIG.\r
3128**/\r
3129typedef union {\r
3130 ///\r
3131 /// Individual bit fields\r
3132 ///\r
3133 struct {\r
3134 UINT32 Reserved1:11;\r
3135 ///\r
3136 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.\r
3137 ///\r
3138 UINT32 SYSCALL_SYSRET:1;\r
3139 UINT32 Reserved2:8;\r
3140 ///\r
3141 /// [Bit 20] Execute Disable Bit available.\r
3142 ///\r
3143 UINT32 NX:1;\r
3144 UINT32 Reserved3:5;\r
3145 ///\r
3146 /// [Bit 26] 1-GByte pages are available if 1.\r
3147 ///\r
3148 UINT32 Page1GB:1;\r
3149 ///\r
3150 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.\r
3151 ///\r
3152 UINT32 RDTSCP:1;\r
3153 UINT32 Reserved4:1;\r
3154 ///\r
3155 /// [Bit 29] Intel(R) 64 Architecture available if 1.\r
3156 ///\r
3157 UINT32 LM:1;\r
3158 UINT32 Reserved5:2;\r
3159 } Bits;\r
3160 ///\r
3161 /// All bit fields as a 32-bit value\r
3162 ///\r
3163 UINT32 Uint32;\r
3164} CPUID_EXTENDED_CPU_SIG_EDX;\r
3165\r
3166\r
3167/**\r
3168 CPUID Processor Brand String\r
3169\r
3170 @param EAX CPUID_BRAND_STRING1 (0x80000002)\r
3171\r
3172 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.\r
3173 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3174 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3175 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3176\r
3177 <b>Example usage</b>\r
3178 @code\r
3179 CPUID_BRAND_STRING_DATA Eax;\r
3180 CPUID_BRAND_STRING_DATA Ebx;\r
3181 CPUID_BRAND_STRING_DATA Ecx;\r
3182 CPUID_BRAND_STRING_DATA Edx;\r
3183\r
3184 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
3185 @endcode\r
3186**/\r
28a7ddf0
MK
3187#define CPUID_BRAND_STRING1 0x80000002\r
3188\r
57d16ba1
MK
3189/**\r
3190 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,\r
3191 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.\r
3192**/\r
3193typedef union {\r
3194 ///\r
3195 /// 4 ASCII characters of Processor Brand String\r
3196 ///\r
3197 CHAR8 BrandString[4];\r
3198 ///\r
3199 /// All fields as a 32-bit value\r
3200 ///\r
3201 UINT32 Uint32;\r
3202} CPUID_BRAND_STRING_DATA;\r
3203\r
3204/**\r
3205 CPUID Processor Brand String\r
3206\r
3207 @param EAX CPUID_BRAND_STRING2 (0x80000003)\r
3208\r
3209 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3210 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3211 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3212 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3213\r
3214 <b>Example usage</b>\r
3215 @code\r
3216 CPUID_BRAND_STRING_DATA Eax;\r
3217 CPUID_BRAND_STRING_DATA Ebx;\r
3218 CPUID_BRAND_STRING_DATA Ecx;\r
3219 CPUID_BRAND_STRING_DATA Edx;\r
3220\r
3221 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
3222 @endcode\r
3223**/\r
28a7ddf0
MK
3224#define CPUID_BRAND_STRING2 0x80000003\r
3225\r
57d16ba1
MK
3226/**\r
3227 CPUID Processor Brand String\r
3228\r
3229 @param EAX CPUID_BRAND_STRING3 (0x80000004)\r
3230\r
3231 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3232 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3233 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3234 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
3235\r
3236 <b>Example usage</b>\r
3237 @code\r
3238 CPUID_BRAND_STRING_DATA Eax;\r
3239 CPUID_BRAND_STRING_DATA Ebx;\r
3240 CPUID_BRAND_STRING_DATA Ecx;\r
3241 CPUID_BRAND_STRING_DATA Edx;\r
3242\r
3243 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
3244 @endcode\r
3245**/\r
28a7ddf0
MK
3246#define CPUID_BRAND_STRING3 0x80000004\r
3247\r
57d16ba1
MK
3248\r
3249/**\r
3250 CPUID Extended Cache information\r
3251\r
3252 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)\r
3253\r
3254 @retval EAX Reserved.\r
3255 @retval EBX Reserved.\r
3256 @retval ECX Extended cache information described by the type\r
3257 CPUID_EXTENDED_CACHE_INFO_ECX.\r
3258 @retval EDX Reserved.\r
3259\r
3260 <b>Example usage</b>\r
3261 @code\r
3262 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r
3263\r
3264 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r
3265 @endcode\r
3266**/\r
3267#define CPUID_EXTENDED_CACHE_INFO 0x80000006\r
3268\r
3269/**\r
3270 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.\r
3271**/\r
3272typedef union {\r
3273 ///\r
3274 /// Individual bit fields\r
3275 ///\r
3276 struct {\r
3277 ///\r
3278 /// [Bits 7:0] Cache line size in bytes.\r
3279 ///\r
3280 UINT32 CacheLineSize:8;\r
3281 UINT32 Reserved:4;\r
3282 ///\r
3283 /// [Bits 15:12] L2 Associativity field. Supported values are in the range\r
3284 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to\r
3285 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL\r
3286 ///\r
3287 UINT32 L2Associativity:4;\r
3288 ///\r
3289 /// [Bits 31:16] Cache size in 1K units.\r
3290 ///\r
3291 UINT32 CacheSize:16;\r
3292 } Bits;\r
3293 ///\r
3294 /// All bit fields as a 32-bit value\r
3295 ///\r
3296 UINT32 Uint32;\r
3297} CPUID_EXTENDED_CACHE_INFO_ECX;\r
3298\r
3299///\r
3300/// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity\r
3301///\r
3302#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00\r
3303#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01\r
3304#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02\r
3305#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04\r
3306#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06\r
3307#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08\r
3308#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F\r
3309///\r
3310/// @}\r
3311///\r
3312\r
3313/**\r
3314 CPUID Extended Time Stamp Counter information\r
3315\r
3316 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)\r
3317\r
3318 @retval EAX Reserved.\r
3319 @retval EBX Reserved.\r
3320 @retval ECX Reserved.\r
3321 @retval EDX Extended time stamp counter (TSC) information described by the\r
3322 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.\r
3323\r
3324 <b>Example usage</b>\r
3325 @code\r
3326 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;\r
3327\r
3328 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r
3329 @endcode\r
3330**/\r
3331#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007\r
3332\r
3333/**\r
3334 CPUID Extended Time Stamp Counter information EDX for CPUID leaf\r
3335 #CPUID_EXTENDED_TIME_STAMP_COUNTER.\r
3336**/\r
3337typedef union {\r
3338 ///\r
3339 /// Individual bit fields\r
3340 ///\r
3341 struct {\r
3342 UINT32 Reserved1:8;\r
3343 ///\r
3344 /// [Bit 8] Invariant TSC available if 1.\r
3345 ///\r
3346 UINT32 InvariantTsc:1;\r
3347 UINT32 Reserved2:23;\r
3348 } Bits;\r
3349 ///\r
3350 /// All bit fields as a 32-bit value\r
3351 ///\r
3352 UINT32 Uint32;\r
3353} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;\r
3354\r
3355\r
3356/**\r
3357 CPUID Linear Physical Address Size\r
3358\r
3359 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r
3360\r
3361 @retval EAX Linear/Physical Address Size described by the type\r
3362 CPUID_VIR_PHY_ADDRESS_SIZE_EAX.\r
3363 @retval EBX Reserved.\r
3364 @retval ECX Reserved.\r
3365 @retval EDX Reserved.\r
3366\r
3367 <b>Example usage</b>\r
3368 @code\r
3369 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;\r
3370\r
3371 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r
3372 @endcode\r
3373**/\r
28a7ddf0
MK
3374#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
3375\r
57d16ba1
MK
3376/**\r
3377 CPUID Linear Physical Address Size EAX for CPUID leaf\r
3378 #CPUID_VIR_PHY_ADDRESS_SIZE.\r
3379**/\r
3380typedef union {\r
3381 ///\r
3382 /// Individual bit fields\r
3383 ///\r
3384 struct {\r
3385 ///\r
3386 /// [Bits 7:0] Number of physical address bits.\r
3387 ///\r
3388 /// @note\r
3389 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address\r
3390 /// number supported should come from this field.\r
3391 ///\r
3392 UINT32 PhysicalAddressBits:8;\r
3393 ///\r
3394 /// [Bits 15:8] Number of linear address bits.\r
3395 ///\r
3396 UINT32 LinearAddressBits:8;\r
3397 UINT32 Reserved:16;\r
3398 } Bits;\r
3399 ///\r
3400 /// All bit fields as a 32-bit value\r
3401 ///\r
3402 UINT32 Uint32;\r
3403} CPUID_VIR_PHY_ADDRESS_SIZE_EAX;\r
3404\r
28a7ddf0 3405#endif\r