projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 84ada87c MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| f4c982bf | 9 | Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r |
| 84ada87c MK |
10 | This program and the accompanying materials\r |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| 19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 0f16be6d | 20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10.\r |
| 84ada87c MK |
21 | \r |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __IVY_BRIDGE_MSR_H__\r | |
| 25 | #define __IVY_BRIDGE_MSR_H__\r | |
| 26 | \r | |
| 27 | #include <Register/ArchitecturalMsr.h>\r | |
| 28 | \r | |
| f4c982bf JF |
29 | /**\r |
| 30 | Is Intel processors based on the Ivy Bridge microarchitecture?\r | |
| 31 | \r | |
| 32 | @param DisplayFamily Display Family ID\r | |
| 33 | @param DisplayModel Display Model ID\r | |
| 34 | \r | |
| 35 | @retval TRUE Yes, it is.\r | |
| 36 | @retval FALSE No, it isn't.\r | |
| 37 | **/\r | |
| 38 | #define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 39 | (DisplayFamily == 0x06 && \\r | |
| 40 | ( \\r | |
| 41 | DisplayModel == 0x3A \\r | |
| 42 | ) \\r | |
| 43 | )\r | |
| 44 | \r | |
| 84ada87c MK |
45 | /**\r |
| 46 | Package. See http://biosbits.org.\r | |
| 47 | \r | |
| 48 | @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)\r | |
| 49 | @param EAX Lower 32-bits of MSR value.\r | |
| 50 | Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r | |
| 51 | @param EDX Upper 32-bits of MSR value.\r | |
| 52 | Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r | |
| 53 | \r | |
| 54 | <b>Example usage</b>\r | |
| 55 | @code\r | |
| 56 | MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r | |
| 57 | \r | |
| 58 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);\r | |
| 59 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r | |
| 60 | @endcode\r | |
| fed6c37b | 61 | @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
| 84ada87c MK |
62 | **/\r |
| 63 | #define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r | |
| 64 | \r | |
| 65 | /**\r | |
| 66 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO\r | |
| 67 | **/\r | |
| 68 | typedef union {\r | |
| 69 | ///\r | |
| 70 | /// Individual bit fields\r | |
| 71 | ///\r | |
| 72 | struct {\r | |
| 73 | UINT32 Reserved1:8;\r | |
| 74 | ///\r | |
| 75 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 76 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
| 77 | /// MHz.\r | |
| 78 | ///\r | |
| 79 | UINT32 MaximumNonTurboRatio:8;\r | |
| 80 | UINT32 Reserved2:12;\r | |
| 81 | ///\r | |
| 82 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 83 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 84 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 85 | /// Turbo mode is disabled.\r | |
| 86 | ///\r | |
| 87 | UINT32 RatioLimit:1;\r | |
| 88 | ///\r | |
| 89 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
| 90 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
| 91 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
| 92 | /// programmable.\r | |
| 93 | ///\r | |
| 94 | UINT32 TDPLimit:1;\r | |
| 95 | UINT32 Reserved3:2;\r | |
| 96 | ///\r | |
| 97 | /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r | |
| 98 | /// indicates that LPM is supported, and when set to 0, indicates LPM is\r | |
| 99 | /// not supported.\r | |
| 100 | ///\r | |
| 101 | UINT32 LowPowerModeSupport:1;\r | |
| 102 | ///\r | |
| 103 | /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r | |
| 104 | /// TDP level available. 01: One additional TDP level available. 02: Two\r | |
| 105 | /// additional TDP level available. 11: Reserved.\r | |
| 106 | ///\r | |
| 107 | UINT32 ConfigTDPLevels:2;\r | |
| 108 | UINT32 Reserved4:5;\r | |
| 109 | ///\r | |
| 110 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 111 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 112 | /// units of 100MHz.\r | |
| 113 | ///\r | |
| 114 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 115 | ///\r | |
| 116 | /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r | |
| 117 | /// minimum supported operating ratio in units of 100 MHz.\r | |
| 118 | ///\r | |
| 119 | UINT32 MinimumOperatingRatio:8;\r | |
| 120 | UINT32 Reserved5:8;\r | |
| 121 | } Bits;\r | |
| 122 | ///\r | |
| 123 | /// All bit fields as a 64-bit value\r | |
| 124 | ///\r | |
| 125 | UINT64 Uint64;\r | |
| 126 | } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;\r | |
| 127 | \r | |
| 128 | \r | |
| 129 | /**\r | |
| 130 | Core. C-State Configuration Control (R/W) Note: C-state values are\r | |
| 131 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
| 132 | parameters or ACPI C-States. See http://biosbits.org.\r | |
| 133 | \r | |
| 134 | @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 135 | @param EAX Lower 32-bits of MSR value.\r | |
| 136 | Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 137 | @param EDX Upper 32-bits of MSR value.\r | |
| 138 | Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 139 | \r | |
| 140 | <b>Example usage</b>\r | |
| 141 | @code\r | |
| 142 | MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 143 | \r | |
| 144 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r | |
| 145 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 146 | @endcode\r | |
| fed6c37b | 147 | @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
| 84ada87c MK |
148 | **/\r |
| 149 | #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
| 150 | \r | |
| 151 | /**\r | |
| 152 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL\r | |
| 153 | **/\r | |
| 154 | typedef union {\r | |
| 155 | ///\r | |
| 156 | /// Individual bit fields\r | |
| 157 | ///\r | |
| 158 | struct {\r | |
| 159 | ///\r | |
| 160 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 161 | /// processor-specific C-state code name (consuming the least power). for\r | |
| 162 | /// the package. The default is set as factory-configured package C-state\r | |
| 163 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
| 164 | /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r | |
| 165 | /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r | |
| 166 | /// This field cannot be used to limit package C-state to C3.\r | |
| 167 | ///\r | |
| 168 | UINT32 Limit:3;\r | |
| 169 | UINT32 Reserved1:7;\r | |
| 170 | ///\r | |
| 171 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r | |
| 172 | /// IO_read instructions sent to IO register specified by\r | |
| 173 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r | |
| 174 | ///\r | |
| 175 | UINT32 IO_MWAIT:1;\r | |
| 176 | UINT32 Reserved2:4;\r | |
| 177 | ///\r | |
| 178 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r | |
| 179 | /// until next reset.\r | |
| 180 | ///\r | |
| 181 | UINT32 CFGLock:1;\r | |
| 182 | UINT32 Reserved3:9;\r | |
| 183 | ///\r | |
| 184 | /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r | |
| 185 | /// will conditionally demote C6/C7 requests to C3 based on uncore\r | |
| 186 | /// auto-demote information.\r | |
| 187 | ///\r | |
| 188 | UINT32 C3AutoDemotion:1;\r | |
| 189 | ///\r | |
| 190 | /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r | |
| 191 | /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r | |
| 192 | /// auto-demote information.\r | |
| 193 | ///\r | |
| 194 | UINT32 C1AutoDemotion:1;\r | |
| 195 | ///\r | |
| 196 | /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r | |
| 197 | /// demoted C3.\r | |
| 198 | ///\r | |
| 199 | UINT32 C3Undemotion:1;\r | |
| 200 | ///\r | |
| 201 | /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r | |
| 202 | /// demoted C1.\r | |
| 203 | ///\r | |
| 204 | UINT32 C1Undemotion:1;\r | |
| 205 | UINT32 Reserved4:3;\r | |
| 206 | UINT32 Reserved5:32;\r | |
| 207 | } Bits;\r | |
| 208 | ///\r | |
| 209 | /// All bit fields as a 32-bit value\r | |
| 210 | ///\r | |
| 211 | UINT32 Uint32;\r | |
| 212 | ///\r | |
| 213 | /// All bit fields as a 64-bit value\r | |
| 214 | ///\r | |
| 215 | UINT64 Uint64;\r | |
| 216 | } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
| 217 | \r | |
| 218 | \r | |
| 0f16be6d HW |
219 | /**\r |
| 220 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 221 | Domains.".\r | |
| 222 | \r | |
| 223 | @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r | |
| 224 | @param EAX Lower 32-bits of MSR value.\r | |
| 225 | @param EDX Upper 32-bits of MSR value.\r | |
| 226 | \r | |
| 227 | <b>Example usage</b>\r | |
| 228 | @code\r | |
| 229 | UINT64 Msr;\r | |
| 230 | \r | |
| 231 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);\r | |
| 232 | @endcode\r | |
| 233 | @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
| 234 | **/\r | |
| 235 | #define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r | |
| 236 | \r | |
| 237 | \r | |
| 84ada87c MK |
238 | /**\r |
| 239 | Package. Base TDP Ratio (R/O).\r | |
| 240 | \r | |
| 241 | @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)\r | |
| 242 | @param EAX Lower 32-bits of MSR value.\r | |
| 243 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r | |
| 244 | @param EDX Upper 32-bits of MSR value.\r | |
| 245 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r | |
| 246 | \r | |
| 247 | <b>Example usage</b>\r | |
| 248 | @code\r | |
| 249 | MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;\r | |
| 250 | \r | |
| 251 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);\r | |
| 252 | @endcode\r | |
| fed6c37b | 253 | @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r |
| 84ada87c MK |
254 | **/\r |
| 255 | #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r | |
| 256 | \r | |
| 257 | /**\r | |
| 258 | MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL\r | |
| 259 | **/\r | |
| 260 | typedef union {\r | |
| 261 | ///\r | |
| 262 | /// Individual bit fields\r | |
| 263 | ///\r | |
| 264 | struct {\r | |
| 265 | ///\r | |
| 266 | /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r | |
| 267 | /// specific processor (in units of 100 MHz).\r | |
| 268 | ///\r | |
| 269 | UINT32 Config_TDP_Base:8;\r | |
| 270 | UINT32 Reserved1:24;\r | |
| 271 | UINT32 Reserved2:32;\r | |
| 272 | } Bits;\r | |
| 273 | ///\r | |
| 274 | /// All bit fields as a 32-bit value\r | |
| 275 | ///\r | |
| 276 | UINT32 Uint32;\r | |
| 277 | ///\r | |
| 278 | /// All bit fields as a 64-bit value\r | |
| 279 | ///\r | |
| 280 | UINT64 Uint64;\r | |
| 281 | } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;\r | |
| 282 | \r | |
| 283 | \r | |
| 284 | /**\r | |
| 285 | Package. ConfigTDP Level 1 ratio and power level (R/O).\r | |
| 286 | \r | |
| 287 | @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)\r | |
| 288 | @param EAX Lower 32-bits of MSR value.\r | |
| 289 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r | |
| 290 | @param EDX Upper 32-bits of MSR value.\r | |
| 291 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r | |
| 292 | \r | |
| 293 | <b>Example usage</b>\r | |
| 294 | @code\r | |
| 295 | MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;\r | |
| 296 | \r | |
| 297 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);\r | |
| 298 | @endcode\r | |
| fed6c37b | 299 | @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r |
| 84ada87c MK |
300 | **/\r |
| 301 | #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r | |
| 302 | \r | |
| 303 | /**\r | |
| 304 | MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1\r | |
| 305 | **/\r | |
| 306 | typedef union {\r | |
| 307 | ///\r | |
| 308 | /// Individual bit fields\r | |
| 309 | ///\r | |
| 310 | struct {\r | |
| 311 | ///\r | |
| 312 | /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r | |
| 313 | ///\r | |
| 314 | UINT32 PKG_TDP_LVL1:15;\r | |
| 315 | UINT32 Reserved1:1;\r | |
| 316 | ///\r | |
| 317 | /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r | |
| 318 | /// for this specific processor.\r | |
| 319 | ///\r | |
| 320 | UINT32 Config_TDP_LVL1_Ratio:8;\r | |
| 321 | UINT32 Reserved2:8;\r | |
| 322 | ///\r | |
| 323 | /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r | |
| 324 | /// Level 1.\r | |
| 325 | ///\r | |
| 326 | UINT32 PKG_MAX_PWR_LVL1:15;\r | |
| 327 | UINT32 Reserved3:1;\r | |
| 328 | ///\r | |
| 329 | /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r | |
| 330 | /// Level 1.\r | |
| 331 | ///\r | |
| 332 | UINT32 PKG_MIN_PWR_LVL1:15;\r | |
| 333 | UINT32 Reserved4:1;\r | |
| 334 | } Bits;\r | |
| 335 | ///\r | |
| 336 | /// All bit fields as a 64-bit value\r | |
| 337 | ///\r | |
| 338 | UINT64 Uint64;\r | |
| 339 | } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;\r | |
| 340 | \r | |
| 341 | \r | |
| 342 | /**\r | |
| 343 | Package. ConfigTDP Level 2 ratio and power level (R/O).\r | |
| 344 | \r | |
| 345 | @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)\r | |
| 346 | @param EAX Lower 32-bits of MSR value.\r | |
| 347 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r | |
| 348 | @param EDX Upper 32-bits of MSR value.\r | |
| 349 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r | |
| 350 | \r | |
| 351 | <b>Example usage</b>\r | |
| 352 | @code\r | |
| 353 | MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;\r | |
| 354 | \r | |
| 355 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);\r | |
| 356 | @endcode\r | |
| fed6c37b | 357 | @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r |
| 84ada87c MK |
358 | **/\r |
| 359 | #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r | |
| 360 | \r | |
| 361 | /**\r | |
| 362 | MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2\r | |
| 363 | **/\r | |
| 364 | typedef union {\r | |
| 365 | ///\r | |
| 366 | /// Individual bit fields\r | |
| 367 | ///\r | |
| 368 | struct {\r | |
| 369 | ///\r | |
| 370 | /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r | |
| 371 | ///\r | |
| 372 | UINT32 PKG_TDP_LVL2:15;\r | |
| 373 | UINT32 Reserved1:1;\r | |
| 374 | ///\r | |
| 375 | /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r | |
| 376 | /// for this specific processor.\r | |
| 377 | ///\r | |
| 378 | UINT32 Config_TDP_LVL2_Ratio:8;\r | |
| 379 | UINT32 Reserved2:8;\r | |
| 380 | ///\r | |
| 381 | /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r | |
| 382 | /// Level 2.\r | |
| 383 | ///\r | |
| 384 | UINT32 PKG_MAX_PWR_LVL2:15;\r | |
| 385 | UINT32 Reserved3:1;\r | |
| 386 | ///\r | |
| 387 | /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r | |
| 388 | /// Level 2.\r | |
| 389 | ///\r | |
| 390 | UINT32 PKG_MIN_PWR_LVL2:15;\r | |
| 391 | UINT32 Reserved4:1;\r | |
| 392 | } Bits;\r | |
| 393 | ///\r | |
| 394 | /// All bit fields as a 64-bit value\r | |
| 395 | ///\r | |
| 396 | UINT64 Uint64;\r | |
| 397 | } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;\r | |
| 398 | \r | |
| 399 | \r | |
| 400 | /**\r | |
| 401 | Package. ConfigTDP Control (R/W).\r | |
| 402 | \r | |
| 403 | @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)\r | |
| 404 | @param EAX Lower 32-bits of MSR value.\r | |
| 405 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r | |
| 406 | @param EDX Upper 32-bits of MSR value.\r | |
| 407 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r | |
| 408 | \r | |
| 409 | <b>Example usage</b>\r | |
| 410 | @code\r | |
| 411 | MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;\r | |
| 412 | \r | |
| 413 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);\r | |
| 414 | AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);\r | |
| 415 | @endcode\r | |
| fed6c37b | 416 | @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r |
| 84ada87c MK |
417 | **/\r |
| 418 | #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r | |
| 419 | \r | |
| 420 | /**\r | |
| 421 | MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL\r | |
| 422 | **/\r | |
| 423 | typedef union {\r | |
| 424 | ///\r | |
| 425 | /// Individual bit fields\r | |
| 426 | ///\r | |
| 427 | struct {\r | |
| 428 | ///\r | |
| 429 | /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r | |
| 430 | ///\r | |
| 431 | UINT32 TDP_LEVEL:2;\r | |
| 432 | UINT32 Reserved1:29;\r | |
| 433 | ///\r | |
| 434 | /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r | |
| 435 | /// this register is locked until a reset.\r | |
| 436 | ///\r | |
| 437 | UINT32 Config_TDP_Lock:1;\r | |
| 438 | UINT32 Reserved2:32;\r | |
| 439 | } Bits;\r | |
| 440 | ///\r | |
| 441 | /// All bit fields as a 32-bit value\r | |
| 442 | ///\r | |
| 443 | UINT32 Uint32;\r | |
| 444 | ///\r | |
| 445 | /// All bit fields as a 64-bit value\r | |
| 446 | ///\r | |
| 447 | UINT64 Uint64;\r | |
| 448 | } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;\r | |
| 449 | \r | |
| 450 | \r | |
| 451 | /**\r | |
| 452 | Package. ConfigTDP Control (R/W).\r | |
| 453 | \r | |
| 454 | @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
| 455 | @param EAX Lower 32-bits of MSR value.\r | |
| 456 | Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 457 | @param EDX Upper 32-bits of MSR value.\r | |
| 458 | Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 459 | \r | |
| 460 | <b>Example usage</b>\r | |
| 461 | @code\r | |
| 462 | MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r | |
| 463 | \r | |
| 464 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);\r | |
| 465 | AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r | |
| 466 | @endcode\r | |
| fed6c37b | 467 | @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r |
| 84ada87c MK |
468 | **/\r |
| 469 | #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r | |
| 470 | \r | |
| 471 | /**\r | |
| 472 | MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO\r | |
| 473 | **/\r | |
| 474 | typedef union {\r | |
| 475 | ///\r | |
| 476 | /// Individual bit fields\r | |
| 477 | ///\r | |
| 478 | struct {\r | |
| 479 | ///\r | |
| 480 | /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r | |
| 481 | /// field.\r | |
| 482 | ///\r | |
| 483 | UINT32 MAX_NON_TURBO_RATIO:8;\r | |
| 484 | UINT32 Reserved1:23;\r | |
| 485 | ///\r | |
| 486 | /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r | |
| 487 | /// content of this register is locked until a reset.\r | |
| 488 | ///\r | |
| 489 | UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r | |
| 490 | UINT32 Reserved2:32;\r | |
| 491 | } Bits;\r | |
| 492 | ///\r | |
| 493 | /// All bit fields as a 32-bit value\r | |
| 494 | ///\r | |
| 495 | UINT32 Uint32;\r | |
| 496 | ///\r | |
| 497 | /// All bit fields as a 64-bit value\r | |
| 498 | ///\r | |
| 499 | UINT64 Uint64;\r | |
| 500 | } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;\r | |
| 501 | \r | |
| 502 | \r | |
| 503 | /**\r | |
| 504 | Package. Protected Processor Inventory Number Enable Control (R/W).\r | |
| 505 | \r | |
| 506 | @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)\r | |
| 507 | @param EAX Lower 32-bits of MSR value.\r | |
| 508 | Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r | |
| 509 | @param EDX Upper 32-bits of MSR value.\r | |
| 510 | Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r | |
| 511 | \r | |
| 512 | <b>Example usage</b>\r | |
| 513 | @code\r | |
| 514 | MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;\r | |
| 515 | \r | |
| 516 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r | |
| 517 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);\r | |
| 518 | @endcode\r | |
| fed6c37b | 519 | @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r |
| 84ada87c MK |
520 | **/\r |
| 521 | #define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r | |
| 522 | \r | |
| 523 | /**\r | |
| 524 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL\r | |
| 525 | **/\r | |
| 526 | typedef union {\r | |
| 527 | ///\r | |
| 528 | /// Individual bit fields\r | |
| 529 | ///\r | |
| 530 | struct {\r | |
| 531 | ///\r | |
| 532 | /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.\r | |
| 533 | /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit\r | |
| 534 | /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to\r | |
| 535 | /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged\r | |
| 536 | /// inventory initialization agent to access MSR_PPIN. After reading\r | |
| 537 | /// MSR_PPIN, the privileged inventory initialization agent should write\r | |
| 538 | /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r | |
| 539 | /// prevent unauthorized modification to MSR_PPIN_CTL.\r | |
| 540 | ///\r | |
| 541 | UINT32 LockOut:1;\r | |
| 542 | ///\r | |
| 543 | /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r | |
| 544 | /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will\r | |
| 545 | /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default\r | |
| 546 | /// is 0.\r | |
| 547 | ///\r | |
| 548 | UINT32 Enable_PPIN:1;\r | |
| 549 | UINT32 Reserved1:30;\r | |
| 550 | UINT32 Reserved2:32;\r | |
| 551 | } Bits;\r | |
| 552 | ///\r | |
| 553 | /// All bit fields as a 32-bit value\r | |
| 554 | ///\r | |
| 555 | UINT32 Uint32;\r | |
| 556 | ///\r | |
| 557 | /// All bit fields as a 64-bit value\r | |
| 558 | ///\r | |
| 559 | UINT64 Uint64;\r | |
| 560 | } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;\r | |
| 561 | \r | |
| 562 | \r | |
| 563 | /**\r | |
| 564 | Package. Protected Processor Inventory Number (R/O). Protected Processor\r | |
| 565 | Inventory Number (R/O) A unique value within a given CPUID\r | |
| 566 | family/model/stepping signature that a privileged inventory initialization\r | |
| 567 | agent can access to identify each physical processor, when access to\r | |
| 568 | MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r | |
| 569 | MSR_PPIN_CTL[bits 1:0] = '10b'.\r | |
| 570 | \r | |
| 571 | @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)\r | |
| 572 | @param EAX Lower 32-bits of MSR value.\r | |
| 573 | @param EDX Upper 32-bits of MSR value.\r | |
| 574 | \r | |
| 575 | <b>Example usage</b>\r | |
| 576 | @code\r | |
| 577 | UINT64 Msr;\r | |
| 578 | \r | |
| 579 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);\r | |
| 580 | @endcode\r | |
| fed6c37b | 581 | @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.\r |
| 84ada87c MK |
582 | **/\r |
| 583 | #define MSR_IVY_BRIDGE_PPIN 0x0000004F\r | |
| 584 | \r | |
| 585 | \r | |
| 586 | /**\r | |
| 587 | Package. See http://biosbits.org.\r | |
| 588 | \r | |
| 589 | @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)\r | |
| 590 | @param EAX Lower 32-bits of MSR value.\r | |
| 591 | Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r | |
| 592 | @param EDX Upper 32-bits of MSR value.\r | |
| 593 | Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r | |
| 594 | \r | |
| 595 | <b>Example usage</b>\r | |
| 596 | @code\r | |
| 597 | MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;\r | |
| 598 | \r | |
| 599 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r | |
| 600 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);\r | |
| 601 | @endcode\r | |
| fed6c37b | 602 | @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.\r |
| 84ada87c MK |
603 | **/\r |
| 604 | #define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r | |
| 605 | \r | |
| 606 | /**\r | |
| 607 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1\r | |
| 608 | **/\r | |
| 609 | typedef union {\r | |
| 610 | ///\r | |
| 611 | /// Individual bit fields\r | |
| 612 | ///\r | |
| 613 | struct {\r | |
| 614 | UINT32 Reserved1:8;\r | |
| 615 | ///\r | |
| 616 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 617 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
| 618 | /// MHz.\r | |
| 619 | ///\r | |
| 620 | UINT32 MaximumNonTurboRatio:8;\r | |
| 621 | UINT32 Reserved2:7;\r | |
| 622 | ///\r | |
| 623 | /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that\r | |
| 624 | /// Protected Processor Inventory Number (PPIN) capability can be enabled\r | |
| 625 | /// for privileged system inventory agent to read PPIN from MSR_PPIN. When\r | |
| 626 | /// set to 0, PPIN capability is not supported. An attempt to access\r | |
| 627 | /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.\r | |
| 628 | ///\r | |
| 629 | UINT32 PPIN_CAP:1;\r | |
| 630 | UINT32 Reserved3:4;\r | |
| 631 | ///\r | |
| 632 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 633 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 634 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 635 | /// Turbo mode is disabled.\r | |
| 636 | ///\r | |
| 637 | UINT32 RatioLimit:1;\r | |
| 638 | ///\r | |
| 639 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
| 640 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
| 641 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
| 642 | /// programmable.\r | |
| 643 | ///\r | |
| 644 | UINT32 TDPLimit:1;\r | |
| 645 | ///\r | |
| 646 | /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r | |
| 647 | /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r | |
| 648 | /// specify an temperature offset.\r | |
| 649 | ///\r | |
| 650 | UINT32 TJOFFSET:1;\r | |
| 651 | UINT32 Reserved4:1;\r | |
| 652 | UINT32 Reserved5:8;\r | |
| 653 | ///\r | |
| 654 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 655 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 656 | /// units of 100MHz.\r | |
| 657 | ///\r | |
| 658 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 659 | UINT32 Reserved6:16;\r | |
| 660 | } Bits;\r | |
| 661 | ///\r | |
| 662 | /// All bit fields as a 64-bit value\r | |
| 663 | ///\r | |
| 664 | UINT64 Uint64;\r | |
| 665 | } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;\r | |
| 666 | \r | |
| 667 | \r | |
| 668 | /**\r | |
| 669 | Package. MC Bank Error Configuration (R/W).\r | |
| 670 | \r | |
| 671 | @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)\r | |
| 672 | @param EAX Lower 32-bits of MSR value.\r | |
| 673 | Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r | |
| 674 | @param EDX Upper 32-bits of MSR value.\r | |
| 675 | Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r | |
| 676 | \r | |
| 677 | <b>Example usage</b>\r | |
| 678 | @code\r | |
| 679 | MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r | |
| 680 | \r | |
| 681 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);\r | |
| 682 | AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r | |
| 683 | @endcode\r | |
| fed6c37b | 684 | @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r |
| 84ada87c MK |
685 | **/\r |
| 686 | #define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r | |
| 687 | \r | |
| 688 | /**\r | |
| 689 | MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL\r | |
| 690 | **/\r | |
| 691 | typedef union {\r | |
| 692 | ///\r | |
| 693 | /// Individual bit fields\r | |
| 694 | ///\r | |
| 695 | struct {\r | |
| 696 | UINT32 Reserved1:1;\r | |
| 697 | ///\r | |
| 698 | /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r | |
| 699 | /// to log additional info in bits 36:32.\r | |
| 700 | ///\r | |
| 701 | UINT32 MemErrorLogEnable:1;\r | |
| 702 | UINT32 Reserved2:30;\r | |
| 703 | UINT32 Reserved3:32;\r | |
| 704 | } Bits;\r | |
| 705 | ///\r | |
| 706 | /// All bit fields as a 32-bit value\r | |
| 707 | ///\r | |
| 708 | UINT32 Uint32;\r | |
| 709 | ///\r | |
| 710 | /// All bit fields as a 64-bit value\r | |
| 711 | ///\r | |
| 712 | UINT64 Uint64;\r | |
| 713 | } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;\r | |
| 714 | \r | |
| 715 | \r | |
| 716 | /**\r | |
| 717 | Package.\r | |
| 718 | \r | |
| 719 | @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r | |
| 720 | @param EAX Lower 32-bits of MSR value.\r | |
| 721 | Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r | |
| 722 | @param EDX Upper 32-bits of MSR value.\r | |
| 723 | Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r | |
| 724 | \r | |
| 725 | <b>Example usage</b>\r | |
| 726 | @code\r | |
| 727 | MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r | |
| 728 | \r | |
| 729 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);\r | |
| 730 | AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r | |
| 731 | @endcode\r | |
| fed6c37b | 732 | @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r |
| 84ada87c MK |
733 | **/\r |
| 734 | #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r | |
| 735 | \r | |
| 736 | /**\r | |
| 737 | MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET\r | |
| 738 | **/\r | |
| 739 | typedef union {\r | |
| 740 | ///\r | |
| 741 | /// Individual bit fields\r | |
| 742 | ///\r | |
| 743 | struct {\r | |
| 744 | UINT32 Reserved1:16;\r | |
| 745 | ///\r | |
| 746 | /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which\r | |
| 747 | /// PROCHOT# will be asserted. The value is degree C.\r | |
| 748 | ///\r | |
| 749 | UINT32 TemperatureTarget:8;\r | |
| 750 | ///\r | |
| 751 | /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature\r | |
| 752 | /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#\r | |
| 753 | /// will assert at the offset target temperature. Write is permitted only\r | |
| 754 | /// MSR_PLATFORM_INFO.[30] is set.\r | |
| 755 | ///\r | |
| 756 | UINT32 TCCActivationOffset:4;\r | |
| 757 | UINT32 Reserved2:4;\r | |
| 758 | UINT32 Reserved3:32;\r | |
| 759 | } Bits;\r | |
| 760 | ///\r | |
| 761 | /// All bit fields as a 32-bit value\r | |
| 762 | ///\r | |
| 763 | UINT32 Uint32;\r | |
| 764 | ///\r | |
| 765 | /// All bit fields as a 64-bit value\r | |
| 766 | ///\r | |
| 767 | UINT64 Uint64;\r | |
| 768 | } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r | |
| 769 | \r | |
| 770 | \r | |
| 771 | /**\r | |
| 772 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 773 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 774 | \r | |
| 775 | @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)\r | |
| 776 | @param EAX Lower 32-bits of MSR value.\r | |
| 777 | Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r | |
| 778 | @param EDX Upper 32-bits of MSR value.\r | |
| 779 | Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r | |
| 780 | \r | |
| 781 | <b>Example usage</b>\r | |
| 782 | @code\r | |
| 783 | MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;\r | |
| 784 | \r | |
| 785 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);\r | |
| 786 | @endcode\r | |
| fed6c37b | 787 | @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r |
| 84ada87c MK |
788 | **/\r |
| 789 | #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r | |
| 790 | \r | |
| 791 | /**\r | |
| 792 | MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1\r | |
| 793 | **/\r | |
| 794 | typedef union {\r | |
| 795 | ///\r | |
| 796 | /// Individual bit fields\r | |
| 797 | ///\r | |
| 798 | struct {\r | |
| 799 | ///\r | |
| 800 | /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r | |
| 801 | /// limit of 9 core active.\r | |
| 802 | ///\r | |
| 803 | UINT32 Maximum9C:8;\r | |
| 804 | ///\r | |
| 805 | /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r | |
| 806 | /// limit of 10core active.\r | |
| 807 | ///\r | |
| 808 | UINT32 Maximum10C:8;\r | |
| 809 | ///\r | |
| 810 | /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r | |
| 811 | /// limit of 11 core active.\r | |
| 812 | ///\r | |
| 813 | UINT32 Maximum11C:8;\r | |
| 814 | ///\r | |
| 815 | /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r | |
| 816 | /// limit of 12 core active.\r | |
| 817 | ///\r | |
| 818 | UINT32 Maximum12C:8;\r | |
| 819 | ///\r | |
| 820 | /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r | |
| 821 | /// limit of 13 core active.\r | |
| 822 | ///\r | |
| 823 | UINT32 Maximum13C:8;\r | |
| 824 | ///\r | |
| 825 | /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r | |
| 826 | /// limit of 14 core active.\r | |
| 827 | ///\r | |
| 828 | UINT32 Maximum14C:8;\r | |
| 829 | ///\r | |
| 830 | /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r | |
| 831 | /// limit of 15 core active.\r | |
| 832 | ///\r | |
| 833 | UINT32 Maximum15C:8;\r | |
| 834 | UINT32 Reserved:7;\r | |
| 835 | ///\r | |
| 836 | /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r | |
| 837 | /// the processor uses override configuration specified in\r | |
| 838 | /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r | |
| 839 | /// uses factory-set configuration (Default).\r | |
| 840 | ///\r | |
| 841 | UINT32 TurboRatioLimitConfigurationSemaphore:1;\r | |
| 842 | } Bits;\r | |
| 843 | ///\r | |
| 844 | /// All bit fields as a 64-bit value\r | |
| 845 | ///\r | |
| 846 | UINT64 Uint64;\r | |
| 847 | } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;\r | |
| 848 | \r | |
| 849 | \r | |
| 850 | /**\r | |
| 0f16be6d | 851 | Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r |
| 84ada87c | 852 | \r |
| 0f16be6d | 853 | @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)\r |
| 84ada87c | 854 | @param EAX Lower 32-bits of MSR value.\r |
| 0f16be6d | 855 | Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r |
| 84ada87c | 856 | @param EDX Upper 32-bits of MSR value.\r |
| 0f16be6d | 857 | Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r |
| 84ada87c MK |
858 | \r |
| 859 | <b>Example usage</b>\r | |
| 860 | @code\r | |
| 0f16be6d | 861 | MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;\r |
| 84ada87c | 862 | \r |
| 0f16be6d | 863 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r |
| 84ada87c | 864 | @endcode\r |
| 0f16be6d | 865 | @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r |
| 84ada87c | 866 | **/\r |
| 0f16be6d HW |
867 | #define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r |
| 868 | \r | |
| 869 | /**\r | |
| 870 | MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r | |
| 871 | **/\r | |
| 872 | typedef union {\r | |
| 873 | ///\r | |
| 874 | /// Individual bit fields\r | |
| 875 | ///\r | |
| 876 | struct {\r | |
| 877 | ///\r | |
| 878 | /// [Bits 5:0] Recoverable Address LSB.\r | |
| 879 | ///\r | |
| 880 | UINT32 RecoverableAddressLSB:6;\r | |
| 881 | ///\r | |
| 882 | /// [Bits 8:6] Address Mode.\r | |
| 883 | ///\r | |
| 884 | UINT32 AddressMode:3;\r | |
| 885 | UINT32 Reserved1:7;\r | |
| 886 | ///\r | |
| 887 | /// [Bits 31:16] PCI Express Requestor ID.\r | |
| 888 | ///\r | |
| 889 | UINT32 PCIExpressRequestorID:16;\r | |
| 890 | ///\r | |
| 891 | /// [Bits 39:32] PCI Express Segment Number.\r | |
| 892 | ///\r | |
| 893 | UINT32 PCIExpressSegmentNumber:8;\r | |
| 894 | UINT32 Reserved2:24;\r | |
| 895 | } Bits;\r | |
| 896 | ///\r | |
| 897 | /// All bit fields as a 64-bit value\r | |
| 898 | ///\r | |
| 899 | UINT64 Uint64;\r | |
| 900 | } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r | |
| 84ada87c MK |
901 | \r |
| 902 | \r | |
| 903 | /**\r | |
| 904 | Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r | |
| 905 | 15.3.2.4, "IA32_MCi_MISC MSRs.".\r | |
| 906 | \r | |
| 0f16be6d HW |
907 | Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r |
| 908 | and its corresponding slice of L3.\r | |
| 84ada87c | 909 | \r |
| 0f16be6d | 910 | @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL\r |
| 84ada87c MK |
911 | @param EAX Lower 32-bits of MSR value.\r |
| 912 | @param EDX Upper 32-bits of MSR value.\r | |
| 913 | \r | |
| 914 | <b>Example usage</b>\r | |
| 915 | @code\r | |
| 916 | UINT64 Msr;\r | |
| 917 | \r | |
| 0f16be6d HW |
918 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);\r |
| 919 | AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);\r | |
| 84ada87c | 920 | @endcode\r |
| 0f16be6d HW |
921 | @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.\r |
| 922 | MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.\r | |
| 923 | MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.\r | |
| 84ada87c MK |
924 | @{\r |
| 925 | **/\r | |
| 0f16be6d HW |
926 | #define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r |
| 927 | #define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r | |
| 928 | #define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r | |
| 84ada87c MK |
929 | /// @}\r |
| 930 | \r | |
| 931 | \r | |
| 932 | /**\r | |
| 933 | Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r | |
| 934 | 15.3.2.4, "IA32_MCi_MISC MSRs.".\r | |
| 935 | \r | |
| 0f16be6d HW |
936 | Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r |
| 937 | and its corresponding slice of L3.\r | |
| 938 | \r | |
| 939 | @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS\r | |
| 84ada87c MK |
940 | @param EAX Lower 32-bits of MSR value.\r |
| 941 | @param EDX Upper 32-bits of MSR value.\r | |
| 942 | \r | |
| 943 | <b>Example usage</b>\r | |
| 944 | @code\r | |
| 945 | UINT64 Msr;\r | |
| 946 | \r | |
| 0f16be6d HW |
947 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);\r |
| 948 | AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);\r | |
| 84ada87c | 949 | @endcode\r |
| 0f16be6d HW |
950 | @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.\r |
| 951 | MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.\r | |
| 952 | MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.\r | |
| 84ada87c MK |
953 | @{\r |
| 954 | **/\r | |
| 0f16be6d HW |
955 | #define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r |
| 956 | #define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r | |
| 957 | #define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r | |
| 84ada87c MK |
958 | /// @}\r |
| 959 | \r | |
| 960 | \r | |
| 961 | /**\r | |
| 962 | Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r | |
| 963 | 15.3.2.4, "IA32_MCi_MISC MSRs.".\r | |
| 964 | \r | |
| 0f16be6d HW |
965 | Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r |
| 966 | and its corresponding slice of L3.\r | |
| 967 | \r | |
| 968 | @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR\r | |
| 84ada87c MK |
969 | @param EAX Lower 32-bits of MSR value.\r |
| 970 | @param EDX Upper 32-bits of MSR value.\r | |
| 971 | \r | |
| 972 | <b>Example usage</b>\r | |
| 973 | @code\r | |
| 974 | UINT64 Msr;\r | |
| 975 | \r | |
| 0f16be6d HW |
976 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);\r |
| 977 | AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);\r | |
| 84ada87c | 978 | @endcode\r |
| 0f16be6d HW |
979 | @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.\r |
| 980 | MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.\r | |
| 981 | MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.\r | |
| 84ada87c MK |
982 | @{\r |
| 983 | **/\r | |
| 0f16be6d HW |
984 | #define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r |
| 985 | #define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r | |
| 986 | #define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r | |
| 84ada87c MK |
987 | /// @}\r |
| 988 | \r | |
| 989 | \r | |
| 990 | /**\r | |
| 0f16be6d HW |
991 | Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r |
| 992 | 15.3.2.4, "IA32_MCi_MISC MSRs.".\r | |
| 84ada87c | 993 | \r |
| 0f16be6d HW |
994 | Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r |
| 995 | and its corresponding slice of L3.\r | |
| 996 | \r | |
| 997 | @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC\r | |
| 84ada87c | 998 | @param EAX Lower 32-bits of MSR value.\r |
| 84ada87c | 999 | @param EDX Upper 32-bits of MSR value.\r |
| 84ada87c MK |
1000 | \r |
| 1001 | <b>Example usage</b>\r | |
| 1002 | @code\r | |
| 0f16be6d | 1003 | UINT64 Msr;\r |
| 84ada87c | 1004 | \r |
| 0f16be6d HW |
1005 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);\r |
| 1006 | AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);\r | |
| 84ada87c | 1007 | @endcode\r |
| 0f16be6d HW |
1008 | @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.\r |
| 1009 | MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.\r | |
| 1010 | MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.\r | |
| 1011 | @{\r | |
| 84ada87c | 1012 | **/\r |
| 0f16be6d HW |
1013 | #define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r |
| 1014 | #define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r | |
| 1015 | #define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r | |
| 1016 | /// @}\r | |
| 84ada87c MK |
1017 | \r |
| 1018 | \r | |
| 1019 | /**\r | |
| 1020 | Package. Package RAPL Perf Status (R/O).\r | |
| 1021 | \r | |
| 1022 | @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r | |
| 1023 | @param EAX Lower 32-bits of MSR value.\r | |
| 1024 | @param EDX Upper 32-bits of MSR value.\r | |
| 1025 | \r | |
| 1026 | <b>Example usage</b>\r | |
| 1027 | @code\r | |
| 1028 | UINT64 Msr;\r | |
| 1029 | \r | |
| 1030 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);\r | |
| 1031 | @endcode\r | |
| fed6c37b | 1032 | @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r |
| 84ada87c MK |
1033 | **/\r |
| 1034 | #define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r | |
| 1035 | \r | |
| 1036 | \r | |
| 1037 | /**\r | |
| 1038 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
| 1039 | Domain.".\r | |
| 1040 | \r | |
| 1041 | @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r | |
| 1042 | @param EAX Lower 32-bits of MSR value.\r | |
| 1043 | @param EDX Upper 32-bits of MSR value.\r | |
| 1044 | \r | |
| 1045 | <b>Example usage</b>\r | |
| 1046 | @code\r | |
| 1047 | UINT64 Msr;\r | |
| 1048 | \r | |
| 1049 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);\r | |
| 1050 | AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r | |
| 1051 | @endcode\r | |
| fed6c37b | 1052 | @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r |
| 84ada87c MK |
1053 | **/\r |
| 1054 | #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r | |
| 1055 | \r | |
| 1056 | \r | |
| 1057 | /**\r | |
| 1058 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 1059 | \r | |
| 1060 | @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 1061 | @param EAX Lower 32-bits of MSR value.\r | |
| 1062 | @param EDX Upper 32-bits of MSR value.\r | |
| 1063 | \r | |
| 1064 | <b>Example usage</b>\r | |
| 1065 | @code\r | |
| 1066 | UINT64 Msr;\r | |
| 1067 | \r | |
| 1068 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);\r | |
| 1069 | @endcode\r | |
| fed6c37b | 1070 | @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
| 84ada87c MK |
1071 | **/\r |
| 1072 | #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r | |
| 1073 | \r | |
| 1074 | \r | |
| 1075 | /**\r | |
| 1076 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 1077 | RAPL Domain.".\r | |
| 1078 | \r | |
| 1079 | @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r | |
| 1080 | @param EAX Lower 32-bits of MSR value.\r | |
| 1081 | @param EDX Upper 32-bits of MSR value.\r | |
| 1082 | \r | |
| 1083 | <b>Example usage</b>\r | |
| 1084 | @code\r | |
| 1085 | UINT64 Msr;\r | |
| 1086 | \r | |
| 1087 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);\r | |
| 1088 | @endcode\r | |
| fed6c37b | 1089 | @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
| 84ada87c MK |
1090 | **/\r |
| 1091 | #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r | |
| 1092 | \r | |
| 1093 | \r | |
| 1094 | /**\r | |
| 1095 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 1096 | \r | |
| 1097 | @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r | |
| 1098 | @param EAX Lower 32-bits of MSR value.\r | |
| 1099 | @param EDX Upper 32-bits of MSR value.\r | |
| 1100 | \r | |
| 1101 | <b>Example usage</b>\r | |
| 1102 | @code\r | |
| 1103 | UINT64 Msr;\r | |
| 1104 | \r | |
| 1105 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);\r | |
| 1106 | AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);\r | |
| 1107 | @endcode\r | |
| fed6c37b | 1108 | @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r |
| 84ada87c MK |
1109 | **/\r |
| 1110 | #define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r | |
| 1111 | \r | |
| 1112 | \r | |
| 1113 | /**\r | |
| 0f16be6d | 1114 | Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).".\r |
| 84ada87c MK |
1115 | \r |
| 1116 | @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)\r | |
| 1117 | @param EAX Lower 32-bits of MSR value.\r | |
| 1118 | Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r | |
| 1119 | @param EDX Upper 32-bits of MSR value.\r | |
| 1120 | Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r | |
| 1121 | \r | |
| 1122 | <b>Example usage</b>\r | |
| 1123 | @code\r | |
| 1124 | MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r | |
| 1125 | \r | |
| 1126 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);\r | |
| 1127 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r | |
| 1128 | @endcode\r | |
| fed6c37b | 1129 | @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
| 84ada87c MK |
1130 | **/\r |
| 1131 | #define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r | |
| 1132 | \r | |
| 1133 | /**\r | |
| 1134 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE\r | |
| 1135 | **/\r | |
| 1136 | typedef union {\r | |
| 1137 | ///\r | |
| 1138 | /// Individual bit fields\r | |
| 1139 | ///\r | |
| 1140 | struct {\r | |
| 1141 | ///\r | |
| 1142 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r | |
| 1143 | ///\r | |
| 1144 | UINT32 PEBS_EN_PMC0:1;\r | |
| 1145 | ///\r | |
| 1146 | /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r | |
| 1147 | ///\r | |
| 1148 | UINT32 PEBS_EN_PMC1:1;\r | |
| 1149 | ///\r | |
| 1150 | /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r | |
| 1151 | ///\r | |
| 1152 | UINT32 PEBS_EN_PMC2:1;\r | |
| 1153 | ///\r | |
| 1154 | /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r | |
| 1155 | ///\r | |
| 1156 | UINT32 PEBS_EN_PMC3:1;\r | |
| 1157 | UINT32 Reserved1:28;\r | |
| 1158 | ///\r | |
| 1159 | /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r | |
| 1160 | ///\r | |
| 1161 | UINT32 LL_EN_PMC0:1;\r | |
| 1162 | ///\r | |
| 1163 | /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r | |
| 1164 | ///\r | |
| 1165 | UINT32 LL_EN_PMC1:1;\r | |
| 1166 | ///\r | |
| 1167 | /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r | |
| 1168 | ///\r | |
| 1169 | UINT32 LL_EN_PMC2:1;\r | |
| 1170 | ///\r | |
| 1171 | /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r | |
| 1172 | ///\r | |
| 1173 | UINT32 LL_EN_PMC3:1;\r | |
| 1174 | UINT32 Reserved2:28;\r | |
| 1175 | } Bits;\r | |
| 1176 | ///\r | |
| 1177 | /// All bit fields as a 64-bit value\r | |
| 1178 | ///\r | |
| 1179 | UINT64 Uint64;\r | |
| 1180 | } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;\r | |
| 1181 | \r | |
| 1182 | \r | |
| 1183 | /**\r | |
| 1184 | Package. Uncore perfmon per-socket global control.\r | |
| 1185 | \r | |
| 1186 | @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)\r | |
| 1187 | @param EAX Lower 32-bits of MSR value.\r | |
| 1188 | @param EDX Upper 32-bits of MSR value.\r | |
| 1189 | \r | |
| 1190 | <b>Example usage</b>\r | |
| 1191 | @code\r | |
| 1192 | UINT64 Msr;\r | |
| 1193 | \r | |
| 1194 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);\r | |
| 1195 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);\r | |
| 1196 | @endcode\r | |
| fed6c37b | 1197 | @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r |
| 84ada87c MK |
1198 | **/\r |
| 1199 | #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r | |
| 1200 | \r | |
| 1201 | \r | |
| 1202 | /**\r | |
| 1203 | Package. Uncore perfmon per-socket global status.\r | |
| 1204 | \r | |
| 1205 | @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)\r | |
| 1206 | @param EAX Lower 32-bits of MSR value.\r | |
| 1207 | @param EDX Upper 32-bits of MSR value.\r | |
| 1208 | \r | |
| 1209 | <b>Example usage</b>\r | |
| 1210 | @code\r | |
| 1211 | UINT64 Msr;\r | |
| 1212 | \r | |
| 1213 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);\r | |
| 1214 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);\r | |
| 1215 | @endcode\r | |
| fed6c37b | 1216 | @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r |
| 84ada87c MK |
1217 | **/\r |
| 1218 | #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r | |
| 1219 | \r | |
| 1220 | \r | |
| 1221 | /**\r | |
| 1222 | Package. Uncore perfmon per-socket global configuration.\r | |
| 1223 | \r | |
| 1224 | @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)\r | |
| 1225 | @param EAX Lower 32-bits of MSR value.\r | |
| 1226 | @param EDX Upper 32-bits of MSR value.\r | |
| 1227 | \r | |
| 1228 | <b>Example usage</b>\r | |
| 1229 | @code\r | |
| 1230 | UINT64 Msr;\r | |
| 1231 | \r | |
| 1232 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);\r | |
| 1233 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);\r | |
| 1234 | @endcode\r | |
| fed6c37b | 1235 | @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r |
| 84ada87c MK |
1236 | **/\r |
| 1237 | #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r | |
| 1238 | \r | |
| 1239 | \r | |
| 1240 | /**\r | |
| 1241 | Package. Uncore U-box perfmon U-box wide status.\r | |
| 1242 | \r | |
| 1243 | @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)\r | |
| 1244 | @param EAX Lower 32-bits of MSR value.\r | |
| 1245 | @param EDX Upper 32-bits of MSR value.\r | |
| 1246 | \r | |
| 1247 | <b>Example usage</b>\r | |
| 1248 | @code\r | |
| 1249 | UINT64 Msr;\r | |
| 1250 | \r | |
| 1251 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);\r | |
| 1252 | AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);\r | |
| 1253 | @endcode\r | |
| fed6c37b | 1254 | @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r |
| 84ada87c MK |
1255 | **/\r |
| 1256 | #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r | |
| 1257 | \r | |
| 1258 | \r | |
| 1259 | /**\r | |
| 1260 | Package. Uncore PCU perfmon box wide status.\r | |
| 1261 | \r | |
| 1262 | @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)\r | |
| 1263 | @param EAX Lower 32-bits of MSR value.\r | |
| 1264 | @param EDX Upper 32-bits of MSR value.\r | |
| 1265 | \r | |
| 1266 | <b>Example usage</b>\r | |
| 1267 | @code\r | |
| 1268 | UINT64 Msr;\r | |
| 1269 | \r | |
| 1270 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);\r | |
| 1271 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);\r | |
| 1272 | @endcode\r | |
| fed6c37b | 1273 | @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r |
| 84ada87c MK |
1274 | **/\r |
| 1275 | #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r | |
| 1276 | \r | |
| 1277 | \r | |
| 1278 | /**\r | |
| 1279 | Package. Uncore C-box 0 perfmon box wide filter1.\r | |
| 1280 | \r | |
| 1281 | @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)\r | |
| 1282 | @param EAX Lower 32-bits of MSR value.\r | |
| 1283 | @param EDX Upper 32-bits of MSR value.\r | |
| 1284 | \r | |
| 1285 | <b>Example usage</b>\r | |
| 1286 | @code\r | |
| 1287 | UINT64 Msr;\r | |
| 1288 | \r | |
| 1289 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);\r | |
| 1290 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);\r | |
| 1291 | @endcode\r | |
| fed6c37b | 1292 | @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1293 | **/\r |
| 1294 | #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r | |
| 1295 | \r | |
| 1296 | \r | |
| 1297 | /**\r | |
| 1298 | Package. Uncore C-box 1 perfmon box wide filter1.\r | |
| 1299 | \r | |
| 1300 | @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)\r | |
| 1301 | @param EAX Lower 32-bits of MSR value.\r | |
| 1302 | @param EDX Upper 32-bits of MSR value.\r | |
| 1303 | \r | |
| 1304 | <b>Example usage</b>\r | |
| 1305 | @code\r | |
| 1306 | UINT64 Msr;\r | |
| 1307 | \r | |
| 1308 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);\r | |
| 1309 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);\r | |
| 1310 | @endcode\r | |
| fed6c37b | 1311 | @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1312 | **/\r |
| 1313 | #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r | |
| 1314 | \r | |
| 1315 | \r | |
| 1316 | /**\r | |
| 1317 | Package. Uncore C-box 2 perfmon box wide filter1.\r | |
| 1318 | \r | |
| 1319 | @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)\r | |
| 1320 | @param EAX Lower 32-bits of MSR value.\r | |
| 1321 | @param EDX Upper 32-bits of MSR value.\r | |
| 1322 | \r | |
| 1323 | <b>Example usage</b>\r | |
| 1324 | @code\r | |
| 1325 | UINT64 Msr;\r | |
| 1326 | \r | |
| 1327 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);\r | |
| 1328 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);\r | |
| 1329 | @endcode\r | |
| fed6c37b | 1330 | @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1331 | **/\r |
| 1332 | #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r | |
| 1333 | \r | |
| 1334 | \r | |
| 1335 | /**\r | |
| 1336 | Package. Uncore C-box 3 perfmon box wide filter1.\r | |
| 1337 | \r | |
| 1338 | @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)\r | |
| 1339 | @param EAX Lower 32-bits of MSR value.\r | |
| 1340 | @param EDX Upper 32-bits of MSR value.\r | |
| 1341 | \r | |
| 1342 | <b>Example usage</b>\r | |
| 1343 | @code\r | |
| 1344 | UINT64 Msr;\r | |
| 1345 | \r | |
| 1346 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);\r | |
| 1347 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);\r | |
| 1348 | @endcode\r | |
| fed6c37b | 1349 | @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1350 | **/\r |
| 1351 | #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r | |
| 1352 | \r | |
| 1353 | \r | |
| 1354 | /**\r | |
| 1355 | Package. Uncore C-box 4 perfmon box wide filter1.\r | |
| 1356 | \r | |
| 1357 | @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)\r | |
| 1358 | @param EAX Lower 32-bits of MSR value.\r | |
| 1359 | @param EDX Upper 32-bits of MSR value.\r | |
| 1360 | \r | |
| 1361 | <b>Example usage</b>\r | |
| 1362 | @code\r | |
| 1363 | UINT64 Msr;\r | |
| 1364 | \r | |
| 1365 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);\r | |
| 1366 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);\r | |
| 1367 | @endcode\r | |
| fed6c37b | 1368 | @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1369 | **/\r |
| 1370 | #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r | |
| 1371 | \r | |
| 1372 | \r | |
| 1373 | /**\r | |
| 1374 | Package. Uncore C-box 5 perfmon box wide filter1.\r | |
| 1375 | \r | |
| 1376 | @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)\r | |
| 1377 | @param EAX Lower 32-bits of MSR value.\r | |
| 1378 | @param EDX Upper 32-bits of MSR value.\r | |
| 1379 | \r | |
| 1380 | <b>Example usage</b>\r | |
| 1381 | @code\r | |
| 1382 | UINT64 Msr;\r | |
| 1383 | \r | |
| 1384 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);\r | |
| 1385 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);\r | |
| 1386 | @endcode\r | |
| fed6c37b | 1387 | @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1388 | **/\r |
| 1389 | #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r | |
| 1390 | \r | |
| 1391 | \r | |
| 1392 | /**\r | |
| 1393 | Package. Uncore C-box 6 perfmon box wide filter1.\r | |
| 1394 | \r | |
| 1395 | @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)\r | |
| 1396 | @param EAX Lower 32-bits of MSR value.\r | |
| 1397 | @param EDX Upper 32-bits of MSR value.\r | |
| 1398 | \r | |
| 1399 | <b>Example usage</b>\r | |
| 1400 | @code\r | |
| 1401 | UINT64 Msr;\r | |
| 1402 | \r | |
| 1403 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);\r | |
| 1404 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);\r | |
| 1405 | @endcode\r | |
| fed6c37b | 1406 | @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1407 | **/\r |
| 1408 | #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r | |
| 1409 | \r | |
| 1410 | \r | |
| 1411 | /**\r | |
| 1412 | Package. Uncore C-box 7 perfmon box wide filter1.\r | |
| 1413 | \r | |
| 1414 | @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)\r | |
| 1415 | @param EAX Lower 32-bits of MSR value.\r | |
| 1416 | @param EDX Upper 32-bits of MSR value.\r | |
| 1417 | \r | |
| 1418 | <b>Example usage</b>\r | |
| 1419 | @code\r | |
| 1420 | UINT64 Msr;\r | |
| 1421 | \r | |
| 1422 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);\r | |
| 1423 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);\r | |
| 1424 | @endcode\r | |
| fed6c37b | 1425 | @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1426 | **/\r |
| 1427 | #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r | |
| 1428 | \r | |
| 1429 | \r | |
| 1430 | /**\r | |
| 1431 | Package. Uncore C-box 8 perfmon local box wide control.\r | |
| 1432 | \r | |
| 1433 | @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)\r | |
| 1434 | @param EAX Lower 32-bits of MSR value.\r | |
| 1435 | @param EDX Upper 32-bits of MSR value.\r | |
| 1436 | \r | |
| 1437 | <b>Example usage</b>\r | |
| 1438 | @code\r | |
| 1439 | UINT64 Msr;\r | |
| 1440 | \r | |
| 1441 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);\r | |
| 1442 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);\r | |
| 1443 | @endcode\r | |
| fed6c37b | 1444 | @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
1445 | **/\r |
| 1446 | #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r | |
| 1447 | \r | |
| 1448 | \r | |
| 1449 | /**\r | |
| 1450 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r | |
| 1451 | \r | |
| 1452 | @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)\r | |
| 1453 | @param EAX Lower 32-bits of MSR value.\r | |
| 1454 | @param EDX Upper 32-bits of MSR value.\r | |
| 1455 | \r | |
| 1456 | <b>Example usage</b>\r | |
| 1457 | @code\r | |
| 1458 | UINT64 Msr;\r | |
| 1459 | \r | |
| 1460 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);\r | |
| 1461 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);\r | |
| 1462 | @endcode\r | |
| fed6c37b | 1463 | @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
1464 | **/\r |
| 1465 | #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r | |
| 1466 | \r | |
| 1467 | \r | |
| 1468 | /**\r | |
| 1469 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r | |
| 1470 | \r | |
| 1471 | @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)\r | |
| 1472 | @param EAX Lower 32-bits of MSR value.\r | |
| 1473 | @param EDX Upper 32-bits of MSR value.\r | |
| 1474 | \r | |
| 1475 | <b>Example usage</b>\r | |
| 1476 | @code\r | |
| 1477 | UINT64 Msr;\r | |
| 1478 | \r | |
| 1479 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);\r | |
| 1480 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);\r | |
| 1481 | @endcode\r | |
| fed6c37b | 1482 | @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
1483 | **/\r |
| 1484 | #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r | |
| 1485 | \r | |
| 1486 | \r | |
| 1487 | /**\r | |
| 1488 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r | |
| 1489 | \r | |
| 1490 | @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)\r | |
| 1491 | @param EAX Lower 32-bits of MSR value.\r | |
| 1492 | @param EDX Upper 32-bits of MSR value.\r | |
| 1493 | \r | |
| 1494 | <b>Example usage</b>\r | |
| 1495 | @code\r | |
| 1496 | UINT64 Msr;\r | |
| 1497 | \r | |
| 1498 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);\r | |
| 1499 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);\r | |
| 1500 | @endcode\r | |
| fed6c37b | 1501 | @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
1502 | **/\r |
| 1503 | #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r | |
| 1504 | \r | |
| 1505 | \r | |
| 1506 | /**\r | |
| 1507 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r | |
| 1508 | \r | |
| 1509 | @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)\r | |
| 1510 | @param EAX Lower 32-bits of MSR value.\r | |
| 1511 | @param EDX Upper 32-bits of MSR value.\r | |
| 1512 | \r | |
| 1513 | <b>Example usage</b>\r | |
| 1514 | @code\r | |
| 1515 | UINT64 Msr;\r | |
| 1516 | \r | |
| 1517 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);\r | |
| 1518 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);\r | |
| 1519 | @endcode\r | |
| fed6c37b | 1520 | @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
1521 | **/\r |
| 1522 | #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r | |
| 1523 | \r | |
| 1524 | \r | |
| 1525 | /**\r | |
| 1526 | Package. Uncore C-box 8 perfmon box wide filter.\r | |
| 1527 | \r | |
| 1528 | @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)\r | |
| 1529 | @param EAX Lower 32-bits of MSR value.\r | |
| 1530 | @param EDX Upper 32-bits of MSR value.\r | |
| 1531 | \r | |
| 1532 | <b>Example usage</b>\r | |
| 1533 | @code\r | |
| 1534 | UINT64 Msr;\r | |
| 1535 | \r | |
| 1536 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);\r | |
| 1537 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);\r | |
| 1538 | @endcode\r | |
| fed6c37b | 1539 | @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
1540 | **/\r |
| 1541 | #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r | |
| 1542 | \r | |
| 1543 | \r | |
| 1544 | /**\r | |
| 1545 | Package. Uncore C-box 8 perfmon counter 0.\r | |
| 1546 | \r | |
| 1547 | @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)\r | |
| 1548 | @param EAX Lower 32-bits of MSR value.\r | |
| 1549 | @param EDX Upper 32-bits of MSR value.\r | |
| 1550 | \r | |
| 1551 | <b>Example usage</b>\r | |
| 1552 | @code\r | |
| 1553 | UINT64 Msr;\r | |
| 1554 | \r | |
| 1555 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);\r | |
| 1556 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);\r | |
| 1557 | @endcode\r | |
| fed6c37b | 1558 | @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
1559 | **/\r |
| 1560 | #define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r | |
| 1561 | \r | |
| 1562 | \r | |
| 1563 | /**\r | |
| 1564 | Package. Uncore C-box 8 perfmon counter 1.\r | |
| 1565 | \r | |
| 1566 | @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)\r | |
| 1567 | @param EAX Lower 32-bits of MSR value.\r | |
| 1568 | @param EDX Upper 32-bits of MSR value.\r | |
| 1569 | \r | |
| 1570 | <b>Example usage</b>\r | |
| 1571 | @code\r | |
| 1572 | UINT64 Msr;\r | |
| 1573 | \r | |
| 1574 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);\r | |
| 1575 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);\r | |
| 1576 | @endcode\r | |
| fed6c37b | 1577 | @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
1578 | **/\r |
| 1579 | #define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r | |
| 1580 | \r | |
| 1581 | \r | |
| 1582 | /**\r | |
| 1583 | Package. Uncore C-box 8 perfmon counter 2.\r | |
| 1584 | \r | |
| 1585 | @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)\r | |
| 1586 | @param EAX Lower 32-bits of MSR value.\r | |
| 1587 | @param EDX Upper 32-bits of MSR value.\r | |
| 1588 | \r | |
| 1589 | <b>Example usage</b>\r | |
| 1590 | @code\r | |
| 1591 | UINT64 Msr;\r | |
| 1592 | \r | |
| 1593 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);\r | |
| 1594 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);\r | |
| 1595 | @endcode\r | |
| fed6c37b | 1596 | @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
1597 | **/\r |
| 1598 | #define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r | |
| 1599 | \r | |
| 1600 | \r | |
| 1601 | /**\r | |
| 1602 | Package. Uncore C-box 8 perfmon counter 3.\r | |
| 1603 | \r | |
| 1604 | @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)\r | |
| 1605 | @param EAX Lower 32-bits of MSR value.\r | |
| 1606 | @param EDX Upper 32-bits of MSR value.\r | |
| 1607 | \r | |
| 1608 | <b>Example usage</b>\r | |
| 1609 | @code\r | |
| 1610 | UINT64 Msr;\r | |
| 1611 | \r | |
| 1612 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);\r | |
| 1613 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);\r | |
| 1614 | @endcode\r | |
| fed6c37b | 1615 | @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
1616 | **/\r |
| 1617 | #define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r | |
| 1618 | \r | |
| 1619 | \r | |
| 1620 | /**\r | |
| 1621 | Package. Uncore C-box 8 perfmon box wide filter1.\r | |
| 1622 | \r | |
| 1623 | @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)\r | |
| 1624 | @param EAX Lower 32-bits of MSR value.\r | |
| 1625 | @param EDX Upper 32-bits of MSR value.\r | |
| 1626 | \r | |
| 1627 | <b>Example usage</b>\r | |
| 1628 | @code\r | |
| 1629 | UINT64 Msr;\r | |
| 1630 | \r | |
| 1631 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);\r | |
| 1632 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);\r | |
| 1633 | @endcode\r | |
| fed6c37b | 1634 | @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1635 | **/\r |
| 1636 | #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r | |
| 1637 | \r | |
| 1638 | \r | |
| 1639 | /**\r | |
| 1640 | Package. Uncore C-box 9 perfmon local box wide control.\r | |
| 1641 | \r | |
| 1642 | @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)\r | |
| 1643 | @param EAX Lower 32-bits of MSR value.\r | |
| 1644 | @param EDX Upper 32-bits of MSR value.\r | |
| 1645 | \r | |
| 1646 | <b>Example usage</b>\r | |
| 1647 | @code\r | |
| 1648 | UINT64 Msr;\r | |
| 1649 | \r | |
| 1650 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);\r | |
| 1651 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);\r | |
| 1652 | @endcode\r | |
| fed6c37b | 1653 | @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
1654 | **/\r |
| 1655 | #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r | |
| 1656 | \r | |
| 1657 | \r | |
| 1658 | /**\r | |
| 1659 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r | |
| 1660 | \r | |
| 1661 | @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)\r | |
| 1662 | @param EAX Lower 32-bits of MSR value.\r | |
| 1663 | @param EDX Upper 32-bits of MSR value.\r | |
| 1664 | \r | |
| 1665 | <b>Example usage</b>\r | |
| 1666 | @code\r | |
| 1667 | UINT64 Msr;\r | |
| 1668 | \r | |
| 1669 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);\r | |
| 1670 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);\r | |
| 1671 | @endcode\r | |
| fed6c37b | 1672 | @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
1673 | **/\r |
| 1674 | #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r | |
| 1675 | \r | |
| 1676 | \r | |
| 1677 | /**\r | |
| 1678 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r | |
| 1679 | \r | |
| 1680 | @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)\r | |
| 1681 | @param EAX Lower 32-bits of MSR value.\r | |
| 1682 | @param EDX Upper 32-bits of MSR value.\r | |
| 1683 | \r | |
| 1684 | <b>Example usage</b>\r | |
| 1685 | @code\r | |
| 1686 | UINT64 Msr;\r | |
| 1687 | \r | |
| 1688 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);\r | |
| 1689 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);\r | |
| 1690 | @endcode\r | |
| fed6c37b | 1691 | @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
1692 | **/\r |
| 1693 | #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r | |
| 1694 | \r | |
| 1695 | \r | |
| 1696 | /**\r | |
| 1697 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r | |
| 1698 | \r | |
| 1699 | @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)\r | |
| 1700 | @param EAX Lower 32-bits of MSR value.\r | |
| 1701 | @param EDX Upper 32-bits of MSR value.\r | |
| 1702 | \r | |
| 1703 | <b>Example usage</b>\r | |
| 1704 | @code\r | |
| 1705 | UINT64 Msr;\r | |
| 1706 | \r | |
| 1707 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);\r | |
| 1708 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);\r | |
| 1709 | @endcode\r | |
| fed6c37b | 1710 | @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
1711 | **/\r |
| 1712 | #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r | |
| 1713 | \r | |
| 1714 | \r | |
| 1715 | /**\r | |
| 1716 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r | |
| 1717 | \r | |
| 1718 | @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)\r | |
| 1719 | @param EAX Lower 32-bits of MSR value.\r | |
| 1720 | @param EDX Upper 32-bits of MSR value.\r | |
| 1721 | \r | |
| 1722 | <b>Example usage</b>\r | |
| 1723 | @code\r | |
| 1724 | UINT64 Msr;\r | |
| 1725 | \r | |
| 1726 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);\r | |
| 1727 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);\r | |
| 1728 | @endcode\r | |
| fed6c37b | 1729 | @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
1730 | **/\r |
| 1731 | #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r | |
| 1732 | \r | |
| 1733 | \r | |
| 1734 | /**\r | |
| 1735 | Package. Uncore C-box 9 perfmon box wide filter.\r | |
| 1736 | \r | |
| 1737 | @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)\r | |
| 1738 | @param EAX Lower 32-bits of MSR value.\r | |
| 1739 | @param EDX Upper 32-bits of MSR value.\r | |
| 1740 | \r | |
| 1741 | <b>Example usage</b>\r | |
| 1742 | @code\r | |
| 1743 | UINT64 Msr;\r | |
| 1744 | \r | |
| 1745 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);\r | |
| 1746 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);\r | |
| 1747 | @endcode\r | |
| fed6c37b | 1748 | @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
1749 | **/\r |
| 1750 | #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r | |
| 1751 | \r | |
| 1752 | \r | |
| 1753 | /**\r | |
| 1754 | Package. Uncore C-box 9 perfmon counter 0.\r | |
| 1755 | \r | |
| 1756 | @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)\r | |
| 1757 | @param EAX Lower 32-bits of MSR value.\r | |
| 1758 | @param EDX Upper 32-bits of MSR value.\r | |
| 1759 | \r | |
| 1760 | <b>Example usage</b>\r | |
| 1761 | @code\r | |
| 1762 | UINT64 Msr;\r | |
| 1763 | \r | |
| 1764 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);\r | |
| 1765 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);\r | |
| 1766 | @endcode\r | |
| fed6c37b | 1767 | @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
1768 | **/\r |
| 1769 | #define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r | |
| 1770 | \r | |
| 1771 | \r | |
| 1772 | /**\r | |
| 1773 | Package. Uncore C-box 9 perfmon counter 1.\r | |
| 1774 | \r | |
| 1775 | @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)\r | |
| 1776 | @param EAX Lower 32-bits of MSR value.\r | |
| 1777 | @param EDX Upper 32-bits of MSR value.\r | |
| 1778 | \r | |
| 1779 | <b>Example usage</b>\r | |
| 1780 | @code\r | |
| 1781 | UINT64 Msr;\r | |
| 1782 | \r | |
| 1783 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);\r | |
| 1784 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);\r | |
| 1785 | @endcode\r | |
| fed6c37b | 1786 | @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
1787 | **/\r |
| 1788 | #define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r | |
| 1789 | \r | |
| 1790 | \r | |
| 1791 | /**\r | |
| 1792 | Package. Uncore C-box 9 perfmon counter 2.\r | |
| 1793 | \r | |
| 1794 | @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)\r | |
| 1795 | @param EAX Lower 32-bits of MSR value.\r | |
| 1796 | @param EDX Upper 32-bits of MSR value.\r | |
| 1797 | \r | |
| 1798 | <b>Example usage</b>\r | |
| 1799 | @code\r | |
| 1800 | UINT64 Msr;\r | |
| 1801 | \r | |
| 1802 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);\r | |
| 1803 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);\r | |
| 1804 | @endcode\r | |
| fed6c37b | 1805 | @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
1806 | **/\r |
| 1807 | #define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r | |
| 1808 | \r | |
| 1809 | \r | |
| 1810 | /**\r | |
| 1811 | Package. Uncore C-box 9 perfmon counter 3.\r | |
| 1812 | \r | |
| 1813 | @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)\r | |
| 1814 | @param EAX Lower 32-bits of MSR value.\r | |
| 1815 | @param EDX Upper 32-bits of MSR value.\r | |
| 1816 | \r | |
| 1817 | <b>Example usage</b>\r | |
| 1818 | @code\r | |
| 1819 | UINT64 Msr;\r | |
| 1820 | \r | |
| 1821 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);\r | |
| 1822 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);\r | |
| 1823 | @endcode\r | |
| fed6c37b | 1824 | @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
1825 | **/\r |
| 1826 | #define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r | |
| 1827 | \r | |
| 1828 | \r | |
| 1829 | /**\r | |
| 1830 | Package. Uncore C-box 9 perfmon box wide filter1.\r | |
| 1831 | \r | |
| 1832 | @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)\r | |
| 1833 | @param EAX Lower 32-bits of MSR value.\r | |
| 1834 | @param EDX Upper 32-bits of MSR value.\r | |
| 1835 | \r | |
| 1836 | <b>Example usage</b>\r | |
| 1837 | @code\r | |
| 1838 | UINT64 Msr;\r | |
| 1839 | \r | |
| 1840 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);\r | |
| 1841 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);\r | |
| 1842 | @endcode\r | |
| fed6c37b | 1843 | @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1844 | **/\r |
| 1845 | #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r | |
| 1846 | \r | |
| 1847 | \r | |
| 1848 | /**\r | |
| 1849 | Package. Uncore C-box 10 perfmon local box wide control.\r | |
| 1850 | \r | |
| 1851 | @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)\r | |
| 1852 | @param EAX Lower 32-bits of MSR value.\r | |
| 1853 | @param EDX Upper 32-bits of MSR value.\r | |
| 1854 | \r | |
| 1855 | <b>Example usage</b>\r | |
| 1856 | @code\r | |
| 1857 | UINT64 Msr;\r | |
| 1858 | \r | |
| 1859 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);\r | |
| 1860 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);\r | |
| 1861 | @endcode\r | |
| fed6c37b | 1862 | @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
1863 | **/\r |
| 1864 | #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r | |
| 1865 | \r | |
| 1866 | \r | |
| 1867 | /**\r | |
| 1868 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r | |
| 1869 | \r | |
| 1870 | @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)\r | |
| 1871 | @param EAX Lower 32-bits of MSR value.\r | |
| 1872 | @param EDX Upper 32-bits of MSR value.\r | |
| 1873 | \r | |
| 1874 | <b>Example usage</b>\r | |
| 1875 | @code\r | |
| 1876 | UINT64 Msr;\r | |
| 1877 | \r | |
| 1878 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);\r | |
| 1879 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);\r | |
| 1880 | @endcode\r | |
| fed6c37b | 1881 | @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
1882 | **/\r |
| 1883 | #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r | |
| 1884 | \r | |
| 1885 | \r | |
| 1886 | /**\r | |
| 1887 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r | |
| 1888 | \r | |
| 1889 | @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)\r | |
| 1890 | @param EAX Lower 32-bits of MSR value.\r | |
| 1891 | @param EDX Upper 32-bits of MSR value.\r | |
| 1892 | \r | |
| 1893 | <b>Example usage</b>\r | |
| 1894 | @code\r | |
| 1895 | UINT64 Msr;\r | |
| 1896 | \r | |
| 1897 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);\r | |
| 1898 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);\r | |
| 1899 | @endcode\r | |
| fed6c37b | 1900 | @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
1901 | **/\r |
| 1902 | #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r | |
| 1903 | \r | |
| 1904 | \r | |
| 1905 | /**\r | |
| 1906 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r | |
| 1907 | \r | |
| 1908 | @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)\r | |
| 1909 | @param EAX Lower 32-bits of MSR value.\r | |
| 1910 | @param EDX Upper 32-bits of MSR value.\r | |
| 1911 | \r | |
| 1912 | <b>Example usage</b>\r | |
| 1913 | @code\r | |
| 1914 | UINT64 Msr;\r | |
| 1915 | \r | |
| 1916 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);\r | |
| 1917 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);\r | |
| 1918 | @endcode\r | |
| fed6c37b | 1919 | @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
1920 | **/\r |
| 1921 | #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r | |
| 1922 | \r | |
| 1923 | \r | |
| 1924 | /**\r | |
| 1925 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r | |
| 1926 | \r | |
| 1927 | @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)\r | |
| 1928 | @param EAX Lower 32-bits of MSR value.\r | |
| 1929 | @param EDX Upper 32-bits of MSR value.\r | |
| 1930 | \r | |
| 1931 | <b>Example usage</b>\r | |
| 1932 | @code\r | |
| 1933 | UINT64 Msr;\r | |
| 1934 | \r | |
| 1935 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);\r | |
| 1936 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);\r | |
| 1937 | @endcode\r | |
| fed6c37b | 1938 | @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
1939 | **/\r |
| 1940 | #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r | |
| 1941 | \r | |
| 1942 | \r | |
| 1943 | /**\r | |
| 1944 | Package. Uncore C-box 10 perfmon box wide filter.\r | |
| 1945 | \r | |
| 1946 | @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)\r | |
| 1947 | @param EAX Lower 32-bits of MSR value.\r | |
| 1948 | @param EDX Upper 32-bits of MSR value.\r | |
| 1949 | \r | |
| 1950 | <b>Example usage</b>\r | |
| 1951 | @code\r | |
| 1952 | UINT64 Msr;\r | |
| 1953 | \r | |
| 1954 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);\r | |
| 1955 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);\r | |
| 1956 | @endcode\r | |
| fed6c37b | 1957 | @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
1958 | **/\r |
| 1959 | #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r | |
| 1960 | \r | |
| 1961 | \r | |
| 1962 | /**\r | |
| 1963 | Package. Uncore C-box 10 perfmon counter 0.\r | |
| 1964 | \r | |
| 1965 | @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)\r | |
| 1966 | @param EAX Lower 32-bits of MSR value.\r | |
| 1967 | @param EDX Upper 32-bits of MSR value.\r | |
| 1968 | \r | |
| 1969 | <b>Example usage</b>\r | |
| 1970 | @code\r | |
| 1971 | UINT64 Msr;\r | |
| 1972 | \r | |
| 1973 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);\r | |
| 1974 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);\r | |
| 1975 | @endcode\r | |
| fed6c37b | 1976 | @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
1977 | **/\r |
| 1978 | #define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r | |
| 1979 | \r | |
| 1980 | \r | |
| 1981 | /**\r | |
| 1982 | Package. Uncore C-box 10 perfmon counter 1.\r | |
| 1983 | \r | |
| 1984 | @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)\r | |
| 1985 | @param EAX Lower 32-bits of MSR value.\r | |
| 1986 | @param EDX Upper 32-bits of MSR value.\r | |
| 1987 | \r | |
| 1988 | <b>Example usage</b>\r | |
| 1989 | @code\r | |
| 1990 | UINT64 Msr;\r | |
| 1991 | \r | |
| 1992 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);\r | |
| 1993 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);\r | |
| 1994 | @endcode\r | |
| fed6c37b | 1995 | @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
1996 | **/\r |
| 1997 | #define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r | |
| 1998 | \r | |
| 1999 | \r | |
| 2000 | /**\r | |
| 2001 | Package. Uncore C-box 10 perfmon counter 2.\r | |
| 2002 | \r | |
| 2003 | @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)\r | |
| 2004 | @param EAX Lower 32-bits of MSR value.\r | |
| 2005 | @param EDX Upper 32-bits of MSR value.\r | |
| 2006 | \r | |
| 2007 | <b>Example usage</b>\r | |
| 2008 | @code\r | |
| 2009 | UINT64 Msr;\r | |
| 2010 | \r | |
| 2011 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);\r | |
| 2012 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);\r | |
| 2013 | @endcode\r | |
| fed6c37b | 2014 | @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2015 | **/\r |
| 2016 | #define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r | |
| 2017 | \r | |
| 2018 | \r | |
| 2019 | /**\r | |
| 2020 | Package. Uncore C-box 10 perfmon counter 3.\r | |
| 2021 | \r | |
| 2022 | @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)\r | |
| 2023 | @param EAX Lower 32-bits of MSR value.\r | |
| 2024 | @param EDX Upper 32-bits of MSR value.\r | |
| 2025 | \r | |
| 2026 | <b>Example usage</b>\r | |
| 2027 | @code\r | |
| 2028 | UINT64 Msr;\r | |
| 2029 | \r | |
| 2030 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);\r | |
| 2031 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);\r | |
| 2032 | @endcode\r | |
| fed6c37b | 2033 | @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2034 | **/\r |
| 2035 | #define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r | |
| 2036 | \r | |
| 2037 | \r | |
| 2038 | /**\r | |
| 2039 | Package. Uncore C-box 10 perfmon box wide filter1.\r | |
| 2040 | \r | |
| 2041 | @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)\r | |
| 2042 | @param EAX Lower 32-bits of MSR value.\r | |
| 2043 | @param EDX Upper 32-bits of MSR value.\r | |
| 2044 | \r | |
| 2045 | <b>Example usage</b>\r | |
| 2046 | @code\r | |
| 2047 | UINT64 Msr;\r | |
| 2048 | \r | |
| 2049 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);\r | |
| 2050 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);\r | |
| 2051 | @endcode\r | |
| fed6c37b | 2052 | @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2053 | **/\r |
| 2054 | #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r | |
| 2055 | \r | |
| 2056 | \r | |
| 2057 | /**\r | |
| 2058 | Package. Uncore C-box 11 perfmon local box wide control.\r | |
| 2059 | \r | |
| 2060 | @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)\r | |
| 2061 | @param EAX Lower 32-bits of MSR value.\r | |
| 2062 | @param EDX Upper 32-bits of MSR value.\r | |
| 2063 | \r | |
| 2064 | <b>Example usage</b>\r | |
| 2065 | @code\r | |
| 2066 | UINT64 Msr;\r | |
| 2067 | \r | |
| 2068 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);\r | |
| 2069 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);\r | |
| 2070 | @endcode\r | |
| fed6c37b | 2071 | @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
2072 | **/\r |
| 2073 | #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r | |
| 2074 | \r | |
| 2075 | \r | |
| 2076 | /**\r | |
| 2077 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r | |
| 2078 | \r | |
| 2079 | @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)\r | |
| 2080 | @param EAX Lower 32-bits of MSR value.\r | |
| 2081 | @param EDX Upper 32-bits of MSR value.\r | |
| 2082 | \r | |
| 2083 | <b>Example usage</b>\r | |
| 2084 | @code\r | |
| 2085 | UINT64 Msr;\r | |
| 2086 | \r | |
| 2087 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);\r | |
| 2088 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);\r | |
| 2089 | @endcode\r | |
| fed6c37b | 2090 | @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
2091 | **/\r |
| 2092 | #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r | |
| 2093 | \r | |
| 2094 | \r | |
| 2095 | /**\r | |
| 2096 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r | |
| 2097 | \r | |
| 2098 | @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)\r | |
| 2099 | @param EAX Lower 32-bits of MSR value.\r | |
| 2100 | @param EDX Upper 32-bits of MSR value.\r | |
| 2101 | \r | |
| 2102 | <b>Example usage</b>\r | |
| 2103 | @code\r | |
| 2104 | UINT64 Msr;\r | |
| 2105 | \r | |
| 2106 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);\r | |
| 2107 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);\r | |
| 2108 | @endcode\r | |
| fed6c37b | 2109 | @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
2110 | **/\r |
| 2111 | #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r | |
| 2112 | \r | |
| 2113 | \r | |
| 2114 | /**\r | |
| 2115 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r | |
| 2116 | \r | |
| 2117 | @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)\r | |
| 2118 | @param EAX Lower 32-bits of MSR value.\r | |
| 2119 | @param EDX Upper 32-bits of MSR value.\r | |
| 2120 | \r | |
| 2121 | <b>Example usage</b>\r | |
| 2122 | @code\r | |
| 2123 | UINT64 Msr;\r | |
| 2124 | \r | |
| 2125 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);\r | |
| 2126 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);\r | |
| 2127 | @endcode\r | |
| fed6c37b | 2128 | @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
2129 | **/\r |
| 2130 | #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r | |
| 2131 | \r | |
| 2132 | \r | |
| 2133 | /**\r | |
| 2134 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r | |
| 2135 | \r | |
| 2136 | @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)\r | |
| 2137 | @param EAX Lower 32-bits of MSR value.\r | |
| 2138 | @param EDX Upper 32-bits of MSR value.\r | |
| 2139 | \r | |
| 2140 | <b>Example usage</b>\r | |
| 2141 | @code\r | |
| 2142 | UINT64 Msr;\r | |
| 2143 | \r | |
| 2144 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);\r | |
| 2145 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);\r | |
| 2146 | @endcode\r | |
| fed6c37b | 2147 | @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
2148 | **/\r |
| 2149 | #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r | |
| 2150 | \r | |
| 2151 | \r | |
| 2152 | /**\r | |
| 2153 | Package. Uncore C-box 11 perfmon box wide filter.\r | |
| 2154 | \r | |
| 2155 | @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)\r | |
| 2156 | @param EAX Lower 32-bits of MSR value.\r | |
| 2157 | @param EDX Upper 32-bits of MSR value.\r | |
| 2158 | \r | |
| 2159 | <b>Example usage</b>\r | |
| 2160 | @code\r | |
| 2161 | UINT64 Msr;\r | |
| 2162 | \r | |
| 2163 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);\r | |
| 2164 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);\r | |
| 2165 | @endcode\r | |
| fed6c37b | 2166 | @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
2167 | **/\r |
| 2168 | #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r | |
| 2169 | \r | |
| 2170 | \r | |
| 2171 | /**\r | |
| 2172 | Package. Uncore C-box 11 perfmon counter 0.\r | |
| 2173 | \r | |
| 2174 | @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)\r | |
| 2175 | @param EAX Lower 32-bits of MSR value.\r | |
| 2176 | @param EDX Upper 32-bits of MSR value.\r | |
| 2177 | \r | |
| 2178 | <b>Example usage</b>\r | |
| 2179 | @code\r | |
| 2180 | UINT64 Msr;\r | |
| 2181 | \r | |
| 2182 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);\r | |
| 2183 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);\r | |
| 2184 | @endcode\r | |
| fed6c37b | 2185 | @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
2186 | **/\r |
| 2187 | #define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r | |
| 2188 | \r | |
| 2189 | \r | |
| 2190 | /**\r | |
| 2191 | Package. Uncore C-box 11 perfmon counter 1.\r | |
| 2192 | \r | |
| 2193 | @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)\r | |
| 2194 | @param EAX Lower 32-bits of MSR value.\r | |
| 2195 | @param EDX Upper 32-bits of MSR value.\r | |
| 2196 | \r | |
| 2197 | <b>Example usage</b>\r | |
| 2198 | @code\r | |
| 2199 | UINT64 Msr;\r | |
| 2200 | \r | |
| 2201 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);\r | |
| 2202 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);\r | |
| 2203 | @endcode\r | |
| fed6c37b | 2204 | @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
2205 | **/\r |
| 2206 | #define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r | |
| 2207 | \r | |
| 2208 | \r | |
| 2209 | /**\r | |
| 2210 | Package. Uncore C-box 11 perfmon counter 2.\r | |
| 2211 | \r | |
| 2212 | @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)\r | |
| 2213 | @param EAX Lower 32-bits of MSR value.\r | |
| 2214 | @param EDX Upper 32-bits of MSR value.\r | |
| 2215 | \r | |
| 2216 | <b>Example usage</b>\r | |
| 2217 | @code\r | |
| 2218 | UINT64 Msr;\r | |
| 2219 | \r | |
| 2220 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);\r | |
| 2221 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);\r | |
| 2222 | @endcode\r | |
| fed6c37b | 2223 | @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2224 | **/\r |
| 2225 | #define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r | |
| 2226 | \r | |
| 2227 | \r | |
| 2228 | /**\r | |
| 2229 | Package. Uncore C-box 11 perfmon counter 3.\r | |
| 2230 | \r | |
| 2231 | @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)\r | |
| 2232 | @param EAX Lower 32-bits of MSR value.\r | |
| 2233 | @param EDX Upper 32-bits of MSR value.\r | |
| 2234 | \r | |
| 2235 | <b>Example usage</b>\r | |
| 2236 | @code\r | |
| 2237 | UINT64 Msr;\r | |
| 2238 | \r | |
| 2239 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);\r | |
| 2240 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);\r | |
| 2241 | @endcode\r | |
| fed6c37b | 2242 | @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2243 | **/\r |
| 2244 | #define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r | |
| 2245 | \r | |
| 2246 | \r | |
| 2247 | /**\r | |
| 2248 | Package. Uncore C-box 11 perfmon box wide filter1.\r | |
| 2249 | \r | |
| 2250 | @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)\r | |
| 2251 | @param EAX Lower 32-bits of MSR value.\r | |
| 2252 | @param EDX Upper 32-bits of MSR value.\r | |
| 2253 | \r | |
| 2254 | <b>Example usage</b>\r | |
| 2255 | @code\r | |
| 2256 | UINT64 Msr;\r | |
| 2257 | \r | |
| 2258 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);\r | |
| 2259 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);\r | |
| 2260 | @endcode\r | |
| fed6c37b | 2261 | @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2262 | **/\r |
| 2263 | #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r | |
| 2264 | \r | |
| 2265 | \r | |
| 2266 | /**\r | |
| 2267 | Package. Uncore C-box 12 perfmon local box wide control.\r | |
| 2268 | \r | |
| 2269 | @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)\r | |
| 2270 | @param EAX Lower 32-bits of MSR value.\r | |
| 2271 | @param EDX Upper 32-bits of MSR value.\r | |
| 2272 | \r | |
| 2273 | <b>Example usage</b>\r | |
| 2274 | @code\r | |
| 2275 | UINT64 Msr;\r | |
| 2276 | \r | |
| 2277 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);\r | |
| 2278 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);\r | |
| 2279 | @endcode\r | |
| fed6c37b | 2280 | @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
2281 | **/\r |
| 2282 | #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r | |
| 2283 | \r | |
| 2284 | \r | |
| 2285 | /**\r | |
| 2286 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r | |
| 2287 | \r | |
| 2288 | @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)\r | |
| 2289 | @param EAX Lower 32-bits of MSR value.\r | |
| 2290 | @param EDX Upper 32-bits of MSR value.\r | |
| 2291 | \r | |
| 2292 | <b>Example usage</b>\r | |
| 2293 | @code\r | |
| 2294 | UINT64 Msr;\r | |
| 2295 | \r | |
| 2296 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);\r | |
| 2297 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);\r | |
| 2298 | @endcode\r | |
| fed6c37b | 2299 | @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
2300 | **/\r |
| 2301 | #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r | |
| 2302 | \r | |
| 2303 | \r | |
| 2304 | /**\r | |
| 2305 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r | |
| 2306 | \r | |
| 2307 | @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)\r | |
| 2308 | @param EAX Lower 32-bits of MSR value.\r | |
| 2309 | @param EDX Upper 32-bits of MSR value.\r | |
| 2310 | \r | |
| 2311 | <b>Example usage</b>\r | |
| 2312 | @code\r | |
| 2313 | UINT64 Msr;\r | |
| 2314 | \r | |
| 2315 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);\r | |
| 2316 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);\r | |
| 2317 | @endcode\r | |
| fed6c37b | 2318 | @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
2319 | **/\r |
| 2320 | #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r | |
| 2321 | \r | |
| 2322 | \r | |
| 2323 | /**\r | |
| 2324 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r | |
| 2325 | \r | |
| 2326 | @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)\r | |
| 2327 | @param EAX Lower 32-bits of MSR value.\r | |
| 2328 | @param EDX Upper 32-bits of MSR value.\r | |
| 2329 | \r | |
| 2330 | <b>Example usage</b>\r | |
| 2331 | @code\r | |
| 2332 | UINT64 Msr;\r | |
| 2333 | \r | |
| 2334 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);\r | |
| 2335 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);\r | |
| 2336 | @endcode\r | |
| fed6c37b | 2337 | @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
2338 | **/\r |
| 2339 | #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r | |
| 2340 | \r | |
| 2341 | \r | |
| 2342 | /**\r | |
| 2343 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r | |
| 2344 | \r | |
| 2345 | @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)\r | |
| 2346 | @param EAX Lower 32-bits of MSR value.\r | |
| 2347 | @param EDX Upper 32-bits of MSR value.\r | |
| 2348 | \r | |
| 2349 | <b>Example usage</b>\r | |
| 2350 | @code\r | |
| 2351 | UINT64 Msr;\r | |
| 2352 | \r | |
| 2353 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);\r | |
| 2354 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);\r | |
| 2355 | @endcode\r | |
| fed6c37b | 2356 | @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
2357 | **/\r |
| 2358 | #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r | |
| 2359 | \r | |
| 2360 | \r | |
| 2361 | /**\r | |
| 2362 | Package. Uncore C-box 12 perfmon box wide filter.\r | |
| 2363 | \r | |
| 2364 | @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)\r | |
| 2365 | @param EAX Lower 32-bits of MSR value.\r | |
| 2366 | @param EDX Upper 32-bits of MSR value.\r | |
| 2367 | \r | |
| 2368 | <b>Example usage</b>\r | |
| 2369 | @code\r | |
| 2370 | UINT64 Msr;\r | |
| 2371 | \r | |
| 2372 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);\r | |
| 2373 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);\r | |
| 2374 | @endcode\r | |
| fed6c37b | 2375 | @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
2376 | **/\r |
| 2377 | #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r | |
| 2378 | \r | |
| 2379 | \r | |
| 2380 | /**\r | |
| 2381 | Package. Uncore C-box 12 perfmon counter 0.\r | |
| 2382 | \r | |
| 2383 | @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)\r | |
| 2384 | @param EAX Lower 32-bits of MSR value.\r | |
| 2385 | @param EDX Upper 32-bits of MSR value.\r | |
| 2386 | \r | |
| 2387 | <b>Example usage</b>\r | |
| 2388 | @code\r | |
| 2389 | UINT64 Msr;\r | |
| 2390 | \r | |
| 2391 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);\r | |
| 2392 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);\r | |
| 2393 | @endcode\r | |
| fed6c37b | 2394 | @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
2395 | **/\r |
| 2396 | #define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r | |
| 2397 | \r | |
| 2398 | \r | |
| 2399 | /**\r | |
| 2400 | Package. Uncore C-box 12 perfmon counter 1.\r | |
| 2401 | \r | |
| 2402 | @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)\r | |
| 2403 | @param EAX Lower 32-bits of MSR value.\r | |
| 2404 | @param EDX Upper 32-bits of MSR value.\r | |
| 2405 | \r | |
| 2406 | <b>Example usage</b>\r | |
| 2407 | @code\r | |
| 2408 | UINT64 Msr;\r | |
| 2409 | \r | |
| 2410 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);\r | |
| 2411 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);\r | |
| 2412 | @endcode\r | |
| fed6c37b | 2413 | @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
2414 | **/\r |
| 2415 | #define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r | |
| 2416 | \r | |
| 2417 | \r | |
| 2418 | /**\r | |
| 2419 | Package. Uncore C-box 12 perfmon counter 2.\r | |
| 2420 | \r | |
| 2421 | @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)\r | |
| 2422 | @param EAX Lower 32-bits of MSR value.\r | |
| 2423 | @param EDX Upper 32-bits of MSR value.\r | |
| 2424 | \r | |
| 2425 | <b>Example usage</b>\r | |
| 2426 | @code\r | |
| 2427 | UINT64 Msr;\r | |
| 2428 | \r | |
| 2429 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);\r | |
| 2430 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);\r | |
| 2431 | @endcode\r | |
| fed6c37b | 2432 | @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2433 | **/\r |
| 2434 | #define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r | |
| 2435 | \r | |
| 2436 | \r | |
| 2437 | /**\r | |
| 2438 | Package. Uncore C-box 12 perfmon counter 3.\r | |
| 2439 | \r | |
| 2440 | @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)\r | |
| 2441 | @param EAX Lower 32-bits of MSR value.\r | |
| 2442 | @param EDX Upper 32-bits of MSR value.\r | |
| 2443 | \r | |
| 2444 | <b>Example usage</b>\r | |
| 2445 | @code\r | |
| 2446 | UINT64 Msr;\r | |
| 2447 | \r | |
| 2448 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);\r | |
| 2449 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);\r | |
| 2450 | @endcode\r | |
| fed6c37b | 2451 | @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2452 | **/\r |
| 2453 | #define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r | |
| 2454 | \r | |
| 2455 | \r | |
| 2456 | /**\r | |
| 2457 | Package. Uncore C-box 12 perfmon box wide filter1.\r | |
| 2458 | \r | |
| 2459 | @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)\r | |
| 2460 | @param EAX Lower 32-bits of MSR value.\r | |
| 2461 | @param EDX Upper 32-bits of MSR value.\r | |
| 2462 | \r | |
| 2463 | <b>Example usage</b>\r | |
| 2464 | @code\r | |
| 2465 | UINT64 Msr;\r | |
| 2466 | \r | |
| 2467 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);\r | |
| 2468 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);\r | |
| 2469 | @endcode\r | |
| fed6c37b | 2470 | @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2471 | **/\r |
| 2472 | #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r | |
| 2473 | \r | |
| 2474 | \r | |
| 2475 | /**\r | |
| 2476 | Package. Uncore C-box 13 perfmon local box wide control.\r | |
| 2477 | \r | |
| 2478 | @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)\r | |
| 2479 | @param EAX Lower 32-bits of MSR value.\r | |
| 2480 | @param EDX Upper 32-bits of MSR value.\r | |
| 2481 | \r | |
| 2482 | <b>Example usage</b>\r | |
| 2483 | @code\r | |
| 2484 | UINT64 Msr;\r | |
| 2485 | \r | |
| 2486 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);\r | |
| 2487 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);\r | |
| 2488 | @endcode\r | |
| fed6c37b | 2489 | @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
2490 | **/\r |
| 2491 | #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r | |
| 2492 | \r | |
| 2493 | \r | |
| 2494 | /**\r | |
| 2495 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r | |
| 2496 | \r | |
| 2497 | @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)\r | |
| 2498 | @param EAX Lower 32-bits of MSR value.\r | |
| 2499 | @param EDX Upper 32-bits of MSR value.\r | |
| 2500 | \r | |
| 2501 | <b>Example usage</b>\r | |
| 2502 | @code\r | |
| 2503 | UINT64 Msr;\r | |
| 2504 | \r | |
| 2505 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);\r | |
| 2506 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);\r | |
| 2507 | @endcode\r | |
| fed6c37b | 2508 | @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
2509 | **/\r |
| 2510 | #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r | |
| 2511 | \r | |
| 2512 | \r | |
| 2513 | /**\r | |
| 2514 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r | |
| 2515 | \r | |
| 2516 | @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)\r | |
| 2517 | @param EAX Lower 32-bits of MSR value.\r | |
| 2518 | @param EDX Upper 32-bits of MSR value.\r | |
| 2519 | \r | |
| 2520 | <b>Example usage</b>\r | |
| 2521 | @code\r | |
| 2522 | UINT64 Msr;\r | |
| 2523 | \r | |
| 2524 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);\r | |
| 2525 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);\r | |
| 2526 | @endcode\r | |
| fed6c37b | 2527 | @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
2528 | **/\r |
| 2529 | #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r | |
| 2530 | \r | |
| 2531 | \r | |
| 2532 | /**\r | |
| 2533 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r | |
| 2534 | \r | |
| 2535 | @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)\r | |
| 2536 | @param EAX Lower 32-bits of MSR value.\r | |
| 2537 | @param EDX Upper 32-bits of MSR value.\r | |
| 2538 | \r | |
| 2539 | <b>Example usage</b>\r | |
| 2540 | @code\r | |
| 2541 | UINT64 Msr;\r | |
| 2542 | \r | |
| 2543 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);\r | |
| 2544 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);\r | |
| 2545 | @endcode\r | |
| fed6c37b | 2546 | @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
2547 | **/\r |
| 2548 | #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r | |
| 2549 | \r | |
| 2550 | \r | |
| 2551 | /**\r | |
| 2552 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r | |
| 2553 | \r | |
| 2554 | @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)\r | |
| 2555 | @param EAX Lower 32-bits of MSR value.\r | |
| 2556 | @param EDX Upper 32-bits of MSR value.\r | |
| 2557 | \r | |
| 2558 | <b>Example usage</b>\r | |
| 2559 | @code\r | |
| 2560 | UINT64 Msr;\r | |
| 2561 | \r | |
| 2562 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);\r | |
| 2563 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);\r | |
| 2564 | @endcode\r | |
| fed6c37b | 2565 | @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
2566 | **/\r |
| 2567 | #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r | |
| 2568 | \r | |
| 2569 | \r | |
| 2570 | /**\r | |
| 2571 | Package. Uncore C-box 13 perfmon box wide filter.\r | |
| 2572 | \r | |
| 2573 | @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)\r | |
| 2574 | @param EAX Lower 32-bits of MSR value.\r | |
| 2575 | @param EDX Upper 32-bits of MSR value.\r | |
| 2576 | \r | |
| 2577 | <b>Example usage</b>\r | |
| 2578 | @code\r | |
| 2579 | UINT64 Msr;\r | |
| 2580 | \r | |
| 2581 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);\r | |
| 2582 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);\r | |
| 2583 | @endcode\r | |
| fed6c37b | 2584 | @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
2585 | **/\r |
| 2586 | #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r | |
| 2587 | \r | |
| 2588 | \r | |
| 2589 | /**\r | |
| 2590 | Package. Uncore C-box 13 perfmon counter 0.\r | |
| 2591 | \r | |
| 2592 | @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)\r | |
| 2593 | @param EAX Lower 32-bits of MSR value.\r | |
| 2594 | @param EDX Upper 32-bits of MSR value.\r | |
| 2595 | \r | |
| 2596 | <b>Example usage</b>\r | |
| 2597 | @code\r | |
| 2598 | UINT64 Msr;\r | |
| 2599 | \r | |
| 2600 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);\r | |
| 2601 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);\r | |
| 2602 | @endcode\r | |
| fed6c37b | 2603 | @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
2604 | **/\r |
| 2605 | #define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r | |
| 2606 | \r | |
| 2607 | \r | |
| 2608 | /**\r | |
| 2609 | Package. Uncore C-box 13 perfmon counter 1.\r | |
| 2610 | \r | |
| 2611 | @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)\r | |
| 2612 | @param EAX Lower 32-bits of MSR value.\r | |
| 2613 | @param EDX Upper 32-bits of MSR value.\r | |
| 2614 | \r | |
| 2615 | <b>Example usage</b>\r | |
| 2616 | @code\r | |
| 2617 | UINT64 Msr;\r | |
| 2618 | \r | |
| 2619 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);\r | |
| 2620 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);\r | |
| 2621 | @endcode\r | |
| fed6c37b | 2622 | @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
2623 | **/\r |
| 2624 | #define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r | |
| 2625 | \r | |
| 2626 | \r | |
| 2627 | /**\r | |
| 2628 | Package. Uncore C-box 13 perfmon counter 2.\r | |
| 2629 | \r | |
| 2630 | @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)\r | |
| 2631 | @param EAX Lower 32-bits of MSR value.\r | |
| 2632 | @param EDX Upper 32-bits of MSR value.\r | |
| 2633 | \r | |
| 2634 | <b>Example usage</b>\r | |
| 2635 | @code\r | |
| 2636 | UINT64 Msr;\r | |
| 2637 | \r | |
| 2638 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);\r | |
| 2639 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);\r | |
| 2640 | @endcode\r | |
| fed6c37b | 2641 | @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2642 | **/\r |
| 2643 | #define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r | |
| 2644 | \r | |
| 2645 | \r | |
| 2646 | /**\r | |
| 2647 | Package. Uncore C-box 13 perfmon counter 3.\r | |
| 2648 | \r | |
| 2649 | @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)\r | |
| 2650 | @param EAX Lower 32-bits of MSR value.\r | |
| 2651 | @param EDX Upper 32-bits of MSR value.\r | |
| 2652 | \r | |
| 2653 | <b>Example usage</b>\r | |
| 2654 | @code\r | |
| 2655 | UINT64 Msr;\r | |
| 2656 | \r | |
| 2657 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);\r | |
| 2658 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);\r | |
| 2659 | @endcode\r | |
| fed6c37b | 2660 | @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2661 | **/\r |
| 2662 | #define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r | |
| 2663 | \r | |
| 2664 | \r | |
| 2665 | /**\r | |
| 2666 | Package. Uncore C-box 13 perfmon box wide filter1.\r | |
| 2667 | \r | |
| 2668 | @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)\r | |
| 2669 | @param EAX Lower 32-bits of MSR value.\r | |
| 2670 | @param EDX Upper 32-bits of MSR value.\r | |
| 2671 | \r | |
| 2672 | <b>Example usage</b>\r | |
| 2673 | @code\r | |
| 2674 | UINT64 Msr;\r | |
| 2675 | \r | |
| 2676 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);\r | |
| 2677 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);\r | |
| 2678 | @endcode\r | |
| fed6c37b | 2679 | @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2680 | **/\r |
| 2681 | #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r | |
| 2682 | \r | |
| 2683 | \r | |
| 2684 | /**\r | |
| 2685 | Package. Uncore C-box 14 perfmon local box wide control.\r | |
| 2686 | \r | |
| 2687 | @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)\r | |
| 2688 | @param EAX Lower 32-bits of MSR value.\r | |
| 2689 | @param EDX Upper 32-bits of MSR value.\r | |
| 2690 | \r | |
| 2691 | <b>Example usage</b>\r | |
| 2692 | @code\r | |
| 2693 | UINT64 Msr;\r | |
| 2694 | \r | |
| 2695 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);\r | |
| 2696 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);\r | |
| 2697 | @endcode\r | |
| fed6c37b | 2698 | @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
2699 | **/\r |
| 2700 | #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r | |
| 2701 | \r | |
| 2702 | \r | |
| 2703 | /**\r | |
| 2704 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r | |
| 2705 | \r | |
| 2706 | @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)\r | |
| 2707 | @param EAX Lower 32-bits of MSR value.\r | |
| 2708 | @param EDX Upper 32-bits of MSR value.\r | |
| 2709 | \r | |
| 2710 | <b>Example usage</b>\r | |
| 2711 | @code\r | |
| 2712 | UINT64 Msr;\r | |
| 2713 | \r | |
| 2714 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);\r | |
| 2715 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);\r | |
| 2716 | @endcode\r | |
| fed6c37b | 2717 | @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
2718 | **/\r |
| 2719 | #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r | |
| 2720 | \r | |
| 2721 | \r | |
| 2722 | /**\r | |
| 2723 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r | |
| 2724 | \r | |
| 2725 | @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)\r | |
| 2726 | @param EAX Lower 32-bits of MSR value.\r | |
| 2727 | @param EDX Upper 32-bits of MSR value.\r | |
| 2728 | \r | |
| 2729 | <b>Example usage</b>\r | |
| 2730 | @code\r | |
| 2731 | UINT64 Msr;\r | |
| 2732 | \r | |
| 2733 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);\r | |
| 2734 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);\r | |
| 2735 | @endcode\r | |
| fed6c37b | 2736 | @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
2737 | **/\r |
| 2738 | #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r | |
| 2739 | \r | |
| 2740 | \r | |
| 2741 | /**\r | |
| 2742 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r | |
| 2743 | \r | |
| 2744 | @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)\r | |
| 2745 | @param EAX Lower 32-bits of MSR value.\r | |
| 2746 | @param EDX Upper 32-bits of MSR value.\r | |
| 2747 | \r | |
| 2748 | <b>Example usage</b>\r | |
| 2749 | @code\r | |
| 2750 | UINT64 Msr;\r | |
| 2751 | \r | |
| 2752 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);\r | |
| 2753 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);\r | |
| 2754 | @endcode\r | |
| fed6c37b | 2755 | @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
2756 | **/\r |
| 2757 | #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r | |
| 2758 | \r | |
| 2759 | \r | |
| 2760 | /**\r | |
| 2761 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r | |
| 2762 | \r | |
| 2763 | @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)\r | |
| 2764 | @param EAX Lower 32-bits of MSR value.\r | |
| 2765 | @param EDX Upper 32-bits of MSR value.\r | |
| 2766 | \r | |
| 2767 | <b>Example usage</b>\r | |
| 2768 | @code\r | |
| 2769 | UINT64 Msr;\r | |
| 2770 | \r | |
| 2771 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);\r | |
| 2772 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);\r | |
| 2773 | @endcode\r | |
| fed6c37b | 2774 | @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
2775 | **/\r |
| 2776 | #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r | |
| 2777 | \r | |
| 2778 | \r | |
| 2779 | /**\r | |
| 2780 | Package. Uncore C-box 14 perfmon box wide filter.\r | |
| 2781 | \r | |
| 2782 | @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)\r | |
| 2783 | @param EAX Lower 32-bits of MSR value.\r | |
| 2784 | @param EDX Upper 32-bits of MSR value.\r | |
| 2785 | \r | |
| 2786 | <b>Example usage</b>\r | |
| 2787 | @code\r | |
| 2788 | UINT64 Msr;\r | |
| 2789 | \r | |
| 2790 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);\r | |
| 2791 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);\r | |
| 2792 | @endcode\r | |
| fed6c37b | 2793 | @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
2794 | **/\r |
| 2795 | #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r | |
| 2796 | \r | |
| 2797 | \r | |
| 2798 | /**\r | |
| 2799 | Package. Uncore C-box 14 perfmon counter 0.\r | |
| 2800 | \r | |
| 2801 | @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)\r | |
| 2802 | @param EAX Lower 32-bits of MSR value.\r | |
| 2803 | @param EDX Upper 32-bits of MSR value.\r | |
| 2804 | \r | |
| 2805 | <b>Example usage</b>\r | |
| 2806 | @code\r | |
| 2807 | UINT64 Msr;\r | |
| 2808 | \r | |
| 2809 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);\r | |
| 2810 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);\r | |
| 2811 | @endcode\r | |
| fed6c37b | 2812 | @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
2813 | **/\r |
| 2814 | #define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r | |
| 2815 | \r | |
| 2816 | \r | |
| 2817 | /**\r | |
| 2818 | Package. Uncore C-box 14 perfmon counter 1.\r | |
| 2819 | \r | |
| 2820 | @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)\r | |
| 2821 | @param EAX Lower 32-bits of MSR value.\r | |
| 2822 | @param EDX Upper 32-bits of MSR value.\r | |
| 2823 | \r | |
| 2824 | <b>Example usage</b>\r | |
| 2825 | @code\r | |
| 2826 | UINT64 Msr;\r | |
| 2827 | \r | |
| 2828 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);\r | |
| 2829 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);\r | |
| 2830 | @endcode\r | |
| fed6c37b | 2831 | @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
2832 | **/\r |
| 2833 | #define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r | |
| 2834 | \r | |
| 2835 | \r | |
| 2836 | /**\r | |
| 2837 | Package. Uncore C-box 14 perfmon counter 2.\r | |
| 2838 | \r | |
| 2839 | @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)\r | |
| 2840 | @param EAX Lower 32-bits of MSR value.\r | |
| 2841 | @param EDX Upper 32-bits of MSR value.\r | |
| 2842 | \r | |
| 2843 | <b>Example usage</b>\r | |
| 2844 | @code\r | |
| 2845 | UINT64 Msr;\r | |
| 2846 | \r | |
| 2847 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);\r | |
| 2848 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);\r | |
| 2849 | @endcode\r | |
| fed6c37b | 2850 | @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2851 | **/\r |
| 2852 | #define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r | |
| 2853 | \r | |
| 2854 | \r | |
| 2855 | /**\r | |
| 2856 | Package. Uncore C-box 14 perfmon counter 3.\r | |
| 2857 | \r | |
| 2858 | @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)\r | |
| 2859 | @param EAX Lower 32-bits of MSR value.\r | |
| 2860 | @param EDX Upper 32-bits of MSR value.\r | |
| 2861 | \r | |
| 2862 | <b>Example usage</b>\r | |
| 2863 | @code\r | |
| 2864 | UINT64 Msr;\r | |
| 2865 | \r | |
| 2866 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);\r | |
| 2867 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);\r | |
| 2868 | @endcode\r | |
| fed6c37b | 2869 | @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2870 | **/\r |
| 2871 | #define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r | |
| 2872 | \r | |
| 2873 | \r | |
| 2874 | /**\r | |
| 2875 | Package. Uncore C-box 14 perfmon box wide filter1.\r | |
| 2876 | \r | |
| 2877 | @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)\r | |
| 2878 | @param EAX Lower 32-bits of MSR value.\r | |
| 2879 | @param EDX Upper 32-bits of MSR value.\r | |
| 2880 | \r | |
| 2881 | <b>Example usage</b>\r | |
| 2882 | @code\r | |
| 2883 | UINT64 Msr;\r | |
| 2884 | \r | |
| 2885 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);\r | |
| 2886 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);\r | |
| 2887 | @endcode\r | |
| fed6c37b | 2888 | @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2889 | **/\r |
| 2890 | #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r | |
| 2891 | \r | |
| 2892 | #endif\r |