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[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / XeonPhiMsr.h
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3adf6316
MK		 1/** @file\r
2 MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
f4c982bf 9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
3adf6316
MK		 10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
0f16be6d 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17.\r
3adf6316
MK		 21\r
22**/\r
23\r
24#ifndef __XEON_PHI_MSR_H__\r
25#define __XEON_PHI_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
f4c982bf
JF		 29/**\r
30 Is Intel(R) Xeon(R) Phi(TM) processor Family?\r
31\r
32 @param DisplayFamily Display Family ID\r
33 @param DisplayModel Display Model ID\r
34\r
35 @retval TRUE Yes, it is.\r
36 @retval FALSE No, it isn't.\r
37**/\r
38#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \\r
39 (DisplayFamily == 0x06 && \\r
40 ( \\r
41 DisplayModel == 0x57 \\r
42 ) \\r
43 )\r
44\r
3adf6316
MK		 45/**\r
46 Thread. SMI Counter (R/O).\r
47\r
48 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)\r
49 @param EAX Lower 32-bits of MSR value.\r
50 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r
51 @param EDX Upper 32-bits of MSR value.\r
52 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r
53\r
54 <b>Example usage</b>\r
55 @code\r
56 MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;\r
57\r
58 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);\r
59 @endcode\r
ad8a2f5e 60 @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
3adf6316
MK		 61**/\r
62#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
63\r
64/**\r
65 MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r
66**/\r
67typedef union {\r
68 ///\r
69 /// Individual bit fields\r
70 ///\r
71 struct {\r
72 ///\r
73 /// [Bits 31:0] SMI Count (R/O).\r
74 ///\r
75 UINT32 SMICount:32;\r
76 UINT32 Reserved:32;\r
77 } Bits;\r
78 ///\r
79 /// All bit fields as a 32-bit value\r
80 ///\r
81 UINT32 Uint32;\r
82 ///\r
83 /// All bit fields as a 64-bit value\r
84 ///\r
85 UINT64 Uint64;\r
86} MSR_XEON_PHI_SMI_COUNT_REGISTER;\r
87\r
88\r
89/**\r
90 Package. See http://biosbits.org.\r
91\r
92 @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)\r
93 @param EAX Lower 32-bits of MSR value.\r
94 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r
95 @param EDX Upper 32-bits of MSR value.\r
96 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r
97\r
98 <b>Example usage</b>\r
99 @code\r
100 MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;\r
101\r
102 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);\r
103 AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);\r
104 @endcode\r
ad8a2f5e 105 @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
3adf6316
MK		 106**/\r
107#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
108\r
109/**\r
110 MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r
111**/\r
112typedef union {\r
113 ///\r
114 /// Individual bit fields\r
115 ///\r
116 struct {\r
117 UINT32 Reserved1:8;\r
118 ///\r
119 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
120 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
121 /// MHz.\r
122 ///\r
123 UINT32 MaximumNonTurboRatio:8;\r
124 UINT32 Reserved2:12;\r
125 ///\r
126 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
127 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
128 /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
129 /// Turbo mode is disabled.\r
130 ///\r
131 UINT32 RatioLimit:1;\r
132 ///\r
133 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
134 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
135 /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
136 /// programmable.\r
137 ///\r
138 UINT32 TDPLimit:1;\r
139 UINT32 Reserved3:2;\r
140 UINT32 Reserved4:8;\r
141 ///\r
142 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
143 /// minimum ratio (maximum efficiency) that the processor can operates, in\r
144 /// units of 100MHz.\r
145 ///\r
146 UINT32 MaximumEfficiencyRatio:8;\r
147 UINT32 Reserved5:16;\r
148 } Bits;\r
149 ///\r
150 /// All bit fields as a 64-bit value\r
151 ///\r
152 UINT64 Uint64;\r
153} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r
154\r
155\r
156/**\r
157 Module. C-State Configuration Control (R/W).\r
158\r
159 @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
160 @param EAX Lower 32-bits of MSR value.\r
161 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r
162 @param EDX Upper 32-bits of MSR value.\r
163 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r
164\r
165 <b>Example usage</b>\r
166 @code\r
167 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
168\r
169 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);\r
170 AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
171 @endcode\r
ad8a2f5e 172 @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
3adf6316
MK		 173**/\r
174#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
175\r
176/**\r
177 MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r
178**/\r
179typedef union {\r
180 ///\r
181 /// Individual bit fields\r
182 ///\r
183 struct {\r
184 ///\r
185 /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code\r
186 /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r
187 /// Retention 011b: C6 Retention 111b: No limit.\r
188 ///\r
189 UINT32 Limit:3;\r
190 UINT32 Reserved1:7;\r
191 ///\r
192 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
193 ///\r
194 UINT32 IO_MWAIT:1;\r
195 UINT32 Reserved2:4;\r
196 ///\r
197 /// [Bit 15] CFG Lock (R/WO).\r
198 ///\r
199 UINT32 CFGLock:1;\r
200 UINT32 Reserved3:16;\r
201 UINT32 Reserved4:32;\r
202 } Bits;\r
203 ///\r
204 /// All bit fields as a 32-bit value\r
205 ///\r
206 UINT32 Uint32;\r
207 ///\r
208 /// All bit fields as a 64-bit value\r
209 ///\r
210 UINT64 Uint64;\r
211} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r
212\r
213\r
214/**\r
215 Module. Power Management IO Redirection in C-state (R/W).\r
216\r
217 @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)\r
218 @param EAX Lower 32-bits of MSR value.\r
219 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r
220 @param EDX Upper 32-bits of MSR value.\r
221 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r
222\r
223 <b>Example usage</b>\r
224 @code\r
225 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
226\r
227 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);\r
228 AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
229 @endcode\r
ad8a2f5e 230 @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
3adf6316
MK		 231**/\r
232#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
233\r
234/**\r
235 MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r
236**/\r
237typedef union {\r
238 ///\r
239 /// Individual bit fields\r
240 ///\r
241 struct {\r
242 ///\r
243 /// [Bits 15:0] LVL_2 Base Address (R/W).\r
244 ///\r
245 UINT32 Lvl2Base:16;\r
246 ///\r
247 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
248 /// maximum C-State code name to be included when IO read to MWAIT\r
249 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r
250 /// is the max C-State to include 110b - C6 is the max C-State to include.\r
251 ///\r
252 UINT32 CStateRange:3;\r
253 UINT32 Reserved1:13;\r
254 UINT32 Reserved2:32;\r
255 } Bits;\r
256 ///\r
257 /// All bit fields as a 32-bit value\r
258 ///\r
259 UINT32 Uint32;\r
260 ///\r
261 /// All bit fields as a 64-bit value\r
262 ///\r
263 UINT64 Uint64;\r
264} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r
265\r
266\r
267/**\r
268 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
269 handler to handle unsuccessful read of this MSR.\r
270\r
271 @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)\r
272 @param EAX Lower 32-bits of MSR value.\r
273 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r
274 @param EDX Upper 32-bits of MSR value.\r
275 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r
276\r
277 <b>Example usage</b>\r
278 @code\r
279 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;\r
280\r
281 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);\r
282 AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);\r
283 @endcode\r
ad8a2f5e 284 @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
3adf6316
MK		 285**/\r
286#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
287\r
288/**\r
289 MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r
290**/\r
291typedef union {\r
292 ///\r
293 /// Individual bit fields\r
294 ///\r
295 struct {\r
296 ///\r
297 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
298 /// MSR, the configuration of AES instruction set availability is as\r
299 /// follows: 11b: AES instructions are not available until next RESET.\r
300 /// otherwise, AES instructions are available. Note, AES instruction set\r
301 /// is not available if read is unsuccessful. If the configuration is not\r
302 /// 01b, AES instruction can be mis-configured if a privileged agent\r
303 /// unintentionally writes 11b.\r
304 ///\r
305 UINT32 AESConfiguration:2;\r
306 UINT32 Reserved1:30;\r
307 UINT32 Reserved2:32;\r
308 } Bits;\r
309 ///\r
310 /// All bit fields as a 32-bit value\r
311 ///\r
312 UINT32 Uint32;\r
313 ///\r
314 /// All bit fields as a 64-bit value\r
315 ///\r
316 UINT64 Uint64;\r
317} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
318\r
319\r
0f16be6d
HW		 320/**\r
321 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
322 Enhancement. Accessible only while in SMM.\r
323\r
324 @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)\r
325 @param EAX Lower 32-bits of MSR value.\r
326 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
327 @param EDX Upper 32-bits of MSR value.\r
328 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
329\r
330 <b>Example usage</b>\r
331 @code\r
332 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;\r
333\r
334 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);\r
335 AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);\r
336 @endcode\r
337 @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
338**/\r
339#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
340\r
341/**\r
342 MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r
343**/\r
344typedef union {\r
345 ///\r
346 /// Individual bit fields\r
347 ///\r
348 struct {\r
349 UINT32 Reserved1:32;\r
350 UINT32 Reserved2:26;\r
351 ///\r
352 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
353 /// SMM code access restriction is supported and a host-space interface\r
354 /// available to SMM handler.\r
355 ///\r
356 UINT32 SMM_Code_Access_Chk:1;\r
357 ///\r
358 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
359 /// SMM long flow indicator is supported and a host-space interface\r
360 /// available to SMM handler.\r
361 ///\r
362 UINT32 Long_Flow_Indication:1;\r
363 UINT32 Reserved3:4;\r
364 } Bits;\r
365 ///\r
366 /// All bit fields as a 64-bit value\r
367 ///\r
368 UINT64 Uint64;\r
369} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r
370\r
371\r
3adf6316
MK		 372/**\r
373 Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
374 functions to be enabled and disabled.\r
375\r
376 @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)\r
377 @param EAX Lower 32-bits of MSR value.\r
378 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r
379 @param EDX Upper 32-bits of MSR value.\r
380 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r
381\r
382 <b>Example usage</b>\r
383 @code\r
384 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;\r
385\r
386 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);\r
387 AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);\r
388 @endcode\r
ad8a2f5e 389 @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
3adf6316
MK		 390**/\r
391#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
392\r
393/**\r
394 MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r
395**/\r
396typedef union {\r
397 ///\r
398 /// Individual bit fields\r
399 ///\r
400 struct {\r
401 ///\r
402 /// [Bit 0] Fast-Strings Enable.\r
403 ///\r
404 UINT32 FastStrings:1;\r
405 UINT32 Reserved1:2;\r
406 ///\r
0f16be6d
HW		 407 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r
408 /// is 1.\r
3adf6316
MK		 409 ///\r
410 UINT32 AutomaticThermalControlCircuit:1;\r
411 UINT32 Reserved2:3;\r
412 ///\r
413 /// [Bit 7] Performance Monitoring Available (R).\r
414 ///\r
415 UINT32 PerformanceMonitoring:1;\r
416 UINT32 Reserved3:3;\r
417 ///\r
418 /// [Bit 11] Branch Trace Storage Unavailable (RO).\r
419 ///\r
420 UINT32 BTS:1;\r
421 ///\r
0f16be6d 422 /// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r
3adf6316
MK		 423 ///\r
424 UINT32 PEBS:1;\r
425 UINT32 Reserved4:3;\r
426 ///\r
427 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r
428 ///\r
429 UINT32 EIST:1;\r
430 UINT32 Reserved5:1;\r
431 ///\r
432 /// [Bit 18] ENABLE MONITOR FSM (R/W).\r
433 ///\r
434 UINT32 MONITOR:1;\r
435 UINT32 Reserved6:3;\r
436 ///\r
437 /// [Bit 22] Limit CPUID Maxval (R/W).\r
438 ///\r
439 UINT32 LimitCpuidMaxval:1;\r
440 ///\r
441 /// [Bit 23] xTPR Message Disable (R/W).\r
442 ///\r
443 UINT32 xTPR_Message_Disable:1;\r
444 UINT32 Reserved7:8;\r
445 UINT32 Reserved8:2;\r
446 ///\r
447 /// [Bit 34] XD Bit Disable (R/W).\r
448 ///\r
449 UINT32 XD:1;\r
450 UINT32 Reserved9:3;\r
451 ///\r
452 /// [Bit 38] Turbo Mode Disable (R/W).\r
453 ///\r
454 UINT32 TurboModeDisable:1;\r
455 UINT32 Reserved10:25;\r
456 } Bits;\r
457 ///\r
458 /// All bit fields as a 64-bit value\r
459 ///\r
460 UINT64 Uint64;\r
461} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r
462\r
463\r
464/**\r
465 Package.\r
466\r
467 @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)\r
468 @param EAX Lower 32-bits of MSR value.\r
469 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r
470 @param EDX Upper 32-bits of MSR value.\r
471 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r
472\r
473 <b>Example usage</b>\r
474 @code\r
475 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;\r
476\r
477 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);\r
478 AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);\r
479 @endcode\r
ad8a2f5e 480 @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
3adf6316
MK		 481**/\r
482#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
483\r
484/**\r
485 MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r
486**/\r
487typedef union {\r
488 ///\r
489 /// Individual bit fields\r
490 ///\r
491 struct {\r
492 UINT32 Reserved1:16;\r
493 ///\r
494 /// [Bits 23:16] Temperature Target (R).\r
495 ///\r
496 UINT32 TemperatureTarget:8;\r
497 ///\r
498 /// [Bits 29:24] Target Offset (R/W).\r
499 ///\r
500 UINT32 TargetOffset:6;\r
501 UINT32 Reserved2:2;\r
502 UINT32 Reserved3:32;\r
503 } Bits;\r
504 ///\r
505 /// All bit fields as a 32-bit value\r
506 ///\r
507 UINT32 Uint32;\r
508 ///\r
509 /// All bit fields as a 64-bit value\r
510 ///\r
511 UINT64 Uint64;\r
512} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r
513\r
514\r
0f16be6d
HW		 515/**\r
516 Miscellaneous Feature Control (R/W).\r
517\r
518 @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)\r
519 @param EAX Lower 32-bits of MSR value.\r
520 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
521 @param EDX Upper 32-bits of MSR value.\r
522 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
523\r
524 <b>Example usage</b>\r
525 @code\r
526 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;\r
527\r
528 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);\r
529 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);\r
530 @endcode\r
531 @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
532**/\r
533#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
534\r
535/**\r
536 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r
537**/\r
538typedef union {\r
539 ///\r
540 /// Individual bit fields\r
541 ///\r
542 struct {\r
543 ///\r
544 /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r
545 /// L1 data cache prefetcher.\r
546 ///\r
547 UINT32 DCUHardwarePrefetcherDisable:1;\r
548 ///\r
549 /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
550 /// L2 hardware prefetcher.\r
551 ///\r
552 UINT32 L2HardwarePrefetcherDisable:1;\r
553 UINT32 Reserved1:30;\r
554 UINT32 Reserved2:32;\r
555 } Bits;\r
556 ///\r
557 /// All bit fields as a 32-bit value\r
558 ///\r
559 UINT32 Uint32;\r
560 ///\r
561 /// All bit fields as a 64-bit value\r
562 ///\r
563 UINT64 Uint64;\r
564} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r
565\r
566\r
3adf6316
MK		 567/**\r
568 Shared. Offcore Response Event Select Register (R/W).\r
569\r
570 @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)\r
571 @param EAX Lower 32-bits of MSR value.\r
572 @param EDX Upper 32-bits of MSR value.\r
573\r
574 <b>Example usage</b>\r
575 @code\r
576 UINT64 Msr;\r
577\r
578 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);\r
579 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);\r
580 @endcode\r
ad8a2f5e 581 @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
3adf6316
MK		 582**/\r
583#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
584\r
585\r
586/**\r
587 Shared. Offcore Response Event Select Register (R/W).\r
588\r
589 @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)\r
590 @param EAX Lower 32-bits of MSR value.\r
591 @param EDX Upper 32-bits of MSR value.\r
592\r
593 <b>Example usage</b>\r
594 @code\r
595 UINT64 Msr;\r
596\r
597 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);\r
598 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);\r
599 @endcode\r
ad8a2f5e 600 @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
3adf6316
MK		 601**/\r
602#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
603\r
604\r
605/**\r
606 Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r
607\r
608 @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)\r
609 @param EAX Lower 32-bits of MSR value.\r
610 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r
611 @param EDX Upper 32-bits of MSR value.\r
612 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r
613\r
614 <b>Example usage</b>\r
615 @code\r
616 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;\r
617\r
618 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);\r
619 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);\r
620 @endcode\r
ad8a2f5e 621 @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
3adf6316
MK		 622**/\r
623#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
624\r
625/**\r
626 MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r
627**/\r
628typedef union {\r
629 ///\r
630 /// Individual bit fields\r
631 ///\r
632 struct {\r
633 UINT32 Reserved:1;\r
634 ///\r
635 /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r
636 /// processor cores which operates under the maximum ratio limit for group\r
637 /// 0.\r
638 ///\r
639 UINT32 MaxCoresGroup0:7;\r
640 ///\r
641 /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r
642 /// ratio limit when the number of active cores are not more than the\r
643 /// group 0 maximum core count.\r
644 ///\r
645 UINT32 MaxRatioLimitGroup0:8;\r
646 ///\r
647 /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r
648 /// Group 1, which includes the specified number of additional cores plus\r
649 /// the cores in group 0, operates under the group 1 turbo max ratio limit\r
650 /// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r
651 ///\r
652 UINT32 MaxIncrementalCoresGroup1:5;\r
653 ///\r
654 /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r
655 /// integer specifying the ratio decrement relative to the Max ratio limit\r
656 /// to Group 0.\r
657 ///\r
658 UINT32 DeltaRatioGroup1:3;\r
659 ///\r
660 /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r
661 /// Group 2, which includes the specified number of additional cores plus\r
662 /// all the cores in group 1, operates under the group 2 turbo max ratio\r
663 /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r
664 ///\r
665 UINT32 MaxIncrementalCoresGroup2:5;\r
666 ///\r
667 /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r
668 /// integer specifying the ratio decrement relative to the Max ratio limit\r
669 /// for Group 1.\r
670 ///\r
671 UINT32 DeltaRatioGroup2:3;\r
672 ///\r
673 /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r
674 /// Group 3, which includes the specified number of additional cores plus\r
675 /// all the cores in group 2, operates under the group 3 turbo max ratio\r
676 /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r
677 ///\r
678 UINT32 MaxIncrementalCoresGroup3:5;\r
679 ///\r
680 /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r
681 /// integer specifying the ratio decrement relative to the Max ratio limit\r
682 /// for Group 2.\r
683 ///\r
684 UINT32 DeltaRatioGroup3:3;\r
685 ///\r
686 /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r
687 /// Group 4, which includes the specified number of additional cores plus\r
688 /// all the cores in group 3, operates under the group 4 turbo max ratio\r
689 /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r
690 ///\r
691 UINT32 MaxIncrementalCoresGroup4:5;\r
692 ///\r
693 /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r
694 /// integer specifying the ratio decrement relative to the Max ratio limit\r
695 /// for Group 3.\r
696 ///\r
697 UINT32 DeltaRatioGroup4:3;\r
698 ///\r
699 /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r
700 /// Group 5, which includes the specified number of additional cores plus\r
701 /// all the cores in group 4, operates under the group 5 turbo max ratio\r
702 /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r
703 ///\r
704 UINT32 MaxIncrementalCoresGroup5:5;\r
705 ///\r
706 /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r
707 /// integer specifying the ratio decrement relative to the Max ratio limit\r
708 /// for Group 4.\r
709 ///\r
710 UINT32 DeltaRatioGroup5:3;\r
711 ///\r
712 /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r
713 /// Group 6, which includes the specified number of additional cores plus\r
714 /// all the cores in group 5, operates under the group 6 turbo max ratio\r
715 /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r
716 ///\r
717 UINT32 MaxIncrementalCoresGroup6:5;\r
718 ///\r
719 /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r
720 /// integer specifying the ratio decrement relative to the Max ratio limit\r
721 /// for Group 5.\r
722 ///\r
723 UINT32 DeltaRatioGroup6:3;\r
724 } Bits;\r
725 ///\r
726 /// All bit fields as a 64-bit value\r
727 ///\r
728 UINT64 Uint64;\r
729} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r
730\r
731\r
732/**\r
733 Thread. Last Branch Record Filtering Select Register (R/W).\r
734\r
735 @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)\r
736 @param EAX Lower 32-bits of MSR value.\r
737 @param EDX Upper 32-bits of MSR value.\r
738\r
739 <b>Example usage</b>\r
740 @code\r
741 UINT64 Msr;\r
742\r
743 Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);\r
744 AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);\r
745 @endcode\r
ad8a2f5e 746 @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
3adf6316
MK		 747**/\r
748#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
749\r
750\r
751/**\r
752 Thread. Last Branch Record Stack TOS (R/W).\r
753\r
754 @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)\r
755 @param EAX Lower 32-bits of MSR value.\r
756 @param EDX Upper 32-bits of MSR value.\r
757\r
758 <b>Example usage</b>\r
759 @code\r
760 UINT64 Msr;\r
761\r
762 Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);\r
763 AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);\r
764 @endcode\r
ad8a2f5e 765 @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
3adf6316
MK		 766**/\r
767#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
768\r
769\r
770/**\r
771 Thread. Last Exception Record From Linear IP (R).\r
772\r
773 @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)\r
774 @param EAX Lower 32-bits of MSR value.\r
775 @param EDX Upper 32-bits of MSR value.\r
776\r
777 <b>Example usage</b>\r
778 @code\r
779 UINT64 Msr;\r
780\r
781 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);\r
782 @endcode\r
ad8a2f5e 783 @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
3adf6316
MK		 784**/\r
785#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
786\r
787\r
788/**\r
789 Thread. Last Exception Record To Linear IP (R).\r
790\r
791 @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)\r
792 @param EAX Lower 32-bits of MSR value.\r
793 @param EDX Upper 32-bits of MSR value.\r
794\r
795 <b>Example usage</b>\r
796 @code\r
797 UINT64 Msr;\r
798\r
799 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);\r
800 @endcode\r
ad8a2f5e 801 @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
3adf6316
MK		 802**/\r
803#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
804\r
805\r
3adf6316
MK		 806/**\r
807 Thread. See Table 35-2.\r
808\r
809 @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)\r
810 @param EAX Lower 32-bits of MSR value.\r
811 @param EDX Upper 32-bits of MSR value.\r
812\r
813 <b>Example usage</b>\r
814 @code\r
815 UINT64 Msr;\r
816\r
817 Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);\r
818 AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);\r
819 @endcode\r
ad8a2f5e 820 @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
3adf6316
MK		 821**/\r
822#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
823\r
824\r
825/**\r
826 Package. Note: C-state values are processor specific C-state code names,\r
827 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3\r
828 Residency Counter. (R/O).\r
829\r
830 @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)\r
831 @param EAX Lower 32-bits of MSR value.\r
832 @param EDX Upper 32-bits of MSR value.\r
833\r
834 <b>Example usage</b>\r
835 @code\r
836 UINT64 Msr;\r
837\r
838 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);\r
839 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);\r
840 @endcode\r
ad8a2f5e 841 @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
3adf6316
MK		 842**/\r
843#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
844\r
845\r
846/**\r
847 Package. Package C6 Residency Counter. (R/O).\r
848\r
849 @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)\r
850 @param EAX Lower 32-bits of MSR value.\r
851 @param EDX Upper 32-bits of MSR value.\r
852\r
853 <b>Example usage</b>\r
854 @code\r
855 UINT64 Msr;\r
856\r
857 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);\r
858 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);\r
859 @endcode\r
ad8a2f5e 860 @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
3adf6316
MK		 861**/\r
862#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
863\r
864\r
865/**\r
866 Package. Package C7 Residency Counter. (R/O).\r
867\r
868 @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)\r
869 @param EAX Lower 32-bits of MSR value.\r
870 @param EDX Upper 32-bits of MSR value.\r
871\r
872 <b>Example usage</b>\r
873 @code\r
874 UINT64 Msr;\r
875\r
876 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);\r
877 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);\r
878 @endcode\r
ad8a2f5e 879 @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
3adf6316
MK		 880**/\r
881#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
882\r
883\r
884/**\r
885 Module. Note: C-state values are processor specific C-state code names,\r
886 unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0\r
887 Residency Counter. (R/O).\r
888\r
889 @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)\r
890 @param EAX Lower 32-bits of MSR value.\r
891 @param EDX Upper 32-bits of MSR value.\r
892\r
893 <b>Example usage</b>\r
894 @code\r
895 UINT64 Msr;\r
896\r
897 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);\r
898 AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);\r
899 @endcode\r
ad8a2f5e 900 @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r
3adf6316
MK		 901**/\r
902#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
903\r
904\r
905/**\r
906 Module. Module C6 Residency Counter. (R/O).\r
907\r
908 @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)\r
909 @param EAX Lower 32-bits of MSR value.\r
910 @param EDX Upper 32-bits of MSR value.\r
911\r
912 <b>Example usage</b>\r
913 @code\r
914 UINT64 Msr;\r
915\r
916 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);\r
917 AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);\r
918 @endcode\r
ad8a2f5e 919 @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r
3adf6316
MK		 920**/\r
921#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
922\r
923\r
924/**\r
925 Core. Note: C-state values are processor specific C-state code names,\r
926 unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6\r
927 Residency Counter. (R/O).\r
928\r
929 @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)\r
930 @param EAX Lower 32-bits of MSR value.\r
931 @param EDX Upper 32-bits of MSR value.\r
932\r
933 <b>Example usage</b>\r
934 @code\r
935 UINT64 Msr;\r
936\r
937 Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);\r
938 AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);\r
939 @endcode\r
ad8a2f5e 940 @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
3adf6316
MK		 941**/\r
942#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
943\r
944\r
3adf6316
MK		 945/**\r
946 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
947\r
948 @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
949 @param EAX Lower 32-bits of MSR value.\r
950 @param EDX Upper 32-bits of MSR value.\r
951\r
952 <b>Example usage</b>\r
953 @code\r
954 UINT64 Msr;\r
955\r
956 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);\r
957 @endcode\r
ad8a2f5e 958 @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
3adf6316
MK		 959**/\r
960#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
961\r
962\r
963/**\r
964 Core. Capability Reporting Register of VM-function Controls (R/O) See Table\r
965 35-2.\r
966\r
967 @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)\r
968 @param EAX Lower 32-bits of MSR value.\r
969 @param EDX Upper 32-bits of MSR value.\r
970\r
971 <b>Example usage</b>\r
972 @code\r
973 UINT64 Msr;\r
974\r
975 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);\r
976 @endcode\r
ad8a2f5e 977 @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
3adf6316
MK		 978**/\r
979#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
980\r
981\r
982/**\r
983 Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
984\r
985 @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)\r
986 @param EAX Lower 32-bits of MSR value.\r
987 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r
988 @param EDX Upper 32-bits of MSR value.\r
989 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r
990\r
991 <b>Example usage</b>\r
992 @code\r
993 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;\r
994\r
995 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);\r
996 @endcode\r
ad8a2f5e 997 @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
3adf6316
MK		 998**/\r
999#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
1000\r
1001/**\r
1002 MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r
1003**/\r
1004typedef union {\r
1005 ///\r
1006 /// Individual bit fields\r
1007 ///\r
1008 struct {\r
1009 ///\r
1010 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
1011 ///\r
1012 UINT32 PowerUnits:4;\r
1013 UINT32 Reserved1:4;\r
1014 ///\r
1015 /// [Bits 12:8] Package. Energy Status Units Energy related information\r
1016 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
1017 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
1018 /// micro-joules).\r
1019 ///\r
1020 UINT32 EnergyStatusUnits:5;\r
1021 UINT32 Reserved2:3;\r
1022 ///\r
1023 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
1024 /// Interfaces.".\r
1025 ///\r
1026 UINT32 TimeUnits:4;\r
1027 UINT32 Reserved3:12;\r
1028 UINT32 Reserved4:32;\r
1029 } Bits;\r
1030 ///\r
1031 /// All bit fields as a 32-bit value\r
1032 ///\r
1033 UINT32 Uint32;\r
1034 ///\r
1035 /// All bit fields as a 64-bit value\r
1036 ///\r
1037 UINT64 Uint64;\r
1038} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r
1039\r
1040\r
1041/**\r
1042 Package. Note: C-state values are processor specific C-state code names,\r
1043 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r
1044 Residency Counter. (R/O).\r
1045\r
1046 @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)\r
1047 @param EAX Lower 32-bits of MSR value.\r
1048 @param EDX Upper 32-bits of MSR value.\r
1049\r
1050 <b>Example usage</b>\r
1051 @code\r
1052 UINT64 Msr;\r
1053\r
1054 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);\r
1055 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);\r
1056 @endcode\r
ad8a2f5e 1057 @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
3adf6316
MK		 1058**/\r
1059#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
1060\r
1061\r
1062/**\r
1063 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
1064 RAPL Domain.".\r
1065\r
1066 @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)\r
1067 @param EAX Lower 32-bits of MSR value.\r
1068 @param EDX Upper 32-bits of MSR value.\r
1069\r
1070 <b>Example usage</b>\r
1071 @code\r
1072 UINT64 Msr;\r
1073\r
1074 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);\r
1075 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);\r
1076 @endcode\r
ad8a2f5e 1077 @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
3adf6316
MK		 1078**/\r
1079#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
1080\r
1081\r
1082/**\r
1083 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
1084\r
1085 @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)\r
1086 @param EAX Lower 32-bits of MSR value.\r
1087 @param EDX Upper 32-bits of MSR value.\r
1088\r
1089 <b>Example usage</b>\r
1090 @code\r
1091 UINT64 Msr;\r
1092\r
1093 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);\r
1094 @endcode\r
ad8a2f5e 1095 @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
3adf6316
MK		 1096**/\r
1097#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
1098\r
1099\r
1100/**\r
1101 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
1102\r
1103 @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)\r
1104 @param EAX Lower 32-bits of MSR value.\r
1105 @param EDX Upper 32-bits of MSR value.\r
1106\r
1107 <b>Example usage</b>\r
1108 @code\r
1109 UINT64 Msr;\r
1110\r
1111 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);\r
1112 @endcode\r
ad8a2f5e 1113 @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
3adf6316
MK		 1114**/\r
1115#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
1116\r
1117\r
1118/**\r
1119 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
1120 Domain.".\r
1121\r
1122 @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)\r
1123 @param EAX Lower 32-bits of MSR value.\r
1124 @param EDX Upper 32-bits of MSR value.\r
1125\r
1126 <b>Example usage</b>\r
1127 @code\r
1128 UINT64 Msr;\r
1129\r
1130 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);\r
1131 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);\r
1132 @endcode\r
ad8a2f5e 1133 @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
3adf6316
MK		 1134**/\r
1135#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
1136\r
1137\r
1138/**\r
1139 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
1140 Domain.".\r
1141\r
1142 @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)\r
1143 @param EAX Lower 32-bits of MSR value.\r
1144 @param EDX Upper 32-bits of MSR value.\r
1145\r
1146 <b>Example usage</b>\r
1147 @code\r
1148 UINT64 Msr;\r
1149\r
1150 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);\r
1151 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);\r
1152 @endcode\r
ad8a2f5e 1153 @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
3adf6316
MK		 1154**/\r
1155#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
1156\r
1157\r
1158/**\r
1159 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
1160\r
1161 @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)\r
1162 @param EAX Lower 32-bits of MSR value.\r
1163 @param EDX Upper 32-bits of MSR value.\r
1164\r
1165 <b>Example usage</b>\r
1166 @code\r
1167 UINT64 Msr;\r
1168\r
1169 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);\r
1170 @endcode\r
ad8a2f5e 1171 @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
3adf6316
MK		 1172**/\r
1173#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
1174\r
1175\r
1176/**\r
1177 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
1178 RAPL Domain.".\r
1179\r
1180 @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)\r
1181 @param EAX Lower 32-bits of MSR value.\r
1182 @param EDX Upper 32-bits of MSR value.\r
1183\r
1184 <b>Example usage</b>\r
1185 @code\r
1186 UINT64 Msr;\r
1187\r
1188 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);\r
1189 @endcode\r
ad8a2f5e 1190 @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
3adf6316
MK		 1191**/\r
1192#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
1193\r
1194\r
1195/**\r
1196 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
1197\r
1198 @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)\r
1199 @param EAX Lower 32-bits of MSR value.\r
1200 @param EDX Upper 32-bits of MSR value.\r
1201\r
1202 <b>Example usage</b>\r
1203 @code\r
1204 UINT64 Msr;\r
1205\r
1206 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);\r
1207 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);\r
1208 @endcode\r
ad8a2f5e 1209 @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
3adf6316
MK		 1210**/\r
1211#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
1212\r
1213\r
1214/**\r
1215 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
1216 RAPL Domains.".\r
1217\r
1218 @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)\r
1219 @param EAX Lower 32-bits of MSR value.\r
1220 @param EDX Upper 32-bits of MSR value.\r
1221\r
1222 <b>Example usage</b>\r
1223 @code\r
1224 UINT64 Msr;\r
1225\r
1226 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);\r
1227 AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);\r
1228 @endcode\r
ad8a2f5e 1229 @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
3adf6316
MK		 1230**/\r
1231#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
1232\r
1233\r
1234/**\r
1235 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
1236 Domains.".\r
1237\r
1238 @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)\r
1239 @param EAX Lower 32-bits of MSR value.\r
1240 @param EDX Upper 32-bits of MSR value.\r
1241\r
1242 <b>Example usage</b>\r
1243 @code\r
1244 UINT64 Msr;\r
1245\r
1246 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);\r
1247 @endcode\r
ad8a2f5e 1248 @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
3adf6316
MK		 1249**/\r
1250#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
1251\r
1252\r
1253/**\r
0f16be6d 1254 Package. Base TDP Ratio (R/O) See Table 35-23.\r
3adf6316
MK		 1255\r
1256 @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r
1257 @param EAX Lower 32-bits of MSR value.\r
1258 @param EDX Upper 32-bits of MSR value.\r
1259\r
1260 <b>Example usage</b>\r
1261 @code\r
1262 UINT64 Msr;\r
1263\r
1264 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);\r
1265 @endcode\r
ad8a2f5e 1266 @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
3adf6316
MK		 1267**/\r
1268#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
1269\r
1270\r
1271/**\r
0f16be6d 1272 Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23.\r
3adf6316
MK		 1273\r
1274 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r
1275 @param EAX Lower 32-bits of MSR value.\r
1276 @param EDX Upper 32-bits of MSR value.\r
1277\r
1278 <b>Example usage</b>\r
1279 @code\r
1280 UINT64 Msr;\r
1281\r
1282 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);\r
1283 @endcode\r
ad8a2f5e 1284 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
3adf6316
MK		 1285**/\r
1286#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
1287\r
1288\r
1289/**\r
0f16be6d 1290 Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23.\r
3adf6316
MK		 1291\r
1292 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r
1293 @param EAX Lower 32-bits of MSR value.\r
1294 @param EDX Upper 32-bits of MSR value.\r
1295\r
1296 <b>Example usage</b>\r
1297 @code\r
1298 UINT64 Msr;\r
1299\r
1300 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);\r
1301 @endcode\r
ad8a2f5e 1302 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
3adf6316
MK		 1303**/\r
1304#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
1305\r
1306\r
1307/**\r
0f16be6d 1308 Package. ConfigTDP Control (R/W) See Table 35-23.\r
3adf6316
MK		 1309\r
1310 @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r
1311 @param EAX Lower 32-bits of MSR value.\r
1312 @param EDX Upper 32-bits of MSR value.\r
1313\r
1314 <b>Example usage</b>\r
1315 @code\r
1316 UINT64 Msr;\r
1317\r
1318 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);\r
1319 AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);\r
1320 @endcode\r
ad8a2f5e 1321 @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
3adf6316
MK		 1322**/\r
1323#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
1324\r
1325\r
1326/**\r
0f16be6d 1327 Package. ConfigTDP Control (R/W) See Table 35-23.\r
3adf6316
MK		 1328\r
1329 @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r
1330 @param EAX Lower 32-bits of MSR value.\r
1331 @param EDX Upper 32-bits of MSR value.\r
1332\r
1333 <b>Example usage</b>\r
1334 @code\r
1335 UINT64 Msr;\r
1336\r
1337 Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);\r
1338 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);\r
1339 @endcode\r
ad8a2f5e 1340 @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
3adf6316
MK		 1341**/\r
1342#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
1343\r
1344\r
1345/**\r
1346 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
1347 refers to processor core frequency).\r
1348\r
1349 @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)\r
1350 @param EAX Lower 32-bits of MSR value.\r
1351 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r
1352 @param EDX Upper 32-bits of MSR value.\r
1353 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r
1354\r
1355 <b>Example usage</b>\r
1356 @code\r
1357 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
1358\r
1359 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);\r
1360 AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
1361 @endcode\r
ad8a2f5e 1362 @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
3adf6316
MK		 1363**/\r
1364#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
1365\r
1366/**\r
1367 MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r
1368**/\r
1369typedef union {\r
1370 ///\r
1371 /// Individual bit fields\r
1372 ///\r
1373 struct {\r
1374 ///\r
1375 /// [Bit 0] PROCHOT Status (R0).\r
1376 ///\r
1377 UINT32 PROCHOT_Status:1;\r
1378 ///\r
1379 /// [Bit 1] Thermal Status (R0).\r
1380 ///\r
1381 UINT32 ThermalStatus:1;\r
1382 UINT32 Reserved1:4;\r
1383 ///\r
1384 /// [Bit 6] VR Therm Alert Status (R0).\r
1385 ///\r
1386 UINT32 VRThermAlertStatus:1;\r
1387 UINT32 Reserved2:1;\r
1388 ///\r
1389 /// [Bit 8] Electrical Design Point Status (R0).\r
1390 ///\r
1391 UINT32 ElectricalDesignPointStatus:1;\r
1392 UINT32 Reserved3:23;\r
1393 UINT32 Reserved4:32;\r
1394 } Bits;\r
1395 ///\r
1396 /// All bit fields as a 32-bit value\r
1397 ///\r
1398 UINT32 Uint32;\r
1399 ///\r
1400 /// All bit fields as a 64-bit value\r
1401 ///\r
1402 UINT64 Uint64;\r
1403} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r
1404\r
1405#endif\r
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