2 MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17.
24 #ifndef __XEON_PHI_MSR_H__
25 #define __XEON_PHI_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel(R) Xeon(R) Phi(TM) processor Family?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x57 \
46 Thread. SMI Counter (R/O).
48 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)
49 @param EAX Lower 32-bits of MSR value.
50 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
51 @param EDX Upper 32-bits of MSR value.
52 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
56 MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;
58 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
60 @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
62 #define MSR_XEON_PHI_SMI_COUNT 0x00000034
65 MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
69 /// Individual bit fields
73 /// [Bits 31:0] SMI Count (R/O).
79 /// All bit fields as a 32-bit value
83 /// All bit fields as a 64-bit value
86 } MSR_XEON_PHI_SMI_COUNT_REGISTER
;
90 Package. See http://biosbits.org.
92 @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
93 @param EAX Lower 32-bits of MSR value.
94 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
95 @param EDX Upper 32-bits of MSR value.
96 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
100 MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;
102 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
103 AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
105 @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
107 #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
110 MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
114 /// Individual bit fields
119 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
120 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
123 UINT32 MaximumNonTurboRatio
:8;
126 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
127 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
128 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
129 /// Turbo mode is disabled.
133 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
134 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
135 /// and when set to 0, indicates TDP Limit for Turbo mode is not
142 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
143 /// minimum ratio (maximum efficiency) that the processor can operates, in
146 UINT32 MaximumEfficiencyRatio
:8;
150 /// All bit fields as a 64-bit value
153 } MSR_XEON_PHI_PLATFORM_INFO_REGISTER
;
157 Module. C-State Configuration Control (R/W).
159 @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
160 @param EAX Lower 32-bits of MSR value.
161 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
162 @param EDX Upper 32-bits of MSR value.
163 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
167 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
169 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
170 AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
172 @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
174 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
177 MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
181 /// Individual bit fields
185 /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code
186 /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
187 /// Retention 011b: C6 Retention 111b: No limit.
192 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
197 /// [Bit 15] CFG Lock (R/WO).
204 /// All bit fields as a 32-bit value
208 /// All bit fields as a 64-bit value
211 } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
;
215 Module. Power Management IO Redirection in C-state (R/W).
217 @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
218 @param EAX Lower 32-bits of MSR value.
219 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
220 @param EDX Upper 32-bits of MSR value.
221 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
225 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;
227 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
228 AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
230 @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
232 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
235 MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
239 /// Individual bit fields
243 /// [Bits 15:0] LVL_2 Base Address (R/W).
247 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
248 /// maximum C-State code name to be included when IO read to MWAIT
249 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
250 /// is the max C-State to include 110b - C6 is the max C-State to include.
252 UINT32 CStateRange
:3;
257 /// All bit fields as a 32-bit value
261 /// All bit fields as a 64-bit value
264 } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
;
268 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
269 handler to handle unsuccessful read of this MSR.
271 @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
272 @param EAX Lower 32-bits of MSR value.
273 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
274 @param EDX Upper 32-bits of MSR value.
275 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
279 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;
281 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
282 AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
284 @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
286 #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
289 MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
293 /// Individual bit fields
297 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
298 /// MSR, the configuration of AES instruction set availability is as
299 /// follows: 11b: AES instructions are not available until next RESET.
300 /// otherwise, AES instructions are available. Note, AES instruction set
301 /// is not available if read is unsuccessful. If the configuration is not
302 /// 01b, AES instruction can be mis-configured if a privileged agent
303 /// unintentionally writes 11b.
305 UINT32 AESConfiguration
:2;
310 /// All bit fields as a 32-bit value
314 /// All bit fields as a 64-bit value
317 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
;
321 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
322 Enhancement. Accessible only while in SMM.
324 @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
325 @param EAX Lower 32-bits of MSR value.
326 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
327 @param EDX Upper 32-bits of MSR value.
328 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
332 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;
334 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
335 AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);
337 @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
339 #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
342 MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
346 /// Individual bit fields
352 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
353 /// SMM code access restriction is supported and a host-space interface
354 /// available to SMM handler.
356 UINT32 SMM_Code_Access_Chk
:1;
358 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
359 /// SMM long flow indicator is supported and a host-space interface
360 /// available to SMM handler.
362 UINT32 Long_Flow_Indication
:1;
366 /// All bit fields as a 64-bit value
369 } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
;
373 Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
374 functions to be enabled and disabled.
376 @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
377 @param EAX Lower 32-bits of MSR value.
378 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
379 @param EDX Upper 32-bits of MSR value.
380 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
384 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;
386 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
387 AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
389 @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
391 #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
394 MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
398 /// Individual bit fields
402 /// [Bit 0] Fast-Strings Enable.
404 UINT32 FastStrings
:1;
407 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
410 UINT32 AutomaticThermalControlCircuit
:1;
413 /// [Bit 7] Performance Monitoring Available (R).
415 UINT32 PerformanceMonitoring
:1;
418 /// [Bit 11] Branch Trace Storage Unavailable (RO).
422 /// [Bit 12] Processor Event Based Sampling Unavailable (RO).
427 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
432 /// [Bit 18] ENABLE MONITOR FSM (R/W).
437 /// [Bit 22] Limit CPUID Maxval (R/W).
439 UINT32 LimitCpuidMaxval
:1;
441 /// [Bit 23] xTPR Message Disable (R/W).
443 UINT32 xTPR_Message_Disable
:1;
447 /// [Bit 34] XD Bit Disable (R/W).
452 /// [Bit 38] Turbo Mode Disable (R/W).
454 UINT32 TurboModeDisable
:1;
455 UINT32 Reserved10
:25;
458 /// All bit fields as a 64-bit value
461 } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
;
467 @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
468 @param EAX Lower 32-bits of MSR value.
469 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
470 @param EDX Upper 32-bits of MSR value.
471 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
475 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;
477 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
478 AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
480 @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
482 #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
485 MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
489 /// Individual bit fields
494 /// [Bits 23:16] Temperature Target (R).
496 UINT32 TemperatureTarget
:8;
498 /// [Bits 29:24] Target Offset (R/W).
500 UINT32 TargetOffset
:6;
505 /// All bit fields as a 32-bit value
509 /// All bit fields as a 64-bit value
512 } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
;
516 Miscellaneous Feature Control (R/W).
518 @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
519 @param EAX Lower 32-bits of MSR value.
520 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
521 @param EDX Upper 32-bits of MSR value.
522 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
526 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;
528 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
529 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);
531 @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
533 #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
536 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
540 /// Individual bit fields
544 /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
545 /// L1 data cache prefetcher.
547 UINT32 DCUHardwarePrefetcherDisable
:1;
549 /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
550 /// L2 hardware prefetcher.
552 UINT32 L2HardwarePrefetcherDisable
:1;
557 /// All bit fields as a 32-bit value
561 /// All bit fields as a 64-bit value
564 } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
;
568 Shared. Offcore Response Event Select Register (R/W).
570 @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
571 @param EAX Lower 32-bits of MSR value.
572 @param EDX Upper 32-bits of MSR value.
578 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
579 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
581 @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
583 #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
587 Shared. Offcore Response Event Select Register (R/W).
589 @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
590 @param EAX Lower 32-bits of MSR value.
591 @param EDX Upper 32-bits of MSR value.
597 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
598 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
600 @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
602 #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
606 Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
608 @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
609 @param EAX Lower 32-bits of MSR value.
610 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
611 @param EDX Upper 32-bits of MSR value.
612 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
616 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;
618 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
619 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
621 @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
623 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
626 MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
630 /// Individual bit fields
635 /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
636 /// processor cores which operates under the maximum ratio limit for group
639 UINT32 MaxCoresGroup0
:7;
641 /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
642 /// ratio limit when the number of active cores are not more than the
643 /// group 0 maximum core count.
645 UINT32 MaxRatioLimitGroup0
:8;
647 /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
648 /// Group 1, which includes the specified number of additional cores plus
649 /// the cores in group 0, operates under the group 1 turbo max ratio limit
650 /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
652 UINT32 MaxIncrementalCoresGroup1
:5;
654 /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
655 /// integer specifying the ratio decrement relative to the Max ratio limit
658 UINT32 DeltaRatioGroup1
:3;
660 /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
661 /// Group 2, which includes the specified number of additional cores plus
662 /// all the cores in group 1, operates under the group 2 turbo max ratio
663 /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
665 UINT32 MaxIncrementalCoresGroup2
:5;
667 /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
668 /// integer specifying the ratio decrement relative to the Max ratio limit
671 UINT32 DeltaRatioGroup2
:3;
673 /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
674 /// Group 3, which includes the specified number of additional cores plus
675 /// all the cores in group 2, operates under the group 3 turbo max ratio
676 /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
678 UINT32 MaxIncrementalCoresGroup3
:5;
680 /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
681 /// integer specifying the ratio decrement relative to the Max ratio limit
684 UINT32 DeltaRatioGroup3
:3;
686 /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
687 /// Group 4, which includes the specified number of additional cores plus
688 /// all the cores in group 3, operates under the group 4 turbo max ratio
689 /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
691 UINT32 MaxIncrementalCoresGroup4
:5;
693 /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
694 /// integer specifying the ratio decrement relative to the Max ratio limit
697 UINT32 DeltaRatioGroup4
:3;
699 /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
700 /// Group 5, which includes the specified number of additional cores plus
701 /// all the cores in group 4, operates under the group 5 turbo max ratio
702 /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
704 UINT32 MaxIncrementalCoresGroup5
:5;
706 /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
707 /// integer specifying the ratio decrement relative to the Max ratio limit
710 UINT32 DeltaRatioGroup5
:3;
712 /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
713 /// Group 6, which includes the specified number of additional cores plus
714 /// all the cores in group 5, operates under the group 6 turbo max ratio
715 /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
717 UINT32 MaxIncrementalCoresGroup6
:5;
719 /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
720 /// integer specifying the ratio decrement relative to the Max ratio limit
723 UINT32 DeltaRatioGroup6
:3;
726 /// All bit fields as a 64-bit value
729 } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
;
733 Thread. Last Branch Record Filtering Select Register (R/W).
735 @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)
736 @param EAX Lower 32-bits of MSR value.
737 @param EDX Upper 32-bits of MSR value.
743 Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
744 AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
746 @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
748 #define MSR_XEON_PHI_LBR_SELECT 0x000001C8
752 Thread. Last Branch Record Stack TOS (R/W).
754 @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
755 @param EAX Lower 32-bits of MSR value.
756 @param EDX Upper 32-bits of MSR value.
762 Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
763 AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
765 @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
767 #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
771 Thread. Last Exception Record From Linear IP (R).
773 @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
774 @param EAX Lower 32-bits of MSR value.
775 @param EDX Upper 32-bits of MSR value.
781 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
783 @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
785 #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
789 Thread. Last Exception Record To Linear IP (R).
791 @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
792 @param EAX Lower 32-bits of MSR value.
793 @param EDX Upper 32-bits of MSR value.
799 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
801 @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
803 #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
807 Thread. See Table 35-2.
809 @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
810 @param EAX Lower 32-bits of MSR value.
811 @param EDX Upper 32-bits of MSR value.
817 Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
818 AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
820 @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
822 #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
826 Package. Note: C-state values are processor specific C-state code names,
827 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
828 Residency Counter. (R/O).
830 @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
831 @param EAX Lower 32-bits of MSR value.
832 @param EDX Upper 32-bits of MSR value.
838 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
839 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
841 @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
843 #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
847 Package. Package C6 Residency Counter. (R/O).
849 @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
850 @param EAX Lower 32-bits of MSR value.
851 @param EDX Upper 32-bits of MSR value.
857 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
858 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
860 @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
862 #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
866 Package. Package C7 Residency Counter. (R/O).
868 @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
869 @param EAX Lower 32-bits of MSR value.
870 @param EDX Upper 32-bits of MSR value.
876 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
877 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
879 @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
881 #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
885 Module. Note: C-state values are processor specific C-state code names,
886 unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
887 Residency Counter. (R/O).
889 @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
890 @param EAX Lower 32-bits of MSR value.
891 @param EDX Upper 32-bits of MSR value.
897 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
898 AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
900 @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
902 #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
906 Module. Module C6 Residency Counter. (R/O).
908 @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
909 @param EAX Lower 32-bits of MSR value.
910 @param EDX Upper 32-bits of MSR value.
916 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
917 AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
919 @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
921 #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
925 Core. Note: C-state values are processor specific C-state code names,
926 unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
927 Residency Counter. (R/O).
929 @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
930 @param EAX Lower 32-bits of MSR value.
931 @param EDX Upper 32-bits of MSR value.
937 Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
938 AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
940 @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
942 #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
946 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
948 @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
949 @param EAX Lower 32-bits of MSR value.
950 @param EDX Upper 32-bits of MSR value.
956 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
958 @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
960 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
964 Core. Capability Reporting Register of VM-function Controls (R/O) See Table
967 @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
968 @param EAX Lower 32-bits of MSR value.
969 @param EDX Upper 32-bits of MSR value.
975 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
977 @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
979 #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
983 Package. Unit Multipliers used in RAPL Interfaces (R/O).
985 @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
986 @param EAX Lower 32-bits of MSR value.
987 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
988 @param EDX Upper 32-bits of MSR value.
989 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
993 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;
995 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
997 @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
999 #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
1002 MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
1006 /// Individual bit fields
1010 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1012 UINT32 PowerUnits
:4;
1015 /// [Bits 12:8] Package. Energy Status Units Energy related information
1016 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1017 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1020 UINT32 EnergyStatusUnits
:5;
1023 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1027 UINT32 Reserved3
:12;
1028 UINT32 Reserved4
:32;
1031 /// All bit fields as a 32-bit value
1035 /// All bit fields as a 64-bit value
1038 } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
;
1042 Package. Note: C-state values are processor specific C-state code names,
1043 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
1044 Residency Counter. (R/O).
1046 @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
1047 @param EAX Lower 32-bits of MSR value.
1048 @param EDX Upper 32-bits of MSR value.
1050 <b>Example usage</b>
1054 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
1055 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
1057 @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1059 #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
1063 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1066 @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
1067 @param EAX Lower 32-bits of MSR value.
1068 @param EDX Upper 32-bits of MSR value.
1070 <b>Example usage</b>
1074 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
1075 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
1077 @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1079 #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
1083 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1085 @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
1086 @param EAX Lower 32-bits of MSR value.
1087 @param EDX Upper 32-bits of MSR value.
1089 <b>Example usage</b>
1093 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
1095 @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1097 #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
1101 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1103 @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
1104 @param EAX Lower 32-bits of MSR value.
1105 @param EDX Upper 32-bits of MSR value.
1107 <b>Example usage</b>
1111 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
1113 @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1115 #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
1119 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1122 @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
1123 @param EAX Lower 32-bits of MSR value.
1124 @param EDX Upper 32-bits of MSR value.
1126 <b>Example usage</b>
1130 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
1131 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
1133 @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1135 #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
1139 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1142 @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
1143 @param EAX Lower 32-bits of MSR value.
1144 @param EDX Upper 32-bits of MSR value.
1146 <b>Example usage</b>
1150 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
1151 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
1153 @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1155 #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
1159 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1161 @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
1162 @param EAX Lower 32-bits of MSR value.
1163 @param EDX Upper 32-bits of MSR value.
1165 <b>Example usage</b>
1169 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
1171 @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1173 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
1177 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1180 @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
1181 @param EAX Lower 32-bits of MSR value.
1182 @param EDX Upper 32-bits of MSR value.
1184 <b>Example usage</b>
1188 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
1190 @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1192 #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
1196 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1198 @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
1199 @param EAX Lower 32-bits of MSR value.
1200 @param EDX Upper 32-bits of MSR value.
1202 <b>Example usage</b>
1206 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
1207 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
1209 @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1211 #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
1215 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1218 @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
1219 @param EAX Lower 32-bits of MSR value.
1220 @param EDX Upper 32-bits of MSR value.
1222 <b>Example usage</b>
1226 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
1227 AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
1229 @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1231 #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
1235 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1238 @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
1239 @param EAX Lower 32-bits of MSR value.
1240 @param EDX Upper 32-bits of MSR value.
1242 <b>Example usage</b>
1246 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
1248 @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1250 #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
1254 Package. Base TDP Ratio (R/O) See Table 35-23.
1256 @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
1257 @param EAX Lower 32-bits of MSR value.
1258 @param EDX Upper 32-bits of MSR value.
1260 <b>Example usage</b>
1264 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
1266 @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
1268 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
1272 Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23.
1274 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
1275 @param EAX Lower 32-bits of MSR value.
1276 @param EDX Upper 32-bits of MSR value.
1278 <b>Example usage</b>
1282 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
1284 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
1286 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
1290 Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23.
1292 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
1293 @param EAX Lower 32-bits of MSR value.
1294 @param EDX Upper 32-bits of MSR value.
1296 <b>Example usage</b>
1300 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
1302 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
1304 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
1308 Package. ConfigTDP Control (R/W) See Table 35-23.
1310 @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
1311 @param EAX Lower 32-bits of MSR value.
1312 @param EDX Upper 32-bits of MSR value.
1314 <b>Example usage</b>
1318 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
1319 AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
1321 @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
1323 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
1327 Package. ConfigTDP Control (R/W) See Table 35-23.
1329 @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
1330 @param EAX Lower 32-bits of MSR value.
1331 @param EDX Upper 32-bits of MSR value.
1333 <b>Example usage</b>
1337 Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
1338 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
1340 @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
1342 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
1346 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1347 refers to processor core frequency).
1349 @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
1350 @param EAX Lower 32-bits of MSR value.
1351 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1352 @param EDX Upper 32-bits of MSR value.
1353 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1355 <b>Example usage</b>
1357 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1359 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
1360 AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1362 @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1364 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
1367 MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
1371 /// Individual bit fields
1375 /// [Bit 0] PROCHOT Status (R0).
1377 UINT32 PROCHOT_Status
:1;
1379 /// [Bit 1] Thermal Status (R0).
1381 UINT32 ThermalStatus
:1;
1384 /// [Bit 6] VR Therm Alert Status (R0).
1386 UINT32 VRThermAlertStatus
:1;
1389 /// [Bit 8] Electrical Design Point Status (R0).
1391 UINT32 ElectricalDesignPointStatus
:1;
1392 UINT32 Reserved3
:23;
1393 UINT32 Reserved4
:32;
1396 /// All bit fields as a 32-bit value
1400 /// All bit fields as a 64-bit value
1403 } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
;