Update the copyright notice format
[mirror_edk2.git] / UefiCpuPkg / Library / BaseUefiCpuLib / Ia32 / InitializeFpu.S
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d6d8e892 1#------------------------------------------------------------------------------\r
2#*\r
01a1c0fc
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3#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
4#* This program and the accompanying materials\r
d6d8e892 5#* are licensed and made available under the terms and conditions of the BSD License\r
6#* which accompanies this distribution. The full text of the license may be found at\r
7#* http://opensource.org/licenses/bsd-license.php\r
8#*\r
9#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11#*\r
12#*\r
13#------------------------------------------------------------------------------\r
14\r
989322c3 15#\r
16# Float control word initial value: \r
17# all exceptions masked, double-precision, round-to-nearest\r
18#\r
19ASM_PFX(mFpuControlWord): .word 0x027F\r
20#\r
21# Multimedia-extensions control word:\r
22# all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
23#\r
d6d8e892 24ASM_PFX(mMmxControlWord): .long 0x01F80\r
25\r
26#\r
989322c3 27# Initializes floating point units for requirement of UEFI specification.\r
28#\r
29# This function initializes floating-point control word to 0x027F (all exceptions\r
30# masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
31# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
d6d8e892 32# for masked underflow).\r
33#\r
34ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)\r
35ASM_PFX(InitializeFloatingPointUnits):\r
36\r
37 pushl %ebx\r
38\r
989322c3 39 #\r
40 # Initialize floating point units\r
41 #\r
42 finit\r
43 fldcw ASM_PFX(mFpuControlWord)\r
44 \r
45 #\r
46 # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
47 # whether the processor supports SSE instruction.\r
48 #\r
49 movl $1, %eax\r
50 cpuid\r
51 btl $25, %edx\r
52 jnc Done\r
d6d8e892 53 \r
54 #\r
55 # Set OSFXSR bit 9 in CR4\r
56 #\r
57 movl %cr4, %eax \r
2127579b 58 or $0x200, %eax\r
d6d8e892 59 movl %eax, %cr4\r
60 \r
989322c3 61 #\r
62 # The processor should support SSE instruction and we can use\r
63 # ldmxcsr instruction\r
64 #\r
d6d8e892 65 ldmxcsr ASM_PFX(mMmxControlWord)\r
66\r
67Done:\r
68 popl %ebx\r
69\r
70 ret\r
71\r
72#END\r
73\r