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bf73cc4b | 1 | /** @file\r |
2 | Local APIC Library.\r | |
3 | \r | |
4 | This local APIC library instance supports xAPIC mode only.\r | |
5 | \r | |
7f33d4f2 | 6 | Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r |
df667535 | 7 | Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>\r |
061ead7a | 8 | \r |
0acd8697 | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bf73cc4b | 10 | \r |
11 | **/\r | |
12 | \r | |
01acb06c | 13 | #include <Register/Intel/Cpuid.h>\r |
061ead7a | 14 | #include <Register/Amd/Cpuid.h>\r |
01acb06c RN |
15 | #include <Register/Intel/Msr.h>\r |
16 | #include <Register/Intel/LocalApic.h>\r | |
bf73cc4b | 17 | \r |
18 | #include <Library/BaseLib.h>\r | |
19 | #include <Library/DebugLib.h>\r | |
20 | #include <Library/LocalApicLib.h>\r | |
21 | #include <Library/IoLib.h>\r | |
22 | #include <Library/TimerLib.h>\r | |
59d67246 | 23 | #include <Library/PcdLib.h>\r |
df667535 | 24 | #include <Library/UefiCpuLib.h>\r |
bf73cc4b | 25 | \r |
26 | //\r | |
27 | // Library internal functions\r | |
28 | //\r | |
29 | \r | |
59d67246 MK |
30 | /**\r |
31 | Determine if the CPU supports the Local APIC Base Address MSR.\r | |
32 | \r | |
33 | @retval TRUE The CPU supports the Local APIC Base Address MSR.\r | |
34 | @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r | |
35 | \r | |
36 | **/\r | |
37 | BOOLEAN\r | |
38 | LocalApicBaseAddressMsrSupported (\r | |
39 | VOID\r | |
40 | )\r | |
41 | {\r | |
42 | UINT32 RegEax;\r | |
43 | UINTN FamilyId;\r | |
7367cc6c | 44 | \r |
59d67246 MK |
45 | AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r |
46 | FamilyId = BitFieldRead32 (RegEax, 8, 11);\r | |
053e878b | 47 | if ((FamilyId == 0x04) || (FamilyId == 0x05)) {\r |
59d67246 | 48 | //\r |
7367cc6c | 49 | // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r |
59d67246 MK |
50 | // Local APIC Base Address MSR\r |
51 | //\r | |
52 | return FALSE;\r | |
53 | }\r | |
053e878b | 54 | \r |
59d67246 MK |
55 | return TRUE;\r |
56 | }\r | |
57 | \r | |
a66e0c7d | 58 | /**\r |
59 | Retrieve the base address of local APIC.\r | |
60 | \r | |
61 | @return The base address of local APIC.\r | |
62 | \r | |
63 | **/\r | |
64 | UINTN\r | |
65 | EFIAPI\r | |
66 | GetLocalApicBaseAddress (\r | |
67 | VOID\r | |
68 | )\r | |
69 | {\r | |
a742e186 | 70 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r |
59d67246 MK |
71 | \r |
72 | if (!LocalApicBaseAddressMsrSupported ()) {\r | |
73 | //\r | |
74 | // If CPU does not support Local APIC Base Address MSR, then retrieve\r | |
75 | // Local APIC Base Address from PCD\r | |
76 | //\r | |
77 | return PcdGet32 (PcdCpuLocalApicBaseAddress);\r | |
78 | }\r | |
79 | \r | |
a742e186 | 80 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
7367cc6c | 81 | \r |
053e878b MK |
82 | return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r |
83 | (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r | |
a66e0c7d | 84 | }\r |
85 | \r | |
86 | /**\r | |
87 | Set the base address of local APIC.\r | |
88 | \r | |
89 | If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r | |
90 | \r | |
91 | @param[in] BaseAddress Local APIC base address to be set.\r | |
92 | \r | |
93 | **/\r | |
94 | VOID\r | |
95 | EFIAPI\r | |
96 | SetLocalApicBaseAddress (\r | |
053e878b | 97 | IN UINTN BaseAddress\r |
a66e0c7d | 98 | )\r |
99 | {\r | |
a742e186 | 100 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r |
a66e0c7d | 101 | \r |
102 | ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r | |
103 | \r | |
59d67246 MK |
104 | if (!LocalApicBaseAddressMsrSupported ()) {\r |
105 | //\r | |
106 | // Ignore set request if the CPU does not support APIC Base Address MSR\r | |
107 | //\r | |
108 | return;\r | |
109 | }\r | |
110 | \r | |
a742e186 | 111 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
a66e0c7d | 112 | \r |
053e878b MK |
113 | ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);\r |
114 | ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));\r | |
a66e0c7d | 115 | \r |
a742e186 | 116 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r |
a66e0c7d | 117 | }\r |
118 | \r | |
bf73cc4b | 119 | /**\r |
120 | Read from a local APIC register.\r | |
121 | \r | |
122 | This function reads from a local APIC register either in xAPIC or x2APIC mode.\r | |
123 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
124 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
125 | 32-bit read.\r | |
126 | \r | |
127 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
128 | It must be 16-byte aligned.\r | |
129 | \r | |
130 | @return 32-bit Value read from the register.\r | |
131 | **/\r | |
132 | UINT32\r | |
133 | EFIAPI\r | |
134 | ReadLocalApicReg (\r | |
135 | IN UINTN MmioOffset\r | |
136 | )\r | |
137 | {\r | |
138 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
139 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
140 | \r | |
053e878b | 141 | return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);\r |
bf73cc4b | 142 | }\r |
143 | \r | |
144 | /**\r | |
145 | Write to a local APIC register.\r | |
146 | \r | |
147 | This function writes to a local APIC register either in xAPIC or x2APIC mode.\r | |
148 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
149 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
150 | 32-bit write.\r | |
151 | \r | |
152 | if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r | |
153 | \r | |
154 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
155 | It must be 16-byte aligned.\r | |
156 | @param Value Value to be written to the register.\r | |
157 | **/\r | |
158 | VOID\r | |
159 | EFIAPI\r | |
160 | WriteLocalApicReg (\r | |
053e878b MK |
161 | IN UINTN MmioOffset,\r |
162 | IN UINT32 Value\r | |
bf73cc4b | 163 | )\r |
164 | {\r | |
165 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
166 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
167 | \r | |
053e878b | 168 | MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);\r |
bf73cc4b | 169 | }\r |
170 | \r | |
171 | /**\r | |
172 | Send an IPI by writing to ICR.\r | |
173 | \r | |
7367cc6c | 174 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 175 | \r |
176 | @param IcrLow 32-bit value to be written to the low half of ICR.\r | |
177 | @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r | |
178 | **/\r | |
179 | VOID\r | |
180 | SendIpi (\r | |
053e878b MK |
181 | IN UINT32 IcrLow,\r |
182 | IN UINT32 ApicId\r | |
bf73cc4b | 183 | )\r |
184 | {\r | |
053e878b MK |
185 | LOCAL_APIC_ICR_LOW IcrLowReg;\r |
186 | UINT32 IcrHigh;\r | |
187 | BOOLEAN InterruptState;\r | |
bf73cc4b | 188 | \r |
189 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
190 | ASSERT (ApicId <= 0xff);\r | |
191 | \r | |
9c71e1e0 JF |
192 | InterruptState = SaveAndDisableInterrupts ();\r |
193 | \r | |
194 | //\r | |
195 | // Save existing contents of ICR high 32 bits\r | |
196 | //\r | |
197 | IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);\r | |
198 | \r | |
199 | //\r | |
200 | // Wait for DeliveryStatus clear in case a previous IPI\r | |
201 | // is still being sent\r | |
202 | //\r | |
203 | do {\r | |
204 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
205 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
206 | \r | |
bf73cc4b | 207 | //\r |
208 | // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r | |
209 | //\r | |
210 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r | |
211 | WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r | |
9c71e1e0 JF |
212 | \r |
213 | //\r | |
214 | // Wait for DeliveryStatus clear again\r | |
215 | //\r | |
bf73cc4b | 216 | do {\r |
217 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
218 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
9c71e1e0 JF |
219 | \r |
220 | //\r | |
221 | // And restore old contents of ICR high\r | |
222 | //\r | |
223 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r | |
224 | \r | |
225 | SetInterruptState (InterruptState);\r | |
bf73cc4b | 226 | }\r |
227 | \r | |
228 | //\r | |
229 | // Library API implementation functions\r | |
230 | //\r | |
231 | \r | |
232 | /**\r | |
233 | Get the current local APIC mode.\r | |
234 | \r | |
235 | If local APIC is disabled, then ASSERT.\r | |
236 | \r | |
237 | @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r | |
238 | @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r | |
239 | **/\r | |
240 | UINTN\r | |
241 | EFIAPI\r | |
242 | GetApicMode (\r | |
243 | VOID\r | |
244 | )\r | |
245 | {\r | |
7c2a6033 | 246 | DEBUG_CODE_BEGIN ();\r |
053e878b MK |
247 | {\r |
248 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r | |
bf73cc4b | 249 | \r |
053e878b MK |
250 | //\r |
251 | // Check to see if the CPU supports the APIC Base Address MSR\r | |
252 | //\r | |
253 | if (LocalApicBaseAddressMsrSupported ()) {\r | |
254 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
bf73cc4b | 255 | //\r |
053e878b | 256 | // Local APIC should have been enabled\r |
bf73cc4b | 257 | //\r |
053e878b MK |
258 | ASSERT (ApicBaseMsr.Bits.EN != 0);\r |
259 | ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r | |
bf73cc4b | 260 | }\r |
053e878b | 261 | }\r |
7c2a6033 | 262 | DEBUG_CODE_END ();\r |
bf73cc4b | 263 | return LOCAL_APIC_MODE_XAPIC;\r |
264 | }\r | |
265 | \r | |
266 | /**\r | |
267 | Set the current local APIC mode.\r | |
268 | \r | |
269 | If the specified local APIC mode is not valid, then ASSERT.\r | |
270 | If the specified local APIC mode can't be set as current, then ASSERT.\r | |
271 | \r | |
272 | @param ApicMode APIC mode to be set.\r | |
9c71e1e0 JF |
273 | \r |
274 | @note This API must not be called from an interrupt handler or SMI handler.\r | |
275 | It may result in unpredictable behavior.\r | |
bf73cc4b | 276 | **/\r |
277 | VOID\r | |
278 | EFIAPI\r | |
279 | SetApicMode (\r | |
280 | IN UINTN ApicMode\r | |
281 | )\r | |
282 | {\r | |
283 | ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r | |
284 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
285 | }\r | |
286 | \r | |
287 | /**\r | |
288 | Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r | |
289 | \r | |
6e3e4d70 | 290 | In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r |
7367cc6c | 291 | In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r |
bf73cc4b | 292 | the 32-bit local APIC ID is returned as initial APIC ID.\r |
293 | \r | |
294 | @return 32-bit initial local APIC ID of the executing processor.\r | |
295 | **/\r | |
296 | UINT32\r | |
297 | EFIAPI\r | |
298 | GetInitialApicId (\r | |
299 | VOID\r | |
300 | )\r | |
301 | {\r | |
053e878b MK |
302 | UINT32 ApicId;\r |
303 | UINT32 MaxCpuIdIndex;\r | |
304 | UINT32 RegEbx;\r | |
bf73cc4b | 305 | \r |
306 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
307 | \r | |
6e3e4d70 JF |
308 | //\r |
309 | // Get the max index of basic CPUID\r | |
310 | //\r | |
311 | AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r | |
312 | \r | |
313 | //\r | |
7367cc6c | 314 | // If CPUID Leaf B is supported,\r |
4af3ae14 | 315 | // And CPUID.0BH:EBX[15:0] reports a non-zero value,\r |
6e3e4d70 JF |
316 | // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r |
317 | // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r | |
318 | //\r | |
319 | if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
4af3ae14 LE |
320 | AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);\r |
321 | if ((RegEbx & (BIT16 - 1)) != 0) {\r | |
322 | return ApicId;\r | |
323 | }\r | |
6e3e4d70 JF |
324 | }\r |
325 | \r | |
bf73cc4b | 326 | AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r |
327 | return RegEbx >> 24;\r | |
328 | }\r | |
329 | \r | |
330 | /**\r | |
331 | Get the local APIC ID of the executing processor.\r | |
332 | \r | |
333 | @return 32-bit local APIC ID of the executing processor.\r | |
334 | **/\r | |
335 | UINT32\r | |
336 | EFIAPI\r | |
337 | GetApicId (\r | |
338 | VOID\r | |
339 | )\r | |
340 | {\r | |
053e878b | 341 | UINT32 ApicId;\r |
bf73cc4b | 342 | \r |
343 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
7367cc6c | 344 | \r |
6e3e4d70 JF |
345 | if ((ApicId = GetInitialApicId ()) < 0x100) {\r |
346 | //\r | |
347 | // If the initial local APIC ID is less 0x100, read APIC ID from\r | |
348 | // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.\r | |
349 | //\r | |
053e878b | 350 | ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r |
6e3e4d70 JF |
351 | ApicId >>= 24;\r |
352 | }\r | |
053e878b | 353 | \r |
bf73cc4b | 354 | return ApicId;\r |
355 | }\r | |
356 | \r | |
ae40aef1 | 357 | /**\r |
358 | Get the value of the local APIC version register.\r | |
359 | \r | |
360 | @return the value of the local APIC version register.\r | |
361 | **/\r | |
362 | UINT32\r | |
363 | EFIAPI\r | |
364 | GetApicVersion (\r | |
365 | VOID\r | |
366 | )\r | |
367 | {\r | |
368 | return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r | |
369 | }\r | |
370 | \r | |
371 | /**\r | |
372 | Send a Fixed IPI to a specified target processor.\r | |
373 | \r | |
7367cc6c | 374 | This function returns after the IPI has been accepted by the target processor.\r |
ae40aef1 | 375 | \r |
376 | @param ApicId The local APIC ID of the target processor.\r | |
377 | @param Vector The vector number of the interrupt being sent.\r | |
378 | **/\r | |
379 | VOID\r | |
380 | EFIAPI\r | |
381 | SendFixedIpi (\r | |
053e878b MK |
382 | IN UINT32 ApicId,\r |
383 | IN UINT8 Vector\r | |
ae40aef1 | 384 | )\r |
385 | {\r | |
053e878b | 386 | LOCAL_APIC_ICR_LOW IcrLow;\r |
ae40aef1 | 387 | \r |
053e878b | 388 | IcrLow.Uint32 = 0;\r |
ae40aef1 | 389 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r |
053e878b MK |
390 | IcrLow.Bits.Level = 1;\r |
391 | IcrLow.Bits.Vector = Vector;\r | |
ae40aef1 | 392 | SendIpi (IcrLow.Uint32, ApicId);\r |
393 | }\r | |
394 | \r | |
395 | /**\r | |
396 | Send a Fixed IPI to all processors excluding self.\r | |
397 | \r | |
7367cc6c | 398 | This function returns after the IPI has been accepted by the target processors.\r |
ae40aef1 | 399 | \r |
400 | @param Vector The vector number of the interrupt being sent.\r | |
401 | **/\r | |
402 | VOID\r | |
403 | EFIAPI\r | |
404 | SendFixedIpiAllExcludingSelf (\r | |
053e878b | 405 | IN UINT8 Vector\r |
ae40aef1 | 406 | )\r |
407 | {\r | |
053e878b | 408 | LOCAL_APIC_ICR_LOW IcrLow;\r |
ae40aef1 | 409 | \r |
053e878b MK |
410 | IcrLow.Uint32 = 0;\r |
411 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
412 | IcrLow.Bits.Level = 1;\r | |
ae40aef1 | 413 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r |
053e878b | 414 | IcrLow.Bits.Vector = Vector;\r |
ae40aef1 | 415 | SendIpi (IcrLow.Uint32, 0);\r |
416 | }\r | |
417 | \r | |
bf73cc4b | 418 | /**\r |
419 | Send a SMI IPI to a specified target processor.\r | |
420 | \r | |
7367cc6c | 421 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 422 | \r |
423 | @param ApicId Specify the local APIC ID of the target processor.\r | |
424 | **/\r | |
425 | VOID\r | |
426 | EFIAPI\r | |
427 | SendSmiIpi (\r | |
053e878b | 428 | IN UINT32 ApicId\r |
bf73cc4b | 429 | )\r |
430 | {\r | |
053e878b | 431 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 432 | \r |
053e878b | 433 | IcrLow.Uint32 = 0;\r |
bf73cc4b | 434 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r |
053e878b | 435 | IcrLow.Bits.Level = 1;\r |
bf73cc4b | 436 | SendIpi (IcrLow.Uint32, ApicId);\r |
437 | }\r | |
438 | \r | |
439 | /**\r | |
440 | Send a SMI IPI to all processors excluding self.\r | |
441 | \r | |
7367cc6c | 442 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 443 | **/\r |
444 | VOID\r | |
445 | EFIAPI\r | |
446 | SendSmiIpiAllExcludingSelf (\r | |
447 | VOID\r | |
448 | )\r | |
449 | {\r | |
053e878b | 450 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 451 | \r |
053e878b MK |
452 | IcrLow.Uint32 = 0;\r |
453 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
454 | IcrLow.Bits.Level = 1;\r | |
bf73cc4b | 455 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r |
456 | SendIpi (IcrLow.Uint32, 0);\r | |
457 | }\r | |
458 | \r | |
459 | /**\r | |
460 | Send an INIT IPI to a specified target processor.\r | |
461 | \r | |
7367cc6c | 462 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 463 | \r |
464 | @param ApicId Specify the local APIC ID of the target processor.\r | |
465 | **/\r | |
466 | VOID\r | |
467 | EFIAPI\r | |
468 | SendInitIpi (\r | |
053e878b | 469 | IN UINT32 ApicId\r |
bf73cc4b | 470 | )\r |
471 | {\r | |
053e878b | 472 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 473 | \r |
053e878b | 474 | IcrLow.Uint32 = 0;\r |
bf73cc4b | 475 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r |
053e878b | 476 | IcrLow.Bits.Level = 1;\r |
bf73cc4b | 477 | SendIpi (IcrLow.Uint32, ApicId);\r |
478 | }\r | |
479 | \r | |
480 | /**\r | |
481 | Send an INIT IPI to all processors excluding self.\r | |
482 | \r | |
7367cc6c | 483 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 484 | **/\r |
485 | VOID\r | |
486 | EFIAPI\r | |
487 | SendInitIpiAllExcludingSelf (\r | |
488 | VOID\r | |
489 | )\r | |
490 | {\r | |
053e878b | 491 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 492 | \r |
053e878b MK |
493 | IcrLow.Uint32 = 0;\r |
494 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
495 | IcrLow.Bits.Level = 1;\r | |
bf73cc4b | 496 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r |
497 | SendIpi (IcrLow.Uint32, 0);\r | |
498 | }\r | |
499 | \r | |
500 | /**\r | |
501 | Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r | |
502 | \r | |
7367cc6c | 503 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 504 | \r |
505 | if StartupRoutine >= 1M, then ASSERT.\r | |
506 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
507 | \r | |
508 | @param ApicId Specify the local APIC ID of the target processor.\r | |
509 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
510 | address and 4K aligned.\r | |
511 | **/\r | |
512 | VOID\r | |
513 | EFIAPI\r | |
514 | SendInitSipiSipi (\r | |
053e878b MK |
515 | IN UINT32 ApicId,\r |
516 | IN UINT32 StartupRoutine\r | |
bf73cc4b | 517 | )\r |
518 | {\r | |
053e878b | 519 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 520 | \r |
521 | ASSERT (StartupRoutine < 0x100000);\r | |
522 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
523 | \r | |
524 | SendInitIpi (ApicId);\r | |
053e878b MK |
525 | MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r |
526 | IcrLow.Uint32 = 0;\r | |
527 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
bf73cc4b | 528 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r |
053e878b | 529 | IcrLow.Bits.Level = 1;\r |
bf73cc4b | 530 | SendIpi (IcrLow.Uint32, ApicId);\r |
bf252e29 ED |
531 | if (!StandardSignatureIsAuthenticAMD ()) {\r |
532 | MicroSecondDelay (200);\r | |
533 | SendIpi (IcrLow.Uint32, ApicId);\r | |
534 | }\r | |
bf73cc4b | 535 | }\r |
536 | \r | |
537 | /**\r | |
538 | Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r | |
539 | \r | |
7367cc6c | 540 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 541 | \r |
542 | if StartupRoutine >= 1M, then ASSERT.\r | |
543 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
544 | \r | |
545 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
546 | address and 4K aligned.\r | |
547 | **/\r | |
548 | VOID\r | |
549 | EFIAPI\r | |
550 | SendInitSipiSipiAllExcludingSelf (\r | |
053e878b | 551 | IN UINT32 StartupRoutine\r |
bf73cc4b | 552 | )\r |
553 | {\r | |
053e878b | 554 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 555 | \r |
556 | ASSERT (StartupRoutine < 0x100000);\r | |
557 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
558 | \r | |
559 | SendInitIpiAllExcludingSelf ();\r | |
053e878b MK |
560 | MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r |
561 | IcrLow.Uint32 = 0;\r | |
562 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
563 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
564 | IcrLow.Bits.Level = 1;\r | |
bf73cc4b | 565 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r |
566 | SendIpi (IcrLow.Uint32, 0);\r | |
bf252e29 ED |
567 | if (!StandardSignatureIsAuthenticAMD ()) {\r |
568 | MicroSecondDelay (200);\r | |
569 | SendIpi (IcrLow.Uint32, 0);\r | |
570 | }\r | |
bf73cc4b | 571 | }\r |
572 | \r | |
14e4ca25 MK |
573 | /**\r |
574 | Initialize the state of the SoftwareEnable bit in the Local APIC\r | |
575 | Spurious Interrupt Vector register.\r | |
576 | \r | |
577 | @param Enable If TRUE, then set SoftwareEnable to 1\r | |
578 | If FALSE, then set SoftwareEnable to 0.\r | |
579 | \r | |
580 | **/\r | |
581 | VOID\r | |
582 | EFIAPI\r | |
583 | InitializeLocalApicSoftwareEnable (\r | |
584 | IN BOOLEAN Enable\r | |
585 | )\r | |
586 | {\r | |
587 | LOCAL_APIC_SVR Svr;\r | |
588 | \r | |
589 | //\r | |
590 | // Set local APIC software-enabled bit.\r | |
591 | //\r | |
592 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
593 | if (Enable) {\r | |
594 | if (Svr.Bits.SoftwareEnable == 0) {\r | |
595 | Svr.Bits.SoftwareEnable = 1;\r | |
596 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
597 | }\r | |
598 | } else {\r | |
599 | if (Svr.Bits.SoftwareEnable == 1) {\r | |
600 | Svr.Bits.SoftwareEnable = 0;\r | |
601 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
602 | }\r | |
603 | }\r | |
604 | }\r | |
605 | \r | |
bf73cc4b | 606 | /**\r |
607 | Programming Virtual Wire Mode.\r | |
608 | \r | |
609 | This function programs the local APIC for virtual wire mode following\r | |
610 | the example described in chapter A.3 of the MP 1.4 spec.\r | |
611 | \r | |
612 | IOxAPIC is not involved in this type of virtual wire mode.\r | |
613 | **/\r | |
614 | VOID\r | |
615 | EFIAPI\r | |
616 | ProgramVirtualWireMode (\r | |
617 | VOID\r | |
618 | )\r | |
619 | {\r | |
053e878b MK |
620 | LOCAL_APIC_SVR Svr;\r |
621 | LOCAL_APIC_LVT_LINT Lint;\r | |
bf73cc4b | 622 | \r |
623 | //\r | |
624 | // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r | |
625 | //\r | |
053e878b | 626 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r |
bf73cc4b | 627 | Svr.Bits.SpuriousVector = 0xf;\r |
628 | Svr.Bits.SoftwareEnable = 1;\r | |
629 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
630 | \r | |
631 | //\r | |
632 | // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r | |
633 | //\r | |
053e878b MK |
634 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r |
635 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r | |
bf73cc4b | 636 | Lint.Bits.InputPinPolarity = 0;\r |
053e878b MK |
637 | Lint.Bits.TriggerMode = 0;\r |
638 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 639 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r |
bf73cc4b | 640 | \r |
641 | //\r | |
642 | // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r | |
643 | //\r | |
053e878b MK |
644 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r |
645 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r | |
bf73cc4b | 646 | Lint.Bits.InputPinPolarity = 0;\r |
053e878b MK |
647 | Lint.Bits.TriggerMode = 0;\r |
648 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 649 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r |
bf73cc4b | 650 | }\r |
651 | \r | |
b1b8c631 | 652 | /**\r |
653 | Disable LINT0 & LINT1 interrupts.\r | |
654 | \r | |
655 | This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r | |
656 | **/\r | |
657 | VOID\r | |
658 | EFIAPI\r | |
659 | DisableLvtInterrupts (\r | |
660 | VOID\r | |
661 | )\r | |
662 | {\r | |
053e878b | 663 | LOCAL_APIC_LVT_LINT LvtLint;\r |
b1b8c631 | 664 | \r |
053e878b | 665 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r |
b1b8c631 | 666 | LvtLint.Bits.Mask = 1;\r |
667 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r | |
668 | \r | |
053e878b | 669 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r |
b1b8c631 | 670 | LvtLint.Bits.Mask = 1;\r |
671 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r | |
672 | }\r | |
673 | \r | |
bf73cc4b | 674 | /**\r |
675 | Read the initial count value from the init-count register.\r | |
676 | \r | |
677 | @return The initial count value read from the init-count register.\r | |
678 | **/\r | |
679 | UINT32\r | |
680 | EFIAPI\r | |
681 | GetApicTimerInitCount (\r | |
682 | VOID\r | |
683 | )\r | |
684 | {\r | |
685 | return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r | |
686 | }\r | |
687 | \r | |
688 | /**\r | |
689 | Read the current count value from the current-count register.\r | |
690 | \r | |
691 | @return The current count value read from the current-count register.\r | |
692 | **/\r | |
693 | UINT32\r | |
694 | EFIAPI\r | |
695 | GetApicTimerCurrentCount (\r | |
696 | VOID\r | |
697 | )\r | |
698 | {\r | |
699 | return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r | |
700 | }\r | |
701 | \r | |
702 | /**\r | |
703 | Initialize the local APIC timer.\r | |
704 | \r | |
705 | The local APIC timer is initialized and enabled.\r | |
706 | \r | |
707 | @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
708 | If it is 0, then use the current divide value in the DCR.\r | |
709 | @param InitCount The initial count value.\r | |
710 | @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
711 | @param Vector The timer interrupt vector number.\r | |
712 | **/\r | |
713 | VOID\r | |
714 | EFIAPI\r | |
715 | InitializeApicTimer (\r | |
053e878b MK |
716 | IN UINTN DivideValue,\r |
717 | IN UINT32 InitCount,\r | |
718 | IN BOOLEAN PeriodicMode,\r | |
719 | IN UINT8 Vector\r | |
bf73cc4b | 720 | )\r |
721 | {\r | |
053e878b MK |
722 | LOCAL_APIC_DCR Dcr;\r |
723 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
724 | UINT32 Divisor;\r | |
bf73cc4b | 725 | \r |
726 | //\r | |
727 | // Ensure local APIC is in software-enabled state.\r | |
728 | //\r | |
14e4ca25 | 729 | InitializeLocalApicSoftwareEnable (TRUE);\r |
bf73cc4b | 730 | \r |
731 | //\r | |
732 | // Program init-count register.\r | |
733 | //\r | |
734 | WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r | |
735 | \r | |
736 | if (DivideValue != 0) {\r | |
737 | ASSERT (DivideValue <= 128);\r | |
053e878b | 738 | ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));\r |
bf73cc4b | 739 | Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r |
740 | \r | |
053e878b | 741 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r |
bf73cc4b | 742 | Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r |
743 | Dcr.Bits.DivideValue2 = (Divisor >> 2);\r | |
7367cc6c | 744 | WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r |
bf73cc4b | 745 | }\r |
746 | \r | |
747 | //\r | |
748 | // Enable APIC timer interrupt with specified timer mode.\r | |
749 | //\r | |
750 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
751 | if (PeriodicMode) {\r | |
752 | LvtTimer.Bits.TimerMode = 1;\r | |
753 | } else {\r | |
754 | LvtTimer.Bits.TimerMode = 0;\r | |
755 | }\r | |
053e878b MK |
756 | \r |
757 | LvtTimer.Bits.Mask = 0;\r | |
bf73cc4b | 758 | LvtTimer.Bits.Vector = Vector;\r |
759 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
760 | }\r | |
761 | \r | |
ae40aef1 | 762 | /**\r |
763 | Get the state of the local APIC timer.\r | |
764 | \r | |
6d72ff7d HW |
765 | This function will ASSERT if the local APIC is not software enabled.\r |
766 | \r | |
ae40aef1 | 767 | @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r |
768 | @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
769 | @param Vector Return the timer interrupt vector number.\r | |
770 | **/\r | |
771 | VOID\r | |
772 | EFIAPI\r | |
773 | GetApicTimerState (\r | |
774 | OUT UINTN *DivideValue OPTIONAL,\r | |
775 | OUT BOOLEAN *PeriodicMode OPTIONAL,\r | |
776 | OUT UINT8 *Vector OPTIONAL\r | |
777 | )\r | |
778 | {\r | |
053e878b MK |
779 | UINT32 Divisor;\r |
780 | LOCAL_APIC_DCR Dcr;\r | |
781 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
ae40aef1 | 782 | \r |
6d72ff7d HW |
783 | //\r |
784 | // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r | |
785 | // Vector Register.\r | |
786 | // This bit will be 1, if local APIC is software enabled.\r | |
787 | //\r | |
053e878b | 788 | ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r |
6d72ff7d | 789 | \r |
ae40aef1 | 790 | if (DivideValue != NULL) {\r |
053e878b MK |
791 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r |
792 | Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r | |
793 | Divisor = (Divisor + 1) & 0x7;\r | |
ae40aef1 | 794 | *DivideValue = ((UINTN)1) << Divisor;\r |
795 | }\r | |
796 | \r | |
053e878b | 797 | if ((PeriodicMode != NULL) || (Vector != NULL)) {\r |
ae40aef1 | 798 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r |
799 | if (PeriodicMode != NULL) {\r | |
800 | if (LvtTimer.Bits.TimerMode == 1) {\r | |
801 | *PeriodicMode = TRUE;\r | |
802 | } else {\r | |
803 | *PeriodicMode = FALSE;\r | |
804 | }\r | |
805 | }\r | |
053e878b | 806 | \r |
ae40aef1 | 807 | if (Vector != NULL) {\r |
053e878b | 808 | *Vector = (UINT8)LvtTimer.Bits.Vector;\r |
ae40aef1 | 809 | }\r |
810 | }\r | |
811 | }\r | |
812 | \r | |
bf73cc4b | 813 | /**\r |
814 | Enable the local APIC timer interrupt.\r | |
815 | **/\r | |
816 | VOID\r | |
817 | EFIAPI\r | |
818 | EnableApicTimerInterrupt (\r | |
819 | VOID\r | |
820 | )\r | |
821 | {\r | |
053e878b | 822 | LOCAL_APIC_LVT_TIMER LvtTimer;\r |
bf73cc4b | 823 | \r |
053e878b | 824 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r |
bf73cc4b | 825 | LvtTimer.Bits.Mask = 0;\r |
826 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
827 | }\r | |
828 | \r | |
829 | /**\r | |
830 | Disable the local APIC timer interrupt.\r | |
831 | **/\r | |
832 | VOID\r | |
833 | EFIAPI\r | |
834 | DisableApicTimerInterrupt (\r | |
835 | VOID\r | |
836 | )\r | |
837 | {\r | |
053e878b | 838 | LOCAL_APIC_LVT_TIMER LvtTimer;\r |
bf73cc4b | 839 | \r |
053e878b | 840 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r |
bf73cc4b | 841 | LvtTimer.Bits.Mask = 1;\r |
842 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
843 | }\r | |
844 | \r | |
845 | /**\r | |
846 | Get the local APIC timer interrupt state.\r | |
847 | \r | |
848 | @retval TRUE The local APIC timer interrupt is enabled.\r | |
849 | @retval FALSE The local APIC timer interrupt is disabled.\r | |
850 | **/\r | |
851 | BOOLEAN\r | |
852 | EFIAPI\r | |
853 | GetApicTimerInterruptState (\r | |
854 | VOID\r | |
855 | )\r | |
856 | {\r | |
053e878b | 857 | LOCAL_APIC_LVT_TIMER LvtTimer;\r |
bf73cc4b | 858 | \r |
859 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
860 | return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r | |
861 | }\r | |
862 | \r | |
863 | /**\r | |
864 | Send EOI to the local APIC.\r | |
865 | **/\r | |
866 | VOID\r | |
867 | EFIAPI\r | |
868 | SendApicEoi (\r | |
869 | VOID\r | |
870 | )\r | |
871 | {\r | |
872 | WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r | |
873 | }\r | |
874 | \r | |
5f867ad0 | 875 | /**\r |
7367cc6c | 876 | Get the 32-bit address that a device should use to send a Message Signaled\r |
5f867ad0 | 877 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r |
878 | \r | |
879 | @return 32-bit address used to send an MSI to the Local APIC.\r | |
880 | **/\r | |
881 | UINT32\r | |
7367cc6c | 882 | EFIAPI\r |
5f867ad0 | 883 | GetApicMsiAddress (\r |
884 | VOID\r | |
885 | )\r | |
886 | {\r | |
887 | LOCAL_APIC_MSI_ADDRESS MsiAddress;\r | |
888 | \r | |
889 | //\r | |
7367cc6c | 890 | // Return address for an MSI interrupt to be delivered only to the APIC ID\r |
5f867ad0 | 891 | // of the currently executing processor.\r |
892 | //\r | |
893 | MsiAddress.Uint32 = 0;\r | |
894 | MsiAddress.Bits.BaseAddress = 0xFEE;\r | |
895 | MsiAddress.Bits.DestinationId = GetApicId ();\r | |
896 | return MsiAddress.Uint32;\r | |
897 | }\r | |
7367cc6c | 898 | \r |
5f867ad0 | 899 | /**\r |
7367cc6c | 900 | Get the 64-bit data value that a device should use to send a Message Signaled\r |
5f867ad0 | 901 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r |
902 | \r | |
903 | If Vector is not in range 0x10..0xFE, then ASSERT().\r | |
904 | If DeliveryMode is not supported, then ASSERT().\r | |
7367cc6c LG |
905 | \r |
906 | @param Vector The 8-bit interrupt vector associated with the MSI.\r | |
5f867ad0 | 907 | Must be in the range 0x10..0xFE\r |
7367cc6c | 908 | @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r |
5f867ad0 | 909 | is handled. The only supported values are:\r |
910 | 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r | |
911 | 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
912 | 2: LOCAL_APIC_DELIVERY_MODE_SMI\r | |
913 | 4: LOCAL_APIC_DELIVERY_MODE_NMI\r | |
914 | 5: LOCAL_APIC_DELIVERY_MODE_INIT\r | |
915 | 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r | |
7367cc6c LG |
916 | \r |
917 | @param LevelTriggered TRUE specifies a level triggered interrupt.\r | |
5f867ad0 | 918 | FALSE specifies an edge triggered interrupt.\r |
919 | @param AssertionLevel Ignored if LevelTriggered is FALSE.\r | |
7367cc6c | 920 | TRUE specifies a level triggered interrupt that active\r |
5f867ad0 | 921 | when the interrupt line is asserted.\r |
7367cc6c | 922 | FALSE specifies a level triggered interrupt that active\r |
5f867ad0 | 923 | when the interrupt line is deasserted.\r |
924 | \r | |
925 | @return 64-bit data value used to send an MSI to the Local APIC.\r | |
926 | **/\r | |
927 | UINT64\r | |
7367cc6c | 928 | EFIAPI\r |
5f867ad0 | 929 | GetApicMsiValue (\r |
930 | IN UINT8 Vector,\r | |
931 | IN UINTN DeliveryMode,\r | |
932 | IN BOOLEAN LevelTriggered,\r | |
933 | IN BOOLEAN AssertionLevel\r | |
934 | )\r | |
935 | {\r | |
936 | LOCAL_APIC_MSI_DATA MsiData;\r | |
937 | \r | |
938 | ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r | |
939 | ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r | |
7367cc6c | 940 | \r |
5f867ad0 | 941 | MsiData.Uint64 = 0;\r |
942 | MsiData.Bits.Vector = Vector;\r | |
943 | MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r | |
944 | if (LevelTriggered) {\r | |
945 | MsiData.Bits.TriggerMode = 1;\r | |
946 | if (AssertionLevel) {\r | |
947 | MsiData.Bits.Level = 1;\r | |
948 | }\r | |
949 | }\r | |
053e878b | 950 | \r |
5f867ad0 | 951 | return MsiData.Uint64;\r |
952 | }\r | |
73152f19 LD |
953 | \r |
954 | /**\r | |
955 | Get Package ID/Core ID/Thread ID of a processor.\r | |
956 | \r | |
957 | The algorithm assumes the target system has symmetry across physical\r | |
958 | package boundaries with respect to the number of logical processors\r | |
959 | per package, number of cores per package.\r | |
960 | \r | |
961 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
962 | @param[out] Package Returns the processor package ID.\r | |
963 | @param[out] Core Returns the processor core ID.\r | |
964 | @param[out] Thread Returns the processor thread ID.\r | |
965 | **/\r | |
966 | VOID\r | |
1c8ca9a0 | 967 | EFIAPI\r |
262128e5 | 968 | GetProcessorLocationByApicId (\r |
73152f19 LD |
969 | IN UINT32 InitialApicId,\r |
970 | OUT UINT32 *Package OPTIONAL,\r | |
971 | OUT UINT32 *Core OPTIONAL,\r | |
972 | OUT UINT32 *Thread OPTIONAL\r | |
973 | )\r | |
974 | {\r | |
061ead7a LD |
975 | BOOLEAN TopologyLeafSupported;\r |
976 | CPUID_VERSION_INFO_EBX VersionInfoEbx;\r | |
977 | CPUID_VERSION_INFO_EDX VersionInfoEdx;\r | |
978 | CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r | |
979 | CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r | |
980 | CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r | |
981 | CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r | |
982 | CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r | |
983 | CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r | |
061ead7a LD |
984 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r |
985 | UINT32 MaxStandardCpuIdIndex;\r | |
986 | UINT32 MaxExtendedCpuIdIndex;\r | |
987 | UINT32 SubIndex;\r | |
988 | UINTN LevelType;\r | |
989 | UINT32 MaxLogicProcessorsPerPackage;\r | |
990 | UINT32 MaxCoresPerPackage;\r | |
061ead7a LD |
991 | UINTN ThreadBits;\r |
992 | UINTN CoreBits;\r | |
73152f19 LD |
993 | \r |
994 | //\r | |
995 | // Check if the processor is capable of supporting more than one logical processor.\r | |
996 | //\r | |
ae66c6f1 | 997 | AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r |
73152f19 LD |
998 | if (VersionInfoEdx.Bits.HTT == 0) {\r |
999 | if (Thread != NULL) {\r | |
061ead7a | 1000 | *Thread = 0;\r |
73152f19 | 1001 | }\r |
053e878b | 1002 | \r |
73152f19 | 1003 | if (Core != NULL) {\r |
061ead7a | 1004 | *Core = 0;\r |
73152f19 | 1005 | }\r |
053e878b | 1006 | \r |
73152f19 LD |
1007 | if (Package != NULL) {\r |
1008 | *Package = 0;\r | |
1009 | }\r | |
053e878b | 1010 | \r |
73152f19 LD |
1011 | return;\r |
1012 | }\r | |
1013 | \r | |
061ead7a LD |
1014 | //\r |
1015 | // Assume three-level mapping of APIC ID: Package|Core|Thread.\r | |
1016 | //\r | |
73152f19 | 1017 | ThreadBits = 0;\r |
053e878b | 1018 | CoreBits = 0;\r |
73152f19 LD |
1019 | \r |
1020 | //\r | |
061ead7a | 1021 | // Get max index of CPUID\r |
73152f19 | 1022 | //\r |
ae66c6f1 LD |
1023 | AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r |
1024 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r | |
73152f19 LD |
1025 | \r |
1026 | //\r | |
1027 | // If the extended topology enumeration leaf is available, it\r | |
1028 | // is the preferred mechanism for enumerating topology.\r | |
1029 | //\r | |
061ead7a LD |
1030 | TopologyLeafSupported = FALSE;\r |
1031 | if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
053e878b | 1032 | AsmCpuidEx (\r |
73152f19 LD |
1033 | CPUID_EXTENDED_TOPOLOGY,\r |
1034 | 0,\r | |
1035 | &ExtendedTopologyEax.Uint32,\r | |
1036 | &ExtendedTopologyEbx.Uint32,\r | |
1037 | &ExtendedTopologyEcx.Uint32,\r | |
1038 | NULL\r | |
1039 | );\r | |
1040 | //\r | |
1041 | // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r | |
1042 | // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r | |
1043 | // supported on that processor.\r | |
1044 | //\r | |
1045 | if (ExtendedTopologyEbx.Uint32 != 0) {\r | |
1046 | TopologyLeafSupported = TRUE;\r | |
1047 | \r | |
1048 | //\r | |
1049 | // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r | |
1050 | // the SMT sub-field of x2APIC ID.\r | |
1051 | //\r | |
1052 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
ae66c6f1 | 1053 | ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r |
73152f19 LD |
1054 | ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r |
1055 | \r | |
1056 | //\r | |
1057 | // Software must not assume any "level type" encoding\r | |
1058 | // value to be related to any sub-leaf index, except sub-leaf 0.\r | |
1059 | //\r | |
1060 | SubIndex = 1;\r | |
1061 | do {\r | |
ae66c6f1 | 1062 | AsmCpuidEx (\r |
73152f19 LD |
1063 | CPUID_EXTENDED_TOPOLOGY,\r |
1064 | SubIndex,\r | |
1065 | &ExtendedTopologyEax.Uint32,\r | |
1066 | NULL,\r | |
1067 | &ExtendedTopologyEcx.Uint32,\r | |
1068 | NULL\r | |
1069 | );\r | |
1070 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
1071 | if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r | |
1072 | CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r | |
1073 | break;\r | |
1074 | }\r | |
053e878b | 1075 | \r |
73152f19 LD |
1076 | SubIndex++;\r |
1077 | } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r | |
1078 | }\r | |
1079 | }\r | |
1080 | \r | |
1081 | if (!TopologyLeafSupported) {\r | |
061ead7a LD |
1082 | //\r |
1083 | // Get logical processor count\r | |
1084 | //\r | |
ae66c6f1 | 1085 | AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r |
73152f19 | 1086 | MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r |
061ead7a LD |
1087 | \r |
1088 | //\r | |
1089 | // Assume single-core processor\r | |
1090 | //\r | |
1091 | MaxCoresPerPackage = 1;\r | |
1092 | \r | |
1093 | //\r | |
1094 | // Check for topology extensions on AMD processor\r | |
1095 | //\r | |
053e878b | 1096 | if (StandardSignatureIsAuthenticAMD ()) {\r |
061ead7a | 1097 | if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r |
ae66c6f1 | 1098 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r |
061ead7a | 1099 | if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r |
061ead7a | 1100 | //\r |
ae66c6f1 | 1101 | // Account for max possible thread count to decode ApicId\r |
061ead7a | 1102 | //\r |
ae66c6f1 LD |
1103 | AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r |
1104 | MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r | |
061ead7a LD |
1105 | \r |
1106 | //\r | |
ae66c6f1 | 1107 | // Get cores per processor package\r |
061ead7a | 1108 | //\r |
ae66c6f1 LD |
1109 | AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r |
1110 | MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r | |
061ead7a LD |
1111 | }\r |
1112 | }\r | |
053e878b | 1113 | } else {\r |
73152f19 | 1114 | //\r |
061ead7a | 1115 | // Extract core count based on CACHE information\r |
73152f19 | 1116 | //\r |
061ead7a | 1117 | if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r |
ae66c6f1 | 1118 | AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r |
061ead7a LD |
1119 | if (CacheParamsEax.Uint32 != 0) {\r |
1120 | MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r | |
1121 | }\r | |
1122 | }\r | |
73152f19 LD |
1123 | }\r |
1124 | \r | |
053e878b MK |
1125 | ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r |
1126 | CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r | |
061ead7a | 1127 | }\r |
73152f19 LD |
1128 | \r |
1129 | if (Thread != NULL) {\r | |
061ead7a | 1130 | *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r |
73152f19 | 1131 | }\r |
053e878b | 1132 | \r |
73152f19 | 1133 | if (Core != NULL) {\r |
061ead7a | 1134 | *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r |
73152f19 | 1135 | }\r |
053e878b | 1136 | \r |
73152f19 LD |
1137 | if (Package != NULL) {\r |
1138 | *Package = (InitialApicId >> (ThreadBits + CoreBits));\r | |
1139 | }\r | |
1140 | }\r | |
7f33d4f2 RN |
1141 | \r |
1142 | /**\r | |
1143 | Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.\r | |
1144 | \r | |
1145 | The algorithm assumes the target system has symmetry across physical\r | |
1146 | package boundaries with respect to the number of threads per core, number of\r | |
1147 | cores per module, number of modules per tile, number of tiles per die, number\r | |
1148 | of dies per package.\r | |
1149 | \r | |
1150 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
1151 | @param[out] Package Returns the processor package ID.\r | |
1152 | @param[out] Die Returns the processor die ID.\r | |
1153 | @param[out] Tile Returns the processor tile ID.\r | |
1154 | @param[out] Module Returns the processor module ID.\r | |
1155 | @param[out] Core Returns the processor core ID.\r | |
1156 | @param[out] Thread Returns the processor thread ID.\r | |
1157 | **/\r | |
1158 | VOID\r | |
1159 | EFIAPI\r | |
1160 | GetProcessorLocation2ByApicId (\r | |
1161 | IN UINT32 InitialApicId,\r | |
1162 | OUT UINT32 *Package OPTIONAL,\r | |
1163 | OUT UINT32 *Die OPTIONAL,\r | |
1164 | OUT UINT32 *Tile OPTIONAL,\r | |
1165 | OUT UINT32 *Module OPTIONAL,\r | |
1166 | OUT UINT32 *Core OPTIONAL,\r | |
1167 | OUT UINT32 *Thread OPTIONAL\r | |
1168 | )\r | |
1169 | {\r | |
053e878b MK |
1170 | CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r |
1171 | CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r | |
1172 | UINT32 MaxStandardCpuIdIndex;\r | |
1173 | UINT32 Index;\r | |
1174 | UINTN LevelType;\r | |
1175 | UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r | |
1176 | UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r | |
7f33d4f2 RN |
1177 | \r |
1178 | for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r | |
1179 | Bits[LevelType] = 0;\r | |
1180 | }\r | |
1181 | \r | |
1182 | //\r | |
1183 | // Get max index of CPUID\r | |
1184 | //\r | |
1185 | AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r | |
1186 | if (MaxStandardCpuIdIndex < CPUID_V2_EXTENDED_TOPOLOGY) {\r | |
1187 | if (Die != NULL) {\r | |
1188 | *Die = 0;\r | |
1189 | }\r | |
053e878b | 1190 | \r |
7f33d4f2 RN |
1191 | if (Tile != NULL) {\r |
1192 | *Tile = 0;\r | |
1193 | }\r | |
053e878b | 1194 | \r |
7f33d4f2 RN |
1195 | if (Module != NULL) {\r |
1196 | *Module = 0;\r | |
1197 | }\r | |
053e878b | 1198 | \r |
7f33d4f2 RN |
1199 | GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);\r |
1200 | return;\r | |
1201 | }\r | |
1202 | \r | |
1203 | //\r | |
1204 | // If the V2 extended topology enumeration leaf is available, it\r | |
1205 | // is the preferred mechanism for enumerating topology.\r | |
1206 | //\r | |
1207 | for (Index = 0; ; Index++) {\r | |
053e878b | 1208 | AsmCpuidEx (\r |
7f33d4f2 RN |
1209 | CPUID_V2_EXTENDED_TOPOLOGY,\r |
1210 | Index,\r | |
1211 | &ExtendedTopologyEax.Uint32,\r | |
1212 | NULL,\r | |
1213 | &ExtendedTopologyEcx.Uint32,\r | |
1214 | NULL\r | |
1215 | );\r | |
1216 | \r | |
1217 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
1218 | \r | |
1219 | //\r | |
1220 | // first level reported should be SMT.\r | |
1221 | //\r | |
1222 | ASSERT ((Index != 0) || (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT));\r | |
1223 | if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r | |
1224 | break;\r | |
1225 | }\r | |
053e878b | 1226 | \r |
7f33d4f2 RN |
1227 | ASSERT (LevelType < ARRAY_SIZE (Bits));\r |
1228 | Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;\r | |
1229 | }\r | |
1230 | \r | |
1231 | for (LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r | |
1232 | //\r | |
1233 | // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored\r | |
1234 | // and treated as an extension of the last known level (i.e., level-1 in this case).\r | |
1235 | //\r | |
1236 | if (Bits[LevelType] == 0) {\r | |
1237 | Bits[LevelType] = Bits[LevelType - 1];\r | |
1238 | }\r | |
1239 | }\r | |
1240 | \r | |
1241 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;\r | |
053e878b MK |
1242 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;\r |
1243 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;\r | |
1244 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;\r | |
1245 | Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;\r | |
1246 | Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;\r | |
7f33d4f2 RN |
1247 | \r |
1248 | Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;\r | |
1249 | \r | |
1250 | for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT\r | |
053e878b MK |
1251 | ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r |
1252 | ; LevelType++\r | |
1253 | )\r | |
1254 | {\r | |
7f33d4f2 RN |
1255 | if (Location[LevelType] != NULL) {\r |
1256 | //\r | |
1257 | // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique\r | |
1258 | // topology ID of the next level type.\r | |
1259 | //\r | |
1260 | *Location[LevelType] = InitialApicId >> Bits[LevelType - 1];\r | |
1261 | \r | |
1262 | //\r | |
1263 | // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.\r | |
1264 | //\r | |
1265 | *Location[LevelType] &= (1 << (Bits[LevelType] - Bits[LevelType - 1])) - 1;\r | |
1266 | }\r | |
1267 | }\r | |
1268 | }\r |