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80c4b236 JF |
1 | /** @file\r |
2 | AESNI feature.\r | |
3 | \r | |
34b162d0 | 4 | Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
80c4b236 JF |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include "CpuCommonFeatures.h"\r | |
10 | \r | |
11 | /**\r | |
12 | Prepares for the data used by CPU feature detection and initialization.\r | |
13 | \r | |
14 | @param[in] NumberOfProcessors The number of CPUs in the platform.\r | |
15 | \r | |
16 | @return Pointer to a buffer of CPU related configuration data.\r | |
17 | \r | |
18 | @note This service could be called by BSP only.\r | |
19 | **/\r | |
20 | VOID *\r | |
21 | EFIAPI\r | |
22 | AesniGetConfigData (\r | |
23 | IN UINTN NumberOfProcessors\r | |
24 | )\r | |
25 | {\r | |
053e878b | 26 | UINT64 *ConfigData;\r |
80c4b236 JF |
27 | \r |
28 | ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);\r | |
29 | ASSERT (ConfigData != NULL);\r | |
30 | return ConfigData;\r | |
31 | }\r | |
32 | \r | |
33 | /**\r | |
34 | Detects if AESNI feature supported on current processor.\r | |
35 | \r | |
36 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
37 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
38 | structure for the CPU executing this function.\r | |
39 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
40 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
41 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
42 | RegisterCpuFeature().\r | |
43 | \r | |
44 | @retval TRUE AESNI feature is supported.\r | |
45 | @retval FALSE AESNI feature is not supported.\r | |
46 | \r | |
47 | @note This service could be called by BSP/APs.\r | |
48 | **/\r | |
49 | BOOLEAN\r | |
50 | EFIAPI\r | |
51 | AesniSupport (\r | |
52 | IN UINTN ProcessorNumber,\r | |
53 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
54 | IN VOID *ConfigData OPTIONAL\r | |
55 | )\r | |
56 | {\r | |
053e878b | 57 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;\r |
80c4b236 | 58 | \r |
9d02c34f | 59 | if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {\r |
053e878b | 60 | MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;\r |
41ac2076 SZ |
61 | ASSERT (MsrFeatureConfig != NULL);\r |
62 | MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);\r | |
9d02c34f | 63 | return TRUE;\r |
80c4b236 | 64 | }\r |
053e878b | 65 | \r |
80c4b236 JF |
66 | return FALSE;\r |
67 | }\r | |
68 | \r | |
69 | /**\r | |
70 | Initializes AESNI feature to specific state.\r | |
71 | \r | |
72 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
73 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
74 | structure for the CPU executing this function.\r | |
75 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
76 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
77 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
78 | RegisterCpuFeature().\r | |
79 | @param[in] State If TRUE, then the AESNI feature must be enabled.\r | |
80 | If FALSE, then the AESNI feature must be disabled.\r | |
81 | \r | |
82 | @retval RETURN_SUCCESS AESNI feature is initialized.\r | |
83 | \r | |
84 | @note This service could be called by BSP only.\r | |
85 | **/\r | |
86 | RETURN_STATUS\r | |
87 | EFIAPI\r | |
88 | AesniInitialize (\r | |
89 | IN UINTN ProcessorNumber,\r | |
90 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
4ec586b9 | 91 | IN VOID *ConfigData OPTIONAL,\r |
80c4b236 JF |
92 | IN BOOLEAN State\r |
93 | )\r | |
94 | {\r | |
053e878b | 95 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;\r |
80c4b236 JF |
96 | \r |
97 | //\r | |
98 | // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,\r | |
99 | // Simply use MSR_SANDY_BRIDGE_FEATURE_CONFIG here\r | |
100 | //\r | |
101 | // The scope of the MSR_SANDY_BRIDGE_FEATURE_CONFIG is Core, only program MSR_FEATURE_CONFIG for thread 0\r | |
102 | // of each core. Otherwise, once a thread in the core disabled AES, the other thread will cause GP when\r | |
103 | // programming it.\r | |
104 | //\r | |
105 | if (CpuInfo->ProcessorInfo.Location.Thread == 0) {\r | |
053e878b | 106 | MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;\r |
3dcb5325 | 107 | ASSERT (MsrFeatureConfig != NULL);\r |
80c4b236 JF |
108 | if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {\r |
109 | CPU_REGISTER_TABLE_WRITE_FIELD (\r | |
110 | ProcessorNumber,\r | |
111 | Msr,\r | |
112 | MSR_SANDY_BRIDGE_FEATURE_CONFIG,\r | |
113 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER,\r | |
114 | Bits.AESConfiguration,\r | |
34b162d0 | 115 | BIT0 | ((State) ? 0 : BIT1)\r |
80c4b236 JF |
116 | );\r |
117 | }\r | |
118 | }\r | |
053e878b | 119 | \r |
80c4b236 JF |
120 | return RETURN_SUCCESS;\r |
121 | }\r |