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2fba7d4e | 1 | ;------------------------------------------------------------------------------ ;\r |
facf52ae | 2 | ; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>\r |
2fba7d4e RN |
3 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4 | ;\r | |
5 | ; Module Name:\r | |
6 | ;\r | |
7 | ; MpEqu.inc\r | |
8 | ;\r | |
9 | ; Abstract:\r | |
10 | ;\r | |
11 | ; This is the equates file for Multiple Processor support\r | |
12 | ;\r | |
13 | ;-------------------------------------------------------------------------------\r | |
14 | %include "Nasm.inc"\r | |
15 | \r | |
2fba7d4e RN |
16 | CPU_SWITCH_STATE_IDLE equ 0\r |
17 | CPU_SWITCH_STATE_STORED equ 1\r | |
18 | CPU_SWITCH_STATE_LOADED equ 2\r | |
19 | \r | |
20 | ;\r | |
21 | ; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP\r | |
22 | ;\r | |
23 | struc MP_ASSEMBLY_ADDRESS_MAP\r | |
facf52ae XY |
24 | .RendezvousFunnelAddress CTYPE_UINTN 1\r |
25 | .ModeEntryOffset CTYPE_UINTN 1\r | |
26 | .RendezvousFunnelSize CTYPE_UINTN 1\r | |
27 | .RelocateApLoopFuncAddressGeneric CTYPE_UINTN 1\r | |
28 | .RelocateApLoopFuncSizeGeneric CTYPE_UINTN 1\r | |
0d1ad06c YX |
29 | .RelocateApLoopFuncAddressAmdSev CTYPE_UINTN 1\r |
30 | .RelocateApLoopFuncSizeAmdSev CTYPE_UINTN 1\r | |
facf52ae XY |
31 | .ModeTransitionOffset CTYPE_UINTN 1\r |
32 | .SwitchToRealNoNxOffset CTYPE_UINTN 1\r | |
33 | .SwitchToRealPM16ModeOffset CTYPE_UINTN 1\r | |
34 | .SwitchToRealPM16ModeSize CTYPE_UINTN 1\r | |
2fba7d4e RN |
35 | endstruc\r |
36 | \r | |
37 | ;\r | |
38 | ; Equivalent NASM structure of IA32_DESCRIPTOR\r | |
39 | ;\r | |
40 | struc IA32_DESCRIPTOR\r | |
41 | .Limit CTYPE_UINT16 1\r | |
42 | .Base CTYPE_UINTN 1\r | |
43 | endstruc\r | |
44 | \r | |
45 | ;\r | |
46 | ; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO\r | |
47 | ;\r | |
48 | struc CPU_EXCHANGE_ROLE_INFO\r | |
49 | ; State is defined as UINT8 in C header file\r | |
50 | ; Define it as UINTN here to guarantee the fields that follow State\r | |
51 | ; is naturally aligned. The structure layout doesn't change.\r | |
52 | .State CTYPE_UINTN 1\r | |
53 | .StackPointer CTYPE_UINTN 1\r | |
54 | .Gdtr CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
55 | .Idtr CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
56 | endstruc\r | |
57 | \r | |
58 | ;\r | |
59 | ; Equivalent NASM structure of CPU_INFO_IN_HOB\r | |
60 | ;\r | |
61 | struc CPU_INFO_IN_HOB\r | |
62 | .InitialApicId CTYPE_UINT32 1\r | |
63 | .ApicId CTYPE_UINT32 1\r | |
64 | .Health CTYPE_UINT32 1\r | |
65 | .ApTopOfStack CTYPE_UINT64 1\r | |
66 | endstruc\r | |
67 | \r | |
68 | ;\r | |
69 | ; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO\r | |
70 | ;\r | |
71 | struc MP_CPU_EXCHANGE_INFO\r | |
2fba7d4e RN |
72 | .StackStart: CTYPE_UINTN 1\r |
73 | .StackSize: CTYPE_UINTN 1\r | |
74 | .CFunction: CTYPE_UINTN 1\r | |
75 | .GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
76 | .IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
77 | .BufferStart: CTYPE_UINTN 1\r | |
78 | .ModeOffset: CTYPE_UINTN 1\r | |
79 | .ApIndex: CTYPE_UINTN 1\r | |
80 | .CodeSegment: CTYPE_UINTN 1\r | |
81 | .DataSegment: CTYPE_UINTN 1\r | |
82 | .EnableExecuteDisable: CTYPE_UINTN 1\r | |
83 | .Cr3: CTYPE_UINTN 1\r | |
84 | .InitFlag: CTYPE_UINTN 1\r | |
85 | .CpuInfo: CTYPE_UINTN 1\r | |
86 | .NumApsExecuting: CTYPE_UINTN 1\r | |
87 | .CpuMpData: CTYPE_UINTN 1\r | |
88 | .InitializeFloatingPointUnits: CTYPE_UINTN 1\r | |
89 | .ModeTransitionMemory: CTYPE_UINT32 1\r | |
90 | .ModeTransitionSegment: CTYPE_UINT16 1\r | |
91 | .ModeHighMemory: CTYPE_UINT32 1\r | |
92 | .ModeHighSegment: CTYPE_UINT16 1\r | |
93 | .Enable5LevelPaging: CTYPE_BOOLEAN 1\r | |
94 | .SevEsIsEnabled: CTYPE_BOOLEAN 1\r | |
9c703bc0 | 95 | .SevSnpIsEnabled CTYPE_BOOLEAN 1\r |
2fba7d4e | 96 | .GhcbBase: CTYPE_UINTN 1\r |
d4d7c9ad | 97 | .ExtTopoAvail: CTYPE_BOOLEAN 1\r |
2fba7d4e RN |
98 | endstruc\r |
99 | \r | |
283ab943 | 100 | MP_CPU_EXCHANGE_INFO_OFFSET equ (Flat32Start - RendezvousFunnelProcStart)\r |
2fba7d4e | 101 | %define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO. %+ Field)\r |