UefiCpuPkg/Library/MpInitLib/MpEqu.inc

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
   3 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   4 ;
   5 ; Module Name:
   6 ;
   7 ;   MpEqu.inc
   8 ;
   9 ; Abstract:
  10 ;
  11 ;   This is the equates file for Multiple Processor support
  12 ;
  13 ;-------------------------------------------------------------------------------
  14 %include "Nasm.inc"
  15
  16 CPU_SWITCH_STATE_IDLE         equ        0
  17 CPU_SWITCH_STATE_STORED       equ        1
  18 CPU_SWITCH_STATE_LOADED       equ        2
  19
  20 ;
  21 ; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP
  22 ;
  23 struc MP_ASSEMBLY_ADDRESS_MAP
  24   .RendezvousFunnelAddress       CTYPE_UINTN 1
  25   .ModeEntryOffset               CTYPE_UINTN 1
  26   .RendezvousFunnelSize          CTYPE_UINTN 1
  27   .RelocateApLoopFuncAddress     CTYPE_UINTN 1
  28   .RelocateApLoopFuncSize        CTYPE_UINTN 1
  29   .ModeTransitionOffset          CTYPE_UINTN 1
  30   .SwitchToRealNoNxOffset        CTYPE_UINTN 1
  31   .SwitchToRealPM16ModeOffset    CTYPE_UINTN 1
  32   .SwitchToRealPM16ModeSize      CTYPE_UINTN 1
  33 endstruc
  34
  35 ;
  36 ; Equivalent NASM structure of IA32_DESCRIPTOR
  37 ;
  38 struc IA32_DESCRIPTOR
  39   .Limit                         CTYPE_UINT16 1
  40   .Base                          CTYPE_UINTN  1
  41 endstruc
  42
  43 ;
  44 ; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO
  45 ;
  46 struc CPU_EXCHANGE_ROLE_INFO
  47   ; State is defined as UINT8 in C header file
  48   ; Define it as UINTN here to guarantee the fields that follow State
  49   ; is naturally aligned. The structure layout doesn't change.
  50   .State                         CTYPE_UINTN 1
  51   .StackPointer                  CTYPE_UINTN 1
  52   .Gdtr                          CTYPE_UINT8 IA32_DESCRIPTOR_size
  53   .Idtr                          CTYPE_UINT8 IA32_DESCRIPTOR_size
  54 endstruc
  55
  56 ;
  57 ; Equivalent NASM structure of CPU_INFO_IN_HOB
  58 ;
  59 struc CPU_INFO_IN_HOB
  60   .InitialApicId                 CTYPE_UINT32 1
  61   .ApicId                        CTYPE_UINT32 1
  62   .Health                        CTYPE_UINT32 1
  63   .ApTopOfStack                  CTYPE_UINT64 1
  64 endstruc
  65
  66 ;
  67 ; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO
  68 ;
  69 struc MP_CPU_EXCHANGE_INFO
  70   .StackStart:                   CTYPE_UINTN 1
  71   .StackSize:                    CTYPE_UINTN 1
  72   .CFunction:                    CTYPE_UINTN 1
  73   .GdtrProfile:                  CTYPE_UINT8 IA32_DESCRIPTOR_size
  74   .IdtrProfile:                  CTYPE_UINT8 IA32_DESCRIPTOR_size
  75   .BufferStart:                  CTYPE_UINTN 1
  76   .ModeOffset:                   CTYPE_UINTN 1
  77   .ApIndex:                      CTYPE_UINTN 1
  78   .CodeSegment:                  CTYPE_UINTN 1
  79   .DataSegment:                  CTYPE_UINTN 1
  80   .EnableExecuteDisable:         CTYPE_UINTN 1
  81   .Cr3:                          CTYPE_UINTN 1
  82   .InitFlag:                     CTYPE_UINTN 1
  83   .CpuInfo:                      CTYPE_UINTN 1
  84   .NumApsExecuting:              CTYPE_UINTN 1
  85   .CpuMpData:                    CTYPE_UINTN 1
  86   .InitializeFloatingPointUnits: CTYPE_UINTN 1
  87   .ModeTransitionMemory:         CTYPE_UINT32 1
  88   .ModeTransitionSegment:        CTYPE_UINT16 1
  89   .ModeHighMemory:               CTYPE_UINT32 1
  90   .ModeHighSegment:              CTYPE_UINT16 1
  91   .Enable5LevelPaging:           CTYPE_BOOLEAN 1
  92   .SevEsIsEnabled:               CTYPE_BOOLEAN 1
  93   .SevSnpIsEnabled               CTYPE_BOOLEAN 1
  94   .GhcbBase:                     CTYPE_UINTN 1
  95   .ExtTopoAvail:                 CTYPE_BOOLEAN 1
  96 endstruc
  97
  98 MP_CPU_EXCHANGE_INFO_OFFSET equ (Flat32Start - RendezvousFunnelProcStart)
  99 %define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO. %+ Field)