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3e8ad6bd JF |
1 | /** @file\r |
2 | Common header file for MP Initialize Library.\r | |
3 | \r | |
08a475df | 4 | Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r |
4c0f6e34 LD |
5 | Copyright (c) 2020, AMD Inc. All rights reserved.<BR>\r |
6 | \r | |
0acd8697 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3e8ad6bd JF |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef _MP_LIB_H_\r | |
12 | #define _MP_LIB_H_\r | |
13 | \r | |
14 | #include <PiPei.h>\r | |
15 | \r | |
01acb06c | 16 | #include <Register/Intel/Cpuid.h>\r |
4c0f6e34 | 17 | #include <Register/Amd/Cpuid.h>\r |
01acb06c RN |
18 | #include <Register/Intel/Msr.h>\r |
19 | #include <Register/Intel/LocalApic.h>\r | |
20 | #include <Register/Intel/Microcode.h>\r | |
3e8ad6bd JF |
21 | \r |
22 | #include <Library/MpInitLib.h>\r | |
23 | #include <Library/BaseLib.h>\r | |
24 | #include <Library/BaseMemoryLib.h>\r | |
25 | #include <Library/MemoryAllocationLib.h>\r | |
26 | #include <Library/DebugLib.h>\r | |
27 | #include <Library/LocalApicLib.h>\r | |
28 | #include <Library/CpuLib.h>\r | |
29 | #include <Library/UefiCpuLib.h>\r | |
30 | #include <Library/TimerLib.h>\r | |
31 | #include <Library/SynchronizationLib.h>\r | |
32 | #include <Library/MtrrLib.h>\r | |
33 | #include <Library/HobLib.h>\r | |
d5339c04 | 34 | #include <Library/PcdLib.h>\r |
3e8ad6bd | 35 | \r |
348a34d9 HW |
36 | #include <Guid/MicrocodePatchHob.h>\r |
37 | \r | |
b8b04307 JF |
38 | #define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')\r |
39 | \r | |
93ca4c0f JF |
40 | #define CPU_INIT_MP_LIB_HOB_GUID \\r |
41 | { \\r | |
42 | 0x58eb6a19, 0x3699, 0x4c68, { 0xa8, 0x36, 0xda, 0xcd, 0x8e, 0xdc, 0xad, 0x4a } \\r | |
43 | }\r | |
44 | \r | |
41be0da5 JF |
45 | //\r |
46 | // The MP data for switch BSP\r | |
47 | //\r | |
48 | #define CPU_SWITCH_STATE_IDLE 0\r | |
49 | #define CPU_SWITCH_STATE_STORED 1\r | |
50 | #define CPU_SWITCH_STATE_LOADED 2\r | |
51 | \r | |
d786a172 HW |
52 | //\r |
53 | // Default maximum number of entries to store the microcode patches information\r | |
54 | //\r | |
55 | #define DEFAULT_MAX_MICROCODE_PATCH_NUM 8\r | |
56 | \r | |
57 | //\r | |
58 | // Data structure for microcode patch information\r | |
59 | //\r | |
60 | typedef struct {\r | |
61 | UINTN Address;\r | |
62 | UINTN Size;\r | |
d786a172 HW |
63 | } MICROCODE_PATCH_INFO;\r |
64 | \r | |
41be0da5 JF |
65 | //\r |
66 | // CPU exchange information for switch BSP\r | |
67 | //\r | |
68 | typedef struct {\r | |
69 | UINT8 State; // offset 0\r | |
70 | UINTN StackPointer; // offset 4 / 8\r | |
71 | IA32_DESCRIPTOR Gdtr; // offset 8 / 16\r | |
72 | IA32_DESCRIPTOR Idtr; // offset 14 / 26\r | |
73 | } CPU_EXCHANGE_ROLE_INFO;\r | |
74 | \r | |
9ebcf0f4 JF |
75 | //\r |
76 | // AP loop state when APs are in idle state\r | |
77 | // It's value is the same with PcdCpuApLoopMode\r | |
78 | //\r | |
79 | typedef enum {\r | |
80 | ApInHltLoop = 1,\r | |
81 | ApInMwaitLoop = 2,\r | |
82 | ApInRunLoop = 3\r | |
83 | } AP_LOOP_MODE;\r | |
84 | \r | |
e59f8f6b JF |
85 | //\r |
86 | // AP initialization state during APs wakeup\r | |
87 | //\r | |
88 | typedef enum {\r | |
89 | ApInitConfig = 1,\r | |
90 | ApInitReconfig = 2,\r | |
91 | ApInitDone = 3\r | |
92 | } AP_INIT_STATE;\r | |
93 | \r | |
03a1a925 JF |
94 | //\r |
95 | // AP state\r | |
96 | //\r | |
2a5997f8 ED |
97 | // The state transitions for an AP when it process a procedure are:\r |
98 | // Idle ----> Ready ----> Busy ----> Idle\r | |
99 | // [BSP] [AP] [AP]\r | |
100 | //\r | |
03a1a925 JF |
101 | typedef enum {\r |
102 | CpuStateIdle,\r | |
103 | CpuStateReady,\r | |
104 | CpuStateBusy,\r | |
e048ce88 | 105 | CpuStateFinished,\r |
03a1a925 JF |
106 | CpuStateDisabled\r |
107 | } CPU_STATE;\r | |
108 | \r | |
68cb9330 JF |
109 | //\r |
110 | // CPU volatile registers around INIT-SIPI-SIPI\r | |
111 | //\r | |
112 | typedef struct {\r | |
113 | UINTN Cr0;\r | |
114 | UINTN Cr3;\r | |
115 | UINTN Cr4;\r | |
116 | UINTN Dr0;\r | |
117 | UINTN Dr1;\r | |
118 | UINTN Dr2;\r | |
119 | UINTN Dr3;\r | |
120 | UINTN Dr6;\r | |
121 | UINTN Dr7;\r | |
e9415e48 JW |
122 | IA32_DESCRIPTOR Gdtr;\r |
123 | IA32_DESCRIPTOR Idtr;\r | |
124 | UINT16 Tr;\r | |
68cb9330 JF |
125 | } CPU_VOLATILE_REGISTERS;\r |
126 | \r | |
e59f8f6b JF |
127 | //\r |
128 | // AP related data\r | |
129 | //\r | |
130 | typedef struct {\r | |
131 | SPIN_LOCK ApLock;\r | |
132 | volatile UINT32 *StartupApSignal;\r | |
133 | volatile UINTN ApFunction;\r | |
134 | volatile UINTN ApFunctionArgument;\r | |
e59f8f6b | 135 | BOOLEAN CpuHealthy;\r |
03a1a925 | 136 | volatile CPU_STATE State;\r |
68cb9330 | 137 | CPU_VOLATILE_REGISTERS VolatileRegisters;\r |
e59f8f6b JF |
138 | BOOLEAN Waiting;\r |
139 | BOOLEAN *Finished;\r | |
140 | UINT64 ExpectedTime;\r | |
141 | UINT64 CurrentTime;\r | |
142 | UINT64 TotalTime;\r | |
143 | EFI_EVENT WaitEvent;\r | |
999463c8 HW |
144 | UINT32 ProcessorSignature;\r |
145 | UINT8 PlatformId;\r | |
e1ed5573 | 146 | UINT64 MicrocodeEntryAddr;\r |
e59f8f6b JF |
147 | } CPU_AP_DATA;\r |
148 | \r | |
149 | //\r | |
150 | // Basic CPU information saved in Guided HOB.\r | |
151 | // Because the contents will be shard between PEI and DXE,\r | |
152 | // we need to make sure the each fields offset same in different\r | |
153 | // architecture.\r | |
154 | //\r | |
dd3fa0cd | 155 | #pragma pack (1)\r |
e59f8f6b JF |
156 | typedef struct {\r |
157 | UINT32 InitialApicId;\r | |
158 | UINT32 ApicId;\r | |
159 | UINT32 Health;\r | |
dd3fa0cd | 160 | UINT64 ApTopOfStack;\r |
e59f8f6b | 161 | } CPU_INFO_IN_HOB;\r |
dd3fa0cd | 162 | #pragma pack ()\r |
e59f8f6b | 163 | \r |
f7f85d83 JF |
164 | //\r |
165 | // AP reset code information including code address and size,\r | |
166 | // this structure will be shared be C code and assembly code.\r | |
167 | // It is natural aligned by design.\r | |
168 | //\r | |
169 | typedef struct {\r | |
170 | UINT8 *RendezvousFunnelAddress;\r | |
171 | UINTN ModeEntryOffset;\r | |
172 | UINTN RendezvousFunnelSize;\r | |
173 | UINT8 *RelocateApLoopFuncAddress;\r | |
174 | UINTN RelocateApLoopFuncSize;\r | |
f32bfe6d | 175 | UINTN ModeTransitionOffset;\r |
7b7508ad TL |
176 | UINTN SwitchToRealSize;\r |
177 | UINTN SwitchToRealOffset;\r | |
178 | UINTN SwitchToRealNoNxOffset;\r | |
179 | UINTN SwitchToRealPM16ModeOffset;\r | |
180 | UINTN SwitchToRealPM16ModeSize;\r | |
f7f85d83 | 181 | } MP_ASSEMBLY_ADDRESS_MAP;\r |
3e8ad6bd | 182 | \r |
e59f8f6b JF |
183 | typedef struct _CPU_MP_DATA CPU_MP_DATA;\r |
184 | \r | |
d94e5f67 JF |
185 | #pragma pack(1)\r |
186 | \r | |
187 | //\r | |
188 | // MP CPU exchange information for AP reset code\r | |
189 | // This structure is required to be packed because fixed field offsets\r | |
190 | // into this structure are used in assembly code in this module\r | |
191 | //\r | |
192 | typedef struct {\r | |
193 | UINTN Lock;\r | |
194 | UINTN StackStart;\r | |
195 | UINTN StackSize;\r | |
196 | UINTN CFunction;\r | |
197 | IA32_DESCRIPTOR GdtrProfile;\r | |
198 | IA32_DESCRIPTOR IdtrProfile;\r | |
199 | UINTN BufferStart;\r | |
200 | UINTN ModeOffset;\r | |
37676b9f | 201 | UINTN ApIndex;\r |
d94e5f67 JF |
202 | UINTN CodeSegment;\r |
203 | UINTN DataSegment;\r | |
5c66d125 | 204 | UINTN EnableExecuteDisable;\r |
d94e5f67 | 205 | UINTN Cr3;\r |
46d4b885 JF |
206 | UINTN InitFlag;\r |
207 | CPU_INFO_IN_HOB *CpuInfo;\r | |
0594ec41 | 208 | UINTN NumApsExecuting;\r |
e59f8f6b | 209 | CPU_MP_DATA *CpuMpData;\r |
3b2928b4 | 210 | UINTN InitializeFloatingPointUnitsAddress;\r |
f32bfe6d JW |
211 | UINT32 ModeTransitionMemory;\r |
212 | UINT16 ModeTransitionSegment;\r | |
213 | UINT32 ModeHighMemory;\r | |
214 | UINT16 ModeHighSegment;\r | |
09f69a87 RN |
215 | //\r |
216 | // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.\r | |
217 | //\r | |
218 | BOOLEAN Enable5LevelPaging;\r | |
7b7508ad TL |
219 | BOOLEAN SevEsIsEnabled;\r |
220 | UINTN GhcbBase;\r | |
d94e5f67 JF |
221 | } MP_CPU_EXCHANGE_INFO;\r |
222 | \r | |
223 | #pragma pack()\r | |
e59f8f6b JF |
224 | \r |
225 | //\r | |
226 | // CPU MP Data save in memory\r | |
227 | //\r | |
228 | struct _CPU_MP_DATA {\r | |
229 | UINT64 CpuInfoInHob;\r | |
230 | UINT32 CpuCount;\r | |
231 | UINT32 BspNumber;\r | |
232 | //\r | |
233 | // The above fields data will be passed from PEI to DXE\r | |
234 | // Please make sure the fields offset same in the different\r | |
235 | // architecture.\r | |
236 | //\r | |
237 | SPIN_LOCK MpLock;\r | |
238 | UINTN Buffer;\r | |
239 | UINTN CpuApStackSize;\r | |
240 | MP_ASSEMBLY_ADDRESS_MAP AddressMap;\r | |
241 | UINTN WakeupBuffer;\r | |
66833b2a | 242 | UINTN WakeupBufferHigh;\r |
e59f8f6b JF |
243 | UINTN BackupBuffer;\r |
244 | UINTN BackupBufferSize;\r | |
e59f8f6b | 245 | \r |
e59f8f6b | 246 | volatile UINT32 FinishedCount;\r |
2da3e96c | 247 | UINT32 RunningCount;\r |
e59f8f6b JF |
248 | BOOLEAN SingleThread;\r |
249 | EFI_AP_PROCEDURE Procedure;\r | |
250 | VOID *ProcArguments;\r | |
251 | BOOLEAN *Finished;\r | |
252 | UINT64 ExpectedTime;\r | |
253 | UINT64 CurrentTime;\r | |
254 | UINT64 TotalTime;\r | |
255 | EFI_EVENT WaitEvent;\r | |
256 | UINTN **FailedCpuList;\r | |
257 | \r | |
258 | AP_INIT_STATE InitFlag;\r | |
41be0da5 | 259 | BOOLEAN SwitchBspFlag;\r |
b3775af2 | 260 | UINTN NewBspNumber;\r |
41be0da5 JF |
261 | CPU_EXCHANGE_ROLE_INFO BSPInfo;\r |
262 | CPU_EXCHANGE_ROLE_INFO APInfo;\r | |
e59f8f6b JF |
263 | MTRR_SETTINGS MtrrTable;\r |
264 | UINT8 ApLoopMode;\r | |
265 | UINT8 ApTargetCState;\r | |
266 | UINT16 PmCodeSegment;\r | |
7b7508ad | 267 | UINT16 Pm16CodeSegment;\r |
e59f8f6b JF |
268 | CPU_AP_DATA *CpuData;\r |
269 | volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo;\r | |
ffab2442 JF |
270 | \r |
271 | UINT32 CurrentTimerCount;\r | |
272 | UINTN DivideValue;\r | |
273 | UINT8 Vector;\r | |
274 | BOOLEAN PeriodicMode;\r | |
275 | BOOLEAN TimerInterruptState;\r | |
d148a178 HW |
276 | UINT64 MicrocodePatchAddress;\r |
277 | UINT64 MicrocodePatchRegionSize;\r | |
2a089134 | 278 | \r |
58942277 ED |
279 | //\r |
280 | // Whether need to use Init-Sipi-Sipi to wake up the APs.\r | |
281 | // Two cases need to set this value to TRUE. One is in HLT\r | |
282 | // loop mode, the other is resume from S3 which loop mode\r | |
e23d9c3e | 283 | // will be hardcode change to HLT mode by PiSmmCpuDxeSmm\r |
58942277 ED |
284 | // driver.\r |
285 | //\r | |
286 | BOOLEAN WakeUpByInitSipiSipi;\r | |
e88a5b98 TL |
287 | \r |
288 | BOOLEAN SevEsIsEnabled;\r | |
7b7508ad TL |
289 | UINTN SevEsAPBuffer;\r |
290 | UINTN SevEsAPResetStackStart;\r | |
291 | CPU_MP_DATA *NewCpuMpData;\r | |
292 | \r | |
293 | UINT64 GhcbBase;\r | |
e59f8f6b | 294 | };\r |
93ca4c0f | 295 | \r |
7b7508ad TL |
296 | #define AP_RESET_STACK_SIZE 64\r |
297 | \r | |
298 | #pragma pack(1)\r | |
299 | \r | |
300 | typedef struct {\r | |
301 | UINT8 InsnBuffer[8];\r | |
302 | UINT16 Rip;\r | |
303 | UINT16 Segment;\r | |
304 | } SEV_ES_AP_JMP_FAR;\r | |
305 | \r | |
306 | #pragma pack()\r | |
307 | \r | |
308 | /**\r | |
309 | Assembly code to move an AP from long mode to real mode.\r | |
310 | \r | |
311 | Move an AP from long mode to real mode in preparation to invoking\r | |
312 | the reset vector. This is used for SEV-ES guests where a hypervisor\r | |
313 | is not allowed to set the CS and RIP to point to the reset vector.\r | |
314 | \r | |
315 | @param[in] BufferStart The reset vector target.\r | |
316 | @param[in] Code16 16-bit protected mode code segment value.\r | |
317 | @param[in] Code32 32-bit protected mode code segment value.\r | |
318 | @param[in] StackStart The start of a stack to be used for transitioning\r | |
319 | from long mode to real mode.\r | |
320 | **/\r | |
321 | typedef\r | |
322 | VOID\r | |
323 | (EFIAPI AP_RESET) (\r | |
324 | IN UINTN BufferStart,\r | |
325 | IN UINT16 Code16,\r | |
326 | IN UINT16 Code32,\r | |
327 | IN UINTN StackStart\r | |
328 | );\r | |
329 | \r | |
93ca4c0f JF |
330 | extern EFI_GUID mCpuInitMpLibHobGuid;\r |
331 | \r | |
76157021 JF |
332 | /**\r |
333 | Assembly code to place AP into safe loop mode.\r | |
334 | \r | |
335 | Place AP into targeted C-State if MONITOR is supported, otherwise\r | |
336 | place AP into hlt state.\r | |
337 | Place AP in protected mode if the current is long mode. Due to AP maybe\r | |
338 | wakeup by some hardware event. It could avoid accessing page table that\r | |
339 | may not available during booting to OS.\r | |
340 | \r | |
341 | @param[in] MwaitSupport TRUE indicates MONITOR is supported.\r | |
342 | FALSE indicates MONITOR is not supported.\r | |
343 | @param[in] ApTargetCState Target C-State value.\r | |
344 | @param[in] PmCodeSegment Protected mode code segment value.\r | |
345 | **/\r | |
346 | typedef\r | |
347 | VOID\r | |
348 | (EFIAPI * ASM_RELOCATE_AP_LOOP) (\r | |
349 | IN BOOLEAN MwaitSupport,\r | |
350 | IN UINTN ApTargetCState,\r | |
bf2786dc | 351 | IN UINTN PmCodeSegment,\r |
9f91cb01 JF |
352 | IN UINTN TopOfApStack,\r |
353 | IN UINTN NumberToFinish\r | |
76157021 | 354 | );\r |
f7f85d83 JF |
355 | \r |
356 | /**\r | |
357 | Assembly code to get starting address and size of the rendezvous entry for APs.\r | |
358 | Information for fixing a jump instruction in the code is also returned.\r | |
359 | \r | |
360 | @param[out] AddressMap Output buffer for address map information.\r | |
361 | **/\r | |
362 | VOID\r | |
363 | EFIAPI\r | |
364 | AsmGetAddressMap (\r | |
365 | OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap\r | |
366 | );\r | |
367 | \r | |
41be0da5 JF |
368 | /**\r |
369 | This function is called by both the BSP and the AP which is to become the BSP to\r | |
370 | Exchange execution context including stack between them. After return from this\r | |
371 | function, the BSP becomes AP and the AP becomes the BSP.\r | |
372 | \r | |
373 | @param[in] MyInfo Pointer to buffer holding the exchanging information for the executing processor.\r | |
374 | @param[in] OthersInfo Pointer to buffer holding the exchanging information for the peer.\r | |
375 | \r | |
376 | **/\r | |
377 | VOID\r | |
378 | EFIAPI\r | |
379 | AsmExchangeRole (\r | |
380 | IN CPU_EXCHANGE_ROLE_INFO *MyInfo,\r | |
381 | IN CPU_EXCHANGE_ROLE_INFO *OthersInfo\r | |
382 | );\r | |
383 | \r | |
93ca4c0f JF |
384 | /**\r |
385 | Get the pointer to CPU MP Data structure.\r | |
386 | \r | |
387 | @return The pointer to CPU MP Data structure.\r | |
388 | **/\r | |
389 | CPU_MP_DATA *\r | |
390 | GetCpuMpData (\r | |
391 | VOID\r | |
392 | );\r | |
393 | \r | |
394 | /**\r | |
395 | Save the pointer to CPU MP Data structure.\r | |
396 | \r | |
397 | @param[in] CpuMpData The pointer to CPU MP Data structure will be saved.\r | |
398 | **/\r | |
399 | VOID\r | |
400 | SaveCpuMpData (\r | |
401 | IN CPU_MP_DATA *CpuMpData\r | |
402 | );\r | |
403 | \r | |
ed66e0e3 JF |
404 | \r |
405 | /**\r | |
a6b3d753 | 406 | Get available system memory below 1MB by specified size.\r |
ed66e0e3 | 407 | \r |
a6b3d753 SZ |
408 | @param[in] WakeupBufferSize Wakeup buffer size required\r |
409 | \r | |
410 | @retval other Return wakeup buffer address below 1MB.\r | |
411 | @retval -1 Cannot find free memory below 1MB.\r | |
ed66e0e3 | 412 | **/\r |
a6b3d753 SZ |
413 | UINTN\r |
414 | GetWakeupBuffer (\r | |
415 | IN UINTN WakeupBufferSize\r | |
ed66e0e3 JF |
416 | );\r |
417 | \r | |
f32bfe6d JW |
418 | /**\r |
419 | Get available EfiBootServicesCode memory below 4GB by specified size.\r | |
420 | \r | |
421 | This buffer is required to safely transfer AP from real address mode to\r | |
422 | protected mode or long mode, due to the fact that the buffer returned by\r | |
423 | GetWakeupBuffer() may be marked as non-executable.\r | |
424 | \r | |
425 | @param[in] BufferSize Wakeup transition buffer size.\r | |
426 | \r | |
427 | @retval other Return wakeup transition buffer address below 4GB.\r | |
428 | @retval 0 Cannot find free memory below 4GB.\r | |
429 | **/\r | |
430 | UINTN\r | |
431 | GetModeTransitionBuffer (\r | |
432 | IN UINTN BufferSize\r | |
433 | );\r | |
434 | \r | |
7b7508ad TL |
435 | /**\r |
436 | Return the address of the SEV-ES AP jump table.\r | |
437 | \r | |
438 | This buffer is required in order for an SEV-ES guest to transition from\r | |
439 | UEFI into an OS.\r | |
440 | \r | |
441 | @return Return SEV-ES AP jump table buffer\r | |
442 | **/\r | |
443 | UINTN\r | |
444 | GetSevEsAPMemory (\r | |
445 | VOID\r | |
446 | );\r | |
447 | \r | |
96f5920d JF |
448 | /**\r |
449 | This function will be called by BSP to wakeup AP.\r | |
450 | \r | |
451 | @param[in] CpuMpData Pointer to CPU MP Data\r | |
452 | @param[in] Broadcast TRUE: Send broadcast IPI to all APs\r | |
453 | FALSE: Send IPI to AP by ApicId\r | |
454 | @param[in] ProcessorNumber The handle number of specified processor\r | |
455 | @param[in] Procedure The function to be invoked by AP\r | |
456 | @param[in] ProcedureArgument The argument to be passed into AP function\r | |
cf4e79e4 | 457 | @param[in] WakeUpDisabledAps Whether need to wake up disabled APs in broadcast mode.\r |
96f5920d JF |
458 | **/\r |
459 | VOID\r | |
460 | WakeUpAP (\r | |
461 | IN CPU_MP_DATA *CpuMpData,\r | |
462 | IN BOOLEAN Broadcast,\r | |
463 | IN UINTN ProcessorNumber,\r | |
464 | IN EFI_AP_PROCEDURE Procedure, OPTIONAL\r | |
cf4e79e4 ED |
465 | IN VOID *ProcedureArgument, OPTIONAL\r |
466 | IN BOOLEAN WakeUpDisabledAps OPTIONAL\r | |
96f5920d JF |
467 | );\r |
468 | \r | |
93ca4c0f JF |
469 | /**\r |
470 | Initialize global data for MP support.\r | |
471 | \r | |
472 | @param[in] CpuMpData The pointer to CPU MP Data structure.\r | |
473 | **/\r | |
474 | VOID\r | |
475 | InitMpGlobalData (\r | |
476 | IN CPU_MP_DATA *CpuMpData\r | |
477 | );\r | |
478 | \r | |
86efe976 JF |
479 | /**\r |
480 | Worker function to execute a caller provided function on all enabled APs.\r | |
481 | \r | |
482 | @param[in] Procedure A pointer to the function to be run on\r | |
483 | enabled APs of the system.\r | |
484 | @param[in] SingleThread If TRUE, then all the enabled APs execute\r | |
485 | the function specified by Procedure one by\r | |
486 | one, in ascending order of processor handle\r | |
487 | number. If FALSE, then all the enabled APs\r | |
488 | execute the function specified by Procedure\r | |
489 | simultaneously.\r | |
ee0c39fa | 490 | @param[in] ExcludeBsp Whether let BSP also trig this task.\r |
86efe976 JF |
491 | @param[in] WaitEvent The event created by the caller with CreateEvent()\r |
492 | service.\r | |
367284e7 | 493 | @param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for\r |
86efe976 JF |
494 | APs to return from Procedure, either for\r |
495 | blocking or non-blocking mode.\r | |
496 | @param[in] ProcedureArgument The parameter passed into Procedure for\r | |
497 | all APs.\r | |
498 | @param[out] FailedCpuList If all APs finish successfully, then its\r | |
499 | content is set to NULL. If not all APs\r | |
500 | finish before timeout expires, then its\r | |
501 | content is set to address of the buffer\r | |
502 | holding handle numbers of the failed APs.\r | |
503 | \r | |
504 | @retval EFI_SUCCESS In blocking mode, all APs have finished before\r | |
505 | the timeout expired.\r | |
506 | @retval EFI_SUCCESS In non-blocking mode, function has been dispatched\r | |
507 | to all enabled APs.\r | |
508 | @retval others Failed to Startup all APs.\r | |
509 | \r | |
510 | **/\r | |
511 | EFI_STATUS\r | |
ee0c39fa | 512 | StartupAllCPUsWorker (\r |
86efe976 JF |
513 | IN EFI_AP_PROCEDURE Procedure,\r |
514 | IN BOOLEAN SingleThread,\r | |
ee0c39fa | 515 | IN BOOLEAN ExcludeBsp,\r |
86efe976 JF |
516 | IN EFI_EVENT WaitEvent OPTIONAL,\r |
517 | IN UINTN TimeoutInMicroseconds,\r | |
518 | IN VOID *ProcedureArgument OPTIONAL,\r | |
519 | OUT UINTN **FailedCpuList OPTIONAL\r | |
520 | );\r | |
521 | \r | |
20ae5774 JF |
522 | /**\r |
523 | Worker function to let the caller get one enabled AP to execute a caller-provided\r | |
524 | function.\r | |
525 | \r | |
526 | @param[in] Procedure A pointer to the function to be run on\r | |
527 | enabled APs of the system.\r | |
528 | @param[in] ProcessorNumber The handle number of the AP.\r | |
529 | @param[in] WaitEvent The event created by the caller with CreateEvent()\r | |
530 | service.\r | |
367284e7 | 531 | @param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for\r |
20ae5774 JF |
532 | APs to return from Procedure, either for\r |
533 | blocking or non-blocking mode.\r | |
534 | @param[in] ProcedureArgument The parameter passed into Procedure for\r | |
535 | all APs.\r | |
536 | @param[out] Finished If AP returns from Procedure before the\r | |
537 | timeout expires, its content is set to TRUE.\r | |
538 | Otherwise, the value is set to FALSE.\r | |
539 | \r | |
540 | @retval EFI_SUCCESS In blocking mode, specified AP finished before\r | |
541 | the timeout expires.\r | |
542 | @retval others Failed to Startup AP.\r | |
543 | \r | |
544 | **/\r | |
545 | EFI_STATUS\r | |
546 | StartupThisAPWorker (\r | |
547 | IN EFI_AP_PROCEDURE Procedure,\r | |
548 | IN UINTN ProcessorNumber,\r | |
549 | IN EFI_EVENT WaitEvent OPTIONAL,\r | |
550 | IN UINTN TimeoutInMicroseconds,\r | |
551 | IN VOID *ProcedureArgument OPTIONAL,\r | |
552 | OUT BOOLEAN *Finished OPTIONAL\r | |
553 | );\r | |
554 | \r | |
41be0da5 JF |
555 | /**\r |
556 | Worker function to switch the requested AP to be the BSP from that point onward.\r | |
557 | \r | |
558 | @param[in] ProcessorNumber The handle number of AP that is to become the new BSP.\r | |
559 | @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an\r | |
560 | enabled AP. Otherwise, it will be disabled.\r | |
561 | \r | |
562 | @retval EFI_SUCCESS BSP successfully switched.\r | |
7367cc6c | 563 | @retval others Failed to switch BSP.\r |
41be0da5 JF |
564 | \r |
565 | **/\r | |
566 | EFI_STATUS\r | |
567 | SwitchBSPWorker (\r | |
568 | IN UINTN ProcessorNumber,\r | |
569 | IN BOOLEAN EnableOldBSP\r | |
570 | );\r | |
571 | \r | |
e37109bc JF |
572 | /**\r |
573 | Worker function to let the caller enable or disable an AP from this point onward.\r | |
574 | This service may only be called from the BSP.\r | |
575 | \r | |
576 | @param[in] ProcessorNumber The handle number of AP.\r | |
577 | @param[in] EnableAP Specifies the new state for the processor for\r | |
578 | enabled, FALSE for disabled.\r | |
579 | @param[in] HealthFlag If not NULL, a pointer to a value that specifies\r | |
580 | the new health status of the AP.\r | |
581 | \r | |
582 | @retval EFI_SUCCESS The specified AP was enabled or disabled successfully.\r | |
583 | @retval others Failed to Enable/Disable AP.\r | |
584 | \r | |
585 | **/\r | |
586 | EFI_STATUS\r | |
587 | EnableDisableApWorker (\r | |
588 | IN UINTN ProcessorNumber,\r | |
589 | IN BOOLEAN EnableAP,\r | |
590 | IN UINT32 *HealthFlag OPTIONAL\r | |
591 | );\r | |
592 | \r | |
93ca4c0f JF |
593 | /**\r |
594 | Get pointer to CPU MP Data structure from GUIDed HOB.\r | |
595 | \r | |
596 | @return The pointer to CPU MP Data structure.\r | |
597 | **/\r | |
598 | CPU_MP_DATA *\r | |
599 | GetCpuMpDataFromGuidedHob (\r | |
600 | VOID\r | |
601 | );\r | |
08085f08 JF |
602 | \r |
603 | /** Checks status of specified AP.\r | |
604 | \r | |
605 | This function checks whether the specified AP has finished the task assigned\r | |
606 | by StartupThisAP(), and whether timeout expires.\r | |
607 | \r | |
608 | @param[in] ProcessorNumber The handle number of processor.\r | |
609 | \r | |
610 | @retval EFI_SUCCESS Specified AP has finished task assigned by StartupThisAPs().\r | |
611 | @retval EFI_TIMEOUT The timeout expires.\r | |
612 | @retval EFI_NOT_READY Specified AP has not finished task and timeout has not expired.\r | |
613 | **/\r | |
614 | EFI_STATUS\r | |
615 | CheckThisAP (\r | |
616 | IN UINTN ProcessorNumber\r | |
617 | );\r | |
618 | \r | |
619 | /**\r | |
620 | Checks status of all APs.\r | |
621 | \r | |
622 | This function checks whether all APs have finished task assigned by StartupAllAPs(),\r | |
623 | and whether timeout expires.\r | |
624 | \r | |
625 | @retval EFI_SUCCESS All APs have finished task assigned by StartupAllAPs().\r | |
626 | @retval EFI_TIMEOUT The timeout expires.\r | |
627 | @retval EFI_NOT_READY APs have not finished task and timeout has not expired.\r | |
628 | **/\r | |
629 | EFI_STATUS\r | |
630 | CheckAllAPs (\r | |
631 | VOID\r | |
632 | );\r | |
633 | \r | |
634 | /**\r | |
635 | Checks APs status and updates APs status if needed.\r | |
636 | \r | |
637 | **/\r | |
638 | VOID\r | |
639 | CheckAndUpdateApsStatus (\r | |
640 | VOID\r | |
641 | );\r | |
642 | \r | |
94f63c76 JF |
643 | /**\r |
644 | Detect whether specified processor can find matching microcode patch and load it.\r | |
645 | \r | |
e1ed5573 HW |
646 | @param[in] CpuMpData The pointer to CPU MP Data structure.\r |
647 | @param[in] ProcessorNumber The handle number of the processor. The range is\r | |
648 | from 0 to the total number of logical processors\r | |
649 | minus 1.\r | |
94f63c76 JF |
650 | **/\r |
651 | VOID\r | |
652 | MicrocodeDetect (\r | |
2a089134 | 653 | IN CPU_MP_DATA *CpuMpData,\r |
e1ed5573 | 654 | IN UINTN ProcessorNumber\r |
94f63c76 JF |
655 | );\r |
656 | \r | |
d786a172 | 657 | /**\r |
dd017041 | 658 | Shadow the required microcode patches data into memory.\r |
d786a172 HW |
659 | \r |
660 | @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r | |
661 | **/\r | |
662 | VOID\r | |
dd017041 | 663 | ShadowMicrocodeUpdatePatch (\r |
d786a172 HW |
664 | IN OUT CPU_MP_DATA *CpuMpData\r |
665 | );\r | |
666 | \r | |
348a34d9 HW |
667 | /**\r |
668 | Get the cached microcode patch base address and size from the microcode patch\r | |
669 | information cache HOB.\r | |
670 | \r | |
671 | @param[out] Address Base address of the microcode patches data.\r | |
672 | It will be updated if the microcode patch\r | |
673 | information cache HOB is found.\r | |
674 | @param[out] RegionSize Size of the microcode patches data.\r | |
675 | It will be updated if the microcode patch\r | |
676 | information cache HOB is found.\r | |
677 | \r | |
678 | @retval TRUE The microcode patch information cache HOB is found.\r | |
679 | @retval FALSE The microcode patch information cache HOB is not found.\r | |
680 | \r | |
681 | **/\r | |
682 | BOOLEAN\r | |
683 | GetMicrocodePatchInfoFromHob (\r | |
684 | UINT64 *Address,\r | |
685 | UINT64 *RegionSize\r | |
686 | );\r | |
687 | \r | |
4d3314f6 JF |
688 | /**\r |
689 | Detect whether Mwait-monitor feature is supported.\r | |
690 | \r | |
691 | @retval TRUE Mwait-monitor feature is supported.\r | |
692 | @retval FALSE Mwait-monitor feature is not supported.\r | |
693 | **/\r | |
694 | BOOLEAN\r | |
695 | IsMwaitSupport (\r | |
696 | VOID\r | |
697 | );\r | |
698 | \r | |
43c9fdcc JF |
699 | /**\r |
700 | Enable Debug Agent to support source debugging on AP function.\r | |
701 | \r | |
702 | **/\r | |
703 | VOID\r | |
704 | EnableDebugAgent (\r | |
705 | VOID\r | |
706 | );\r | |
707 | \r | |
e1ed5573 HW |
708 | /**\r |
709 | Find the current Processor number by APIC ID.\r | |
710 | \r | |
711 | @param[in] CpuMpData Pointer to PEI CPU MP Data\r | |
712 | @param[out] ProcessorNumber Return the pocessor number found\r | |
713 | \r | |
714 | @retval EFI_SUCCESS ProcessorNumber is found and returned.\r | |
715 | @retval EFI_NOT_FOUND ProcessorNumber is not found.\r | |
716 | **/\r | |
717 | EFI_STATUS\r | |
718 | GetProcessorNumber (\r | |
719 | IN CPU_MP_DATA *CpuMpData,\r | |
720 | OUT UINTN *ProcessorNumber\r | |
721 | );\r | |
722 | \r | |
c788c2b1 SF |
723 | /**\r |
724 | This funtion will try to invoke platform specific microcode shadow logic to\r | |
725 | relocate microcode update patches into memory.\r | |
726 | \r | |
4ac82ea1 | 727 | @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r |
c788c2b1 SF |
728 | \r |
729 | @retval EFI_SUCCESS Shadow microcode success.\r | |
730 | @retval EFI_OUT_OF_RESOURCES No enough resource to complete the operation.\r | |
731 | @retval EFI_UNSUPPORTED Can't find platform specific microcode shadow\r | |
732 | PPI/Protocol.\r | |
733 | **/\r | |
734 | EFI_STATUS\r | |
735 | PlatformShadowMicrocode (\r | |
736 | IN OUT CPU_MP_DATA *CpuMpData\r | |
737 | );\r | |
738 | \r | |
3e8ad6bd JF |
739 | #endif\r |
740 | \r |