[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / CPU / PowerManagement / AcpiTables / Ssdt / Cpu0Ist.asl

/*-----------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
\r
 Intel Silvermont Processor Power Management BIOS Reference Code\r
\r
 Copyright (c) 2006 - 2014, Intel Corporation\r
\r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
 Filename:    CPU0IST.ASL\r
\r
 Revision:    Refer to Readme\r
\r
 Date:        Refer to Readme\r
\r
--------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
 This Processor Power Management BIOS Source Code is furnished under license\r
 and may only be used or copied in accordance with the terms of the license.\r
 The information in this document is furnished for informational use only, is\r
 subject to change without notice, and should not be construed as a commitment\r
 by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
 for any errors or inaccuracies that may appear in this document or any\r
 software that may be provided in association with this document.\r
\r
 Except as permitted by such license, no part of this document may be\r
 reproduced, stored in a retrieval system, or transmitted in any form or by\r
 any means without the express written consent of Intel Corporation.\r
\r
 WARNING: You are authorized and licensed to install and use this BIOS code\r
 ONLY on an IST PC. This utility may damage any system that does not\r
 meet these requirements.\r
\r
    An IST PC is a computer which\r
    (1) Is capable of seamlessly and automatically transitioning among\r
    multiple performance states (potentially operating at different\r
    efficiency ratings) based upon power source changes, END user\r
    preference, processor performance demand, and thermal conditions; and\r
    (2) Includes an Intel Pentium II processors, Intel Pentium III\r
    processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
    Processor-M, Intel Pentium M Processor, or any other future Intel\r
    processors that incorporates the capability to transition between\r
    different performance states by altering some, or any combination of,\r
    the following processor attributes: core voltage, core frequency, bus\r
    frequency, number of processor cores available, or any other attribute\r
    that changes the efficiency (instructions/unit time-power) at which the\r
    processor operates.\r
\r
-------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
NOTES:\r
    (1) <TODO> - IF the trap range and port definitions do not match those\r
    specified by this reference code, this file must be modified IAW the\r
    individual implmentation.\r
\r
--------------------------------------------------------------------------------\r
------------------------------------------------------------------------------*/\r
\r
\r
DefinitionBlock (\r
    "CPU0IST.aml",\r
    "SSDT",\r
    0x01,\r
    "PmRef",\r
    "Cpu0Ist",\r
    0x3000\r
    )\r
{\r
    External (\_PR.CPU0, DeviceObj)\r
    External (PDC0)\r
    External (CFGD)\r
\r
    Scope(\_PR.CPU0)\r
    {\r
        //OperationRegion (DEB0, SystemIO, 0x80, 1)    //DBG\r
        //Field (DEB0, ByteAcc,NoLock,Preserve)        //DBG\r
        //{ DBG8, 8,}                                  //DBG\r
\r
        Name(_PPC, 0)        // Initialize as All States Available.\r
\r
        // NOTE:  For CMP systems; this table is not loaded unless\r
        //      the required driver support is present.\r
        //      So, we do not check for those cases here.\r
        //\r
        //   CFGD[0] = GV3 Capable/Enabled\r
        //   PDCx[0]  = OS Capable of Hardware P-State control\r
        //\r
        Method(_PCT,0)\r
        {\r
            If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))\r
            {\r
                //Store(0xA0,DBG8) //DBG\r
                Return(Package()    // Native Mode\r
                {\r
                    ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},\r
                    ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}\r
                })\r
            }\r
            // @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT\r
            // For all other cases, report control through the\r
            // SMI interface.  (The port used for SMM control is fixed up\r
            // by the initialization code.)\r
            //\r
            Return(Package()        // SMM Mode\r
            {\r
               ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},\r
               ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}\r
            })\r
        }\r
\r
\r
        // NOTE:  For CMP systems; this table is not loaded if MP\r
        //      driver support is not present or P-State are disabled.\r
        //\r
        Method(_PSS,0)\r
        {\r
            //\r
            // Report NSPP if:\r
            //   (1) GV3 capable (Not checked, see above.)\r
            //   (2) Driver support direct hardware control\r
            //   (3) MP driver support present (Not checked, see above.)\r
            // else;\r
            //   Report SPSS\r
            //\r
            //   PDCx[0]  = OS Capable of Hardware P-State control\r
            //\r
            If(And(PDC0,0x0001)){\r
                //Store(0xB0,DBG8) //DBG\r
                Return(NPSS)\r
            }\r
            //Store(0xBF,DBG8) //DBG\r
            // Otherwise, report SMM mode\r
            //\r
            Return(SPSS)\r
\r
        }\r
\r
        Name(SPSS,Package()\r
        {\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
        })\r
\r
        Name(NPSS,Package()\r
        {\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
        })\r
\r
        // The _PSD object provides information to the OSPM related\r
        // to P-State coordination between processors in a multi-processor\r
        // configurations.\r
        //\r
        Method(_PSD,0)\r
        {\r
            //\r
            // IF CMP is supported/enabled\r
            //   IF quad core processor\r
            //     IF PDC[11]\r
            //         Report 4 processors and HW_ALL as the coordination type\r
            //     ELSE\r
            //         Report 4 processors and SW_ALL as the coordination type\r
            //   ELSE\r
            //     IF PDC[11]\r
            //         Report 2 processors and HW_ALL as the coordination type\r
            //     ELSE\r
            //         Report 2 processors and SW_ALL as the coordination type\r
            // ELSE\r
            //    Report 1 processor and SW_ALL as the coordination type\r
            //    (Domain 0)\r
            //\r
            //   CFGD[24] = Two or more cores enabled\r
            //   CFGD[23] = Four cores enabled\r
            //   PDCx[11] = Hardware coordination with hardware feedback\r
            //\r
\r
            If(And(CFGD,0x1000000))    // CMP Enabled.\r
            {\r
              If(And(CFGD,0x800000))    // 2 or 4 process.\r
                {\r
                  If(And(PDC0,0x0800))\r
                  {\r
                      Return(Package(){    // HW_ALL\r
                        Package(){\r
                            5,              // # entries.\r
                            0,              // Revision.\r
                            0,              // Domain #.\r
                            0xFE,           // Coord Type- HW_ALL.\r
                            4               // # processors.\r
                        }\r
                      })\r
                  } // If(And(PDC0,0x0800))\r
                   Return(Package(){        // SW_ALL\r
                     Package(){\r
                        5,                  // # entries.\r
                        0,                  // Revision.\r
                        0,                  // Domain #.\r
                        0xFC,               // Coord Type- SW_ALL.\r
                        4                   // # processors.\r
                     }\r
                    })\r
                } else {\r
                  Return(Package(){        // HW_ALL\r
                      Package(){\r
                          5,                  // # entries.\r
                          0,                  // Revision.\r
                          0,                  // Domain #.\r
                          0xFE,               // Coord Type- HW_ALL.\r
                          2                   // # processors.\r
                      }\r
                  })\r
                }\r
            }    // If(And(CFGD,0x1000000))    // CMP Enabled.\r
\r
            Return(Package(){              // SW_ALL\r
                Package(){\r
                    5,                        // # entries.\r
                    0,                        // Revision.\r
                    0,                        // Domain #.\r
                    0xFC,                     // Coord Type- SW_ALL.\r
                    1                         // # processors.\r
                }\r
            })\r
        } // Method(_PSD,0)\r
    } // Scope(\_PR.CPU0)\r
} // End of Definition Block\r
\r
\r
Commit	Line	Data
3cbfba02 DW	1	/*-----------------------------------------------------------------------------\r
	2	-------------------------------------------------------------------------------\r
	3	\r
	4	\r
	5	Intel Silvermont Processor Power Management BIOS Reference Code\r
	6	\r
	7	Copyright (c) 2006 - 2014, Intel Corporation\r
	8	\r
	9	This program and the accompanying materials are licensed and made available under\r
	10	the terms and conditions of the BSD License that accompanies this distribution.\r
	11	The full text of the license may be found at\r
	12	http://opensource.org/licenses/bsd-license.php.\r
	13	\r
	14	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	15	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	16	\r
	17	\r
	18	Filename: CPU0IST.ASL\r
	19	\r
	20	Revision: Refer to Readme\r
	21	\r
	22	Date: Refer to Readme\r
	23	\r
	24	--------------------------------------------------------------------------------\r
	25	-------------------------------------------------------------------------------\r
	26	\r
	27	This Processor Power Management BIOS Source Code is furnished under license\r
	28	and may only be used or copied in accordance with the terms of the license.\r
	29	The information in this document is furnished for informational use only, is\r
	30	subject to change without notice, and should not be construed as a commitment\r
	31	by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
	32	for any errors or inaccuracies that may appear in this document or any\r
	33	software that may be provided in association with this document.\r
	34	\r
	35	Except as permitted by such license, no part of this document may be\r
	36	reproduced, stored in a retrieval system, or transmitted in any form or by\r
	37	any means without the express written consent of Intel Corporation.\r
	38	\r
	39	WARNING: You are authorized and licensed to install and use this BIOS code\r
	40	ONLY on an IST PC. This utility may damage any system that does not\r
	41	meet these requirements.\r
	42	\r
	43	An IST PC is a computer which\r
	44	(1) Is capable of seamlessly and automatically transitioning among\r
	45	multiple performance states (potentially operating at different\r
	46	efficiency ratings) based upon power source changes, END user\r
	47	preference, processor performance demand, and thermal conditions; and\r
	48	(2) Includes an Intel Pentium II processors, Intel Pentium III\r
	49	processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
	50	Processor-M, Intel Pentium M Processor, or any other future Intel\r
	51	processors that incorporates the capability to transition between\r
	52	different performance states by altering some, or any combination of,\r
	53	the following processor attributes: core voltage, core frequency, bus\r
	54	frequency, number of processor cores available, or any other attribute\r
	55	that changes the efficiency (instructions/unit time-power) at which the\r
	56	processor operates.\r
	57	\r
	58	-------------------------------------------------------------------------------\r
	59	-------------------------------------------------------------------------------\r
	60	\r
	61	NOTES:\r
	62	(1) <TODO> - IF the trap range and port definitions do not match those\r
	63	specified by this reference code, this file must be modified IAW the\r
	64	individual implmentation.\r
65	\r
66	--------------------------------------------------------------------------------\r
67	------------------------------------------------------------------------------*/\r
68	\r
69	\r
70	DefinitionBlock (\r
71	"CPU0IST.aml",\r
72	"SSDT",\r
73	0x01,\r
74	"PmRef",\r
75	"Cpu0Ist",\r
76	0x3000\r
77	)\r
78	{\r
79	External (\_PR.CPU0, DeviceObj)\r
80	External (PDC0)\r
81	External (CFGD)\r
82	\r
83	Scope(\_PR.CPU0)\r
84	{\r
85	//OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG\r
86	//Field (DEB0, ByteAcc,NoLock,Preserve) //DBG\r
87	//{ DBG8, 8,} //DBG\r
88	\r
89	Name(_PPC, 0) // Initialize as All States Available.\r
90	\r
91	// NOTE: For CMP systems; this table is not loaded unless\r
92	// the required driver support is present.\r
93	// So, we do not check for those cases here.\r
94	//\r
95	// CFGD[0] = GV3 Capable/Enabled\r
96	// PDCx[0] = OS Capable of Hardware P-State control\r
97	//\r
98	Method(_PCT,0)\r
99	{\r
100	If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))\r
101	{\r
102	//Store(0xA0,DBG8) //DBG\r
103	Return(Package() // Native Mode\r
104	{\r
105	ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},\r
106	ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}\r
107	})\r
108	}\r
109	// @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT\r
110	// For all other cases, report control through the\r
111	// SMI interface. (The port used for SMM control is fixed up\r
112	// by the initialization code.)\r
113	//\r
114	Return(Package() // SMM Mode\r
115	{\r
116	ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},\r
117	ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}\r
118	})\r
119	}\r
120	\r
121	\r
122	// NOTE: For CMP systems; this table is not loaded if MP\r
123	// driver support is not present or P-State are disabled.\r
124	//\r
125	Method(_PSS,0)\r
126	{\r
127	//\r
128	// Report NSPP if:\r
129	// (1) GV3 capable (Not checked, see above.)\r
130	// (2) Driver support direct hardware control\r
131	// (3) MP driver support present (Not checked, see above.)\r
132	// else;\r
133	// Report SPSS\r
134	//\r
135	// PDCx[0] = OS Capable of Hardware P-State control\r
136	//\r
137	If(And(PDC0,0x0001)){\r
138	//Store(0xB0,DBG8) //DBG\r
139	Return(NPSS)\r
140	}\r
141	//Store(0xBF,DBG8) //DBG\r
142	// Otherwise, report SMM mode\r
143	//\r
144	Return(SPSS)\r
145	\r
146	}\r
147	\r
148	Name(SPSS,Package()\r
149	{\r
150	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
151	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
152	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
153	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
154	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
155	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
156	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
157	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
158	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
159	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
160	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
161	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
162	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
163	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
164	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
165	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
166	})\r
167	\r
168	Name(NPSS,Package()\r
169	{\r
170	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
171	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
172	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
173	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
174	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
175	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
176	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
177	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
178	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
179	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
180	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
181	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
182	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
183	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
184	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
185	Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
186	})\r
187	\r
188	// The _PSD object provides information to the OSPM related\r
189	// to P-State coordination between processors in a multi-processor\r
190	// configurations.\r
191	//\r
192	Method(_PSD,0)\r
193	{\r
194	//\r
195	// IF CMP is supported/enabled\r
196	// IF quad core processor\r
197	// IF PDC[11]\r
198	// Report 4 processors and HW_ALL as the coordination type\r
199	// ELSE\r
200	// Report 4 processors and SW_ALL as the coordination type\r
201	// ELSE\r
202	// IF PDC[11]\r
203	// Report 2 processors and HW_ALL as the coordination type\r
204	// ELSE\r
205	// Report 2 processors and SW_ALL as the coordination type\r
206	// ELSE\r
207	// Report 1 processor and SW_ALL as the coordination type\r
208	// (Domain 0)\r
209	//\r
210	// CFGD[24] = Two or more cores enabled\r
211	// CFGD[23] = Four cores enabled\r
212	// PDCx[11] = Hardware coordination with hardware feedback\r
213	//\r
214	\r
215	If(And(CFGD,0x1000000)) // CMP Enabled.\r
216	{\r
217	If(And(CFGD,0x800000)) // 2 or 4 process.\r
218	{\r
219	If(And(PDC0,0x0800))\r
220	{\r
221	Return(Package(){ // HW_ALL\r
222	Package(){\r
223	5, // # entries.\r
224	0, // Revision.\r
225	0, // Domain #.\r
226	0xFE, // Coord Type- HW_ALL.\r
227	4 // # processors.\r
228	}\r
229	})\r
230	} // If(And(PDC0,0x0800))\r
231	Return(Package(){ // SW_ALL\r
232	Package(){\r
233	5, // # entries.\r
234	0, // Revision.\r
235	0, // Domain #.\r
236	0xFC, // Coord Type- SW_ALL.\r
237	4 // # processors.\r
238	}\r
239	})\r
240	} else {\r
241	Return(Package(){ // HW_ALL\r
242	Package(){\r
243	5, // # entries.\r
244	0, // Revision.\r
245	0, // Domain #.\r
246	0xFE, // Coord Type- HW_ALL.\r
247	2 // # processors.\r
248	}\r
249	})\r
250	}\r
251	} // If(And(CFGD,0x1000000)) // CMP Enabled.\r
252	\r
253	Return(Package(){ // SW_ALL\r
254	Package(){\r
255	5, // # entries.\r
256	0, // Revision.\r
257	0, // Domain #.\r
258	0xFC, // Coord Type- SW_ALL.\r
259	1 // # processors.\r
260	}\r
261	})\r
262	} // Method(_PSD,0)\r
263	} // Scope(\_PR.CPU0)\r
264	} // End of Definition Block\r
265	\r
266	\r