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1/*++\r
2\r
3Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved\r
4\r
5 This program and the accompanying materials are licensed and made available under\r
6 the terms and conditions of the BSD License that accompanies this distribution.\r
7 The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php.\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13\r
14\r
15Module Name:\r
16\r
17 PchCommonDefinitions.h\r
18\r
19Abstract:\r
20\r
21 This header file provides common definitions for PCH\r
22\r
23--*/\r
24#ifndef _PCH_COMMON_DEFINITIONS_H_\r
25#define _PCH_COMMON_DEFINITIONS_H_\r
26\r
27//\r
28// MMIO access macros\r
29//\r
30#define PchMmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register))\r
31\r
32//\r
33// 32 bit MMIO access\r
34//\r
35#define PchMmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))\r
36\r
37#define PchMmio32(BaseAddr, Register) *PchMmio32Ptr (BaseAddr, Register)\r
38\r
39#define PchMmio32Or(BaseAddr, Register, OrData) \\r
40 PchMmio32 (BaseAddr, Register) = (UINT32) \\r
41 (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))\r
42\r
43#define PchMmio32And(BaseAddr, Register, AndData) \\r
44 PchMmio32 (BaseAddr, Register) = (UINT32) \\r
45 (PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))\r
46\r
47#define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \\r
48 PchMmio32 (BaseAddr, Register) = (UINT32) \\r
49 ((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
50\r
51//\r
52// 16 bit MMIO access\r
53//\r
54#define PchMmio16Ptr(BaseAddr, Register) ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register))\r
55\r
56#define PchMmio16(BaseAddr, Register) *PchMmio16Ptr (BaseAddr, Register)\r
57\r
58#define PchMmio16Or(BaseAddr, Register, OrData) \\r
59 PchMmio16 (BaseAddr, Register) = (UINT16) \\r
60 (PchMmio16 (BaseAddr, Register) | (UINT16) (OrData))\r
61\r
62#define PchMmio16And(BaseAddr, Register, AndData) \\r
63 PchMmio16 (BaseAddr, Register) = (UINT16) \\r
64 (PchMmio16 (BaseAddr, Register) & (UINT16) (AndData))\r
65\r
66#define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \\r
67 PchMmio16 (BaseAddr, Register) = (UINT16) \\r
68 ((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
69\r
70//\r
71// 8 bit MMIO access\r
72//\r
73#define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register))\r
74\r
75#define PchMmio8(BaseAddr, Register) *PchMmio8Ptr (BaseAddr, Register)\r
76\r
77#define PchMmio8Or(BaseAddr, Register, OrData) \\r
78 PchMmio8 (BaseAddr, Register) = (UINT8) \\r
79 (PchMmio8 (BaseAddr, Register) | (UINT8) (OrData))\r
80\r
81#define PchMmio8And(BaseAddr, Register, AndData) \\r
82 PchMmio8 (BaseAddr, Register) = (UINT8) \\r
83 (PchMmio8 (BaseAddr, Register) & (UINT8) (AndData))\r
84\r
85#define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \\r
86 PchMmio8 (BaseAddr, Register) = (UINT8) \\r
87 ((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
88\r
89//\r
90// Memory Mapped PCI Access macros\r
91//\r
92#define PCH_PCI_EXPRESS_BASE_ADDRESS 0xE0000000\r
93//\r
94// PCI Device MM Base\r
95//\r
96#define PchPciDeviceMmBase(Bus, Device, Function) \\r
97 ( \\r
98 (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \\r
99 (Function << 12) \\r
100 )\r
101\r
102//\r
103// PCI Device MM Address\r
104//\r
105#define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \\r
106 ( \\r
107 (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \\r
108 (Function << 12) + (UINTN) (Register) \\r
109 )\r
110\r
111//\r
112// 32 bit PCI access\r
113//\r
114#define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \\r
115 ((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
116\r
117#define PchMmPci32(Segment, Bus, Device, Function, Register) *PchMmPci32Ptr (Segment, Bus, Device, Function, Register)\r
118\r
119#define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \\r
120 PchMmPci32 ( \\r
121 Segment, \\r
122 Bus, \\r
123 Device, \\r
124 Function, \\r
125 Register \\r
126 ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))\r
127\r
128#define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \\r
129 PchMmPci32 ( \\r
130 Segment, \\r
131 Bus, \\r
132 Device, \\r
133 Function, \\r
134 Register \\r
135 ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))\r
136\r
137#define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
138 PchMmPci32 ( \\r
139 Segment, \\r
140 Bus, \\r
141 Device, \\r
142 Function, \\r
143 Register \\r
144 ) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
145\r
146//\r
147// 16 bit PCI access\r
148//\r
149#define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \\r
150 ((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
151\r
152#define PchMmPci16(Segment, Bus, Device, Function, Register) *PchMmPci16Ptr (Segment, Bus, Device, Function, Register)\r
153\r
154#define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \\r
155 PchMmPci16 ( \\r
156 Segment, \\r
157 Bus, \\r
158 Device, \\r
159 Function, \\r
160 Register \\r
161 ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))\r
162\r
163#define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \\r
164 PchMmPci16 ( \\r
165 Segment, \\r
166 Bus, \\r
167 Device, \\r
168 Function, \\r
169 Register \\r
170 ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))\r
171\r
172#define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
173 PchMmPci16 ( \\r
174 Segment, \\r
175 Bus, \\r
176 Device, \\r
177 Function, \\r
178 Register \\r
179 ) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
180\r
181//\r
182// 8 bit PCI access\r
183//\r
184#define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \\r
185 ((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
186\r
187#define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register)\r
188\r
189#define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \\r
190 PchMmPci8 ( \\r
191 Segment, \\r
192 Bus, \\r
193 Device, \\r
194 Function, \\r
195 Register \\r
196 ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))\r
197\r
198#define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \\r
199 PchMmPci8 ( \\r
200 Segment, \\r
201 Bus, \\r
202 Device, \\r
203 Function, \\r
204 Register \\r
205 ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))\r
206\r
207#define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
208 PchMmPci8 ( \\r
209 Segment, \\r
210 Bus, \\r
211 Device, \\r
212 Function, \\r
213 Register \\r
214 ) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
215\r
216#endif\r