[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchRegs / PchRegsSmbus.h

/**\r
\r
Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
\r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
\r
  @file\r
  PchRegsSmbus.h\r
\r
  @brief\r
  Register names for VLV Smbus Device.\r
\r
  Conventions:\r
\r
  - Prefixes:\r
    Definitions beginning with "R_" are registers\r
    Definitions beginning with "B_" are bits within registers\r
    Definitions beginning with "V_" are meaningful values of bits within the registers\r
    Definitions beginning with "S_" are register sizes\r
    Definitions beginning with "N_" are the bit position\r
  - In general, PCH registers are denoted by "_PCH_" in register names\r
  - Registers / bits that are different between PCH generations are denoted by\r
    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
    at the end of the register/bit names\r
  - Registers / bits of new devices introduced in a PCH generation will be just named\r
    as "_PCH_" without <generation_name> inserted.\r
\r
**/\r
#ifndef _PCH_REGS_SMBUS_H_\r
#define _PCH_REGS_SMBUS_H_\r
\r
///\r
/// SMBus Controller Registers (D31:F3)\r
///\r
#define PCI_DEVICE_NUMBER_PCH_SMBUS        31\r
#define PCI_FUNCTION_NUMBER_PCH_SMBUS      3\r
\r
#define R_PCH_SMBUS_VENDOR_ID              0x00  // Vendor ID\r
#define V_PCH_SMBUS_VENDOR_ID              V_PCH_INTEL_VENDOR_ID // Intel Vendor ID\r
\r
#define R_PCH_SMBUS_DEVICE_ID              0x02  // Device ID\r
#define V_PCH_SMBUS_DEVICE_ID              0x0F12\r
\r
#define R_PCH_SMBUS_PCICMD                 0x04  // CMD register enables/disables, Memory/IO space access and interrupt\r
#define B_PCH_SMBUS_PCICMD_INTR_DIS        BIT10 // Interrupt Disable\r
#define B_PCH_SMBUS_PCICMD_FBE             BIT9  // FBE - reserved as '0'\r
#define B_PCH_SMBUS_PCICMD_SERR_EN         BIT8  // SERR Enable - reserved as '0'\r
#define B_PCH_SMBUS_PCICMD_WCC             BIT7  // Wait Cycle Control - reserved as '0'\r
#define B_PCH_SMBUS_PCICMD_PER             BIT6  // Parity Error - reserved as '0'\r
#define B_PCH_SMBUS_PCICMD_VPS             BIT5  // VGA Palette Snoop - reserved as '0'\r
#define B_PCH_SMBUS_PCICMD_PMWE            BIT4  // Postable Memory Write Enable - reserved as '0'\r
#define B_PCH_SMBUS_PCICMD_SCE             BIT3  // Special Cycle Enable - reserved as '0'\r
#define B_PCH_SMBUS_PCICMD_BME             BIT2  // Bus Master Enable - reserved as '0'\r
#define B_PCH_SMBUS_PCICMD_MSE             BIT1  // Memory Space Enable\r
#define B_PCH_SMBUS_PCICMD_IOSE            BIT0  // I/O Space Enable\r
\r
#define R_PCH_SMBUS_BASE                   0x20  // The I/O memory bar\r
#define B_PCH_SMBUS_BASE_BAR               0x0000FFE0 // Base Address\r
#define B_PCH_SMBUS_BASE_IOSI              BIT0  // IO Space Indicator\r
\r
#define R_PCH_SMBUS_SVID                   0x2C  // Subsystem Vendor ID\r
#define B_PCH_SMBUS_SVID                   0xFFFF // Subsystem Vendor ID\r
\r
//\r
// SMBus I/O Registers\r
//\r
#define R_PCH_SMBUS_HSTS                   0x00  // Host Status Register R/W\r
#define B_PCH_SMBUS_HSTS_ALL               0xFF\r
#define B_PCH_SMBUS_BYTE_DONE_STS          BIT7  // Byte Done Status\r
#define B_PCH_SMBUS_IUS                    BIT6  // In Use Status\r
#define B_PCH_SMBUS_SMBALERT_STS           BIT5  // SMBUS Alert\r
#define B_PCH_SMBUS_FAIL                   BIT4  // Failed\r
#define B_PCH_SMBUS_BERR                   BIT3  // Bus Error\r
#define B_PCH_SMBUS_DERR                   BIT2  // Device Error\r
#define B_PCH_SMBUS_ERRORS                 (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)\r
#define B_PCH_SMBUS_INTR                   BIT1  // Interrupt\r
#define B_PCH_SMBUS_HBSY                   BIT0  // Host Busy\r
\r
#define R_PCH_SMBUS_HCTL                   0x02  // Host Control Register R/W\r
#define B_PCH_SMBUS_PEC_EN                 BIT7  // Packet Error Checking Enable\r
#define B_PCH_SMBUS_START                  BIT6  // Start\r
#define B_PCH_SMBUS_LAST_BYTE              BIT5  // Last Byte\r
#define B_PCH_SMBUS_SMB_CMD                0x1C  // SMB Command\r
#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS  0x1C  // Block Process\r
#define V_PCH_SMBUS_SMB_CMD_IIC_READ       0x18  // I2C Read\r
#define V_PCH_SMBUS_SMB_CMD_BLOCK          0x14  // Block\r
#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL   0x10  // Process Call\r
#define V_PCH_SMBUS_SMB_CMD_WORD_DATA      0x0C  // Word Data\r
#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA      0x08  // Byte Data\r
#define V_PCH_SMBUS_SMB_CMD_BYTE           0x04  // Byte\r
#define V_PCH_SMBUS_SMB_CMD_QUICK          0x00  // Quick\r
#define B_PCH_SMBUS_KILL                   BIT1  // Kill\r
#define B_PCH_SMBUS_INTREN                 BIT0  // Interrupt Enable\r
\r
#define R_PCH_SMBUS_HCMD                   0x03  // Host Command Register R/W\r
#define B_PCH_SMBUS_HCMD                   0xFF  // Command to be transmitted\r
\r
#define R_PCH_SMBUS_TSA                    0x04  // Transmit Slave Address Register R/W\r
#define B_PCH_SMBUS_ADDRESS                0xFE  // 7-bit address of the targeted slave\r
#define B_PCH_SMBUS_RW_SEL                 BIT0  // Direction of the host transfer, 1 = read, 0 = write\r
#define B_PCH_SMBUS_RW_SEL_READ            0x01  // Read\r
#define B_PCH_SMBUS_RW_SEL_WRITE           0x00  // Write\r
//\r
#define R_PCH_SMBUS_HD0                    0x05  // Data 0 Register R/W\r
#define R_PCH_SMBUS_HD1                    0x06  // Data 1 Register R/W\r
#define R_PCH_SMBUS_HBD                    0x07  // Host Block Data Register R/W\r
#define R_PCH_SMBUS_PEC                    0x08  // Packet Error Check Data Register R/W\r
\r
#define R_PCH_SMBUS_RSA                    0x09  // Receive Slave Address Register R/W\r
#define B_PCH_SMBUS_SLAVE_ADDR             0x7F  // TCO slave address (Not used, reserved)\r
\r
#define R_PCH_SMBUS_SD                     0x0A  // Receive Slave Data Register R/W\r
\r
#define R_PCH_SMBUS_AUXS                   0x0C  // Auxiliary Status Register R/WC\r
#define B_PCH_SMBUS_CRCE                   BIT0  // CRC Error\r
//\r
#define R_PCH_SMBUS_AUXC                   0x0D  // Auxiliary Control Register R/W\r
#define B_PCH_SMBUS_E32B                   BIT1  // Enable 32-byte Buffer\r
#define B_PCH_SMBUS_AAC                    BIT0  // Automatically Append CRC\r
\r
#define R_PCH_SMBUS_SMLC                   0x0E  // SMLINK Pin Control Register R/W\r
#define B_PCH_SMBUS_SMLINK_CLK_CTL         BIT2  // Not supported\r
#define B_PCH_SMBUS_SMLINK1_CUR_STS        BIT1  // Not supported\r
#define B_PCH_SMBUS_SMLINK0_CUR_STS        BIT0  // Not supported\r
\r
\r
#define R_PCH_SMBUS_SMBC                   0x0F  // SMBus Pin Control Register R/W\r
#define B_PCH_SMBUS_SMBCLK_CTL             BIT2  // SMBCLK Control\r
#define B_PCH_SMBUS_SMBDATA_CUR_STS        BIT1  // SMBDATA Current Status\r
#define B_PCH_SMBUS_SMBCLK_CUR_STS         BIT0  // SMBCLK Current Status\r
\r
#define R_PCH_SMBUS_SSTS                   0x10  // Slave Status Register R/WC\r
#define B_PCH_SMBUS_HOST_NOTIFY_STS        BIT0  // Host Notify Status\r
\r
#define R_PCH_SMBUS_SCMD                   0x11  // Slave Command Register R/W\r
#define B_PCH_SMBUS_SMBALERT_DIS           BIT2  // Not supported\r
#define B_PCH_SMBUS_HOST_NOTIFY_WKEN       BIT1  // Host Notify Wake Enable\r
#define B_PCH_SMBUS_HOST_NOTIFY_INTREN     BIT0  // Host Notify Interrupt Enable\r
\r
#define R_PCH_SMBUS_NDA                    0x14  // Notify Device Address Register RO\r
#define B_PCH_SMBUS_DEVICE_ADDRESS         0xFE  // Device Address\r
\r
#define R_PCH_SMBUS_NDLB                   0x16  // Notify Data Low Byte Register RO\r
#define R_PCH_SMBUS_NDHB                   0x17  // Notify Data High Byte Register RO\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	/**\r
	2	\r
	3	Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved\r
	4	\r
	5	This program and the accompanying materials are licensed and made available under\r
	6	the terms and conditions of the BSD License that accompanies this distribution.\r
	7	The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php.\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	\r
	14	\r
	15	@file\r
	16	PchRegsSmbus.h\r
	17	\r
	18	@brief\r
	19	Register names for VLV Smbus Device.\r
	20	\r
	21	Conventions:\r
	22	\r
	23	- Prefixes:\r
	24	Definitions beginning with "R_" are registers\r
	25	Definitions beginning with "B_" are bits within registers\r
	26	Definitions beginning with "V_" are meaningful values of bits within the registers\r
	27	Definitions beginning with "S_" are register sizes\r
	28	Definitions beginning with "N_" are the bit position\r
	29	- In general, PCH registers are denoted by "_PCH_" in register names\r
	30	- Registers / bits that are different between PCH generations are denoted by\r
	31	"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
	32	- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
	33	at the end of the register/bit names\r
	34	- Registers / bits of new devices introduced in a PCH generation will be just named\r
	35	as "_PCH_" without <generation_name> inserted.\r
	36	\r
	37	**/\r
	38	#ifndef _PCH_REGS_SMBUS_H_\r
	39	#define _PCH_REGS_SMBUS_H_\r
	40	\r
	41	///\r
	42	/// SMBus Controller Registers (D31:F3)\r
	43	///\r
	44	#define PCI_DEVICE_NUMBER_PCH_SMBUS 31\r
	45	#define PCI_FUNCTION_NUMBER_PCH_SMBUS 3\r
	46	\r
	47	#define R_PCH_SMBUS_VENDOR_ID 0x00 // Vendor ID\r
	48	#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID\r
	49	\r
	50	#define R_PCH_SMBUS_DEVICE_ID 0x02 // Device ID\r
	51	#define V_PCH_SMBUS_DEVICE_ID 0x0F12\r
	52	\r
	53	#define R_PCH_SMBUS_PCICMD 0x04 // CMD register enables/disables, Memory/IO space access and interrupt\r
	54	#define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 // Interrupt Disable\r
	55	#define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0'\r
	56	#define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 // SERR Enable - reserved as '0'\r
	57	#define B_PCH_SMBUS_PCICMD_WCC BIT7 // Wait Cycle Control - reserved as '0'\r
	58	#define B_PCH_SMBUS_PCICMD_PER BIT6 // Parity Error - reserved as '0'\r
	59	#define B_PCH_SMBUS_PCICMD_VPS BIT5 // VGA Palette Snoop - reserved as '0'\r
	60	#define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'\r
	61	#define B_PCH_SMBUS_PCICMD_SCE BIT3 // Special Cycle Enable - reserved as '0'\r
	62	#define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0'\r
	63	#define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable\r
	64	#define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable\r
65	\r
66	#define R_PCH_SMBUS_BASE 0x20 // The I/O memory bar\r
67	#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 // Base Address\r
68	#define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator\r
69	\r
70	#define R_PCH_SMBUS_SVID 0x2C // Subsystem Vendor ID\r
71	#define B_PCH_SMBUS_SVID 0xFFFF // Subsystem Vendor ID\r
72	\r
73	//\r
74	// SMBus I/O Registers\r
75	//\r
76	#define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W\r
77	#define B_PCH_SMBUS_HSTS_ALL 0xFF\r
78	#define B_PCH_SMBUS_BYTE_DONE_STS BIT7 // Byte Done Status\r
79	#define B_PCH_SMBUS_IUS BIT6 // In Use Status\r
80	#define B_PCH_SMBUS_SMBALERT_STS BIT5 // SMBUS Alert\r
81	#define B_PCH_SMBUS_FAIL BIT4 // Failed\r
82	#define B_PCH_SMBUS_BERR BIT3 // Bus Error\r
83	#define B_PCH_SMBUS_DERR BIT2 // Device Error\r
84	#define B_PCH_SMBUS_ERRORS (B_PCH_SMBUS_FAIL \| B_PCH_SMBUS_BERR \| B_PCH_SMBUS_DERR)\r
85	#define B_PCH_SMBUS_INTR BIT1 // Interrupt\r
86	#define B_PCH_SMBUS_HBSY BIT0 // Host Busy\r
87	\r
88	#define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W\r
89	#define B_PCH_SMBUS_PEC_EN BIT7 // Packet Error Checking Enable\r
90	#define B_PCH_SMBUS_START BIT6 // Start\r
91	#define B_PCH_SMBUS_LAST_BYTE BIT5 // Last Byte\r
92	#define B_PCH_SMBUS_SMB_CMD 0x1C // SMB Command\r
93	#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C // Block Process\r
94	#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 // I2C Read\r
95	#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block\r
96	#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 // Process Call\r
97	#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C // Word Data\r
98	#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data\r
99	#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 // Byte\r
100	#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 // Quick\r
101	#define B_PCH_SMBUS_KILL BIT1 // Kill\r
102	#define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable\r
103	\r
104	#define R_PCH_SMBUS_HCMD 0x03 // Host Command Register R/W\r
105	#define B_PCH_SMBUS_HCMD 0xFF // Command to be transmitted\r
106	\r
107	#define R_PCH_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W\r
108	#define B_PCH_SMBUS_ADDRESS 0xFE // 7-bit address of the targeted slave\r
109	#define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = write\r
110	#define B_PCH_SMBUS_RW_SEL_READ 0x01 // Read\r
111	#define B_PCH_SMBUS_RW_SEL_WRITE 0x00 // Write\r
112	//\r
113	#define R_PCH_SMBUS_HD0 0x05 // Data 0 Register R/W\r
114	#define R_PCH_SMBUS_HD1 0x06 // Data 1 Register R/W\r
115	#define R_PCH_SMBUS_HBD 0x07 // Host Block Data Register R/W\r
116	#define R_PCH_SMBUS_PEC 0x08 // Packet Error Check Data Register R/W\r
117	\r
118	#define R_PCH_SMBUS_RSA 0x09 // Receive Slave Address Register R/W\r
119	#define B_PCH_SMBUS_SLAVE_ADDR 0x7F // TCO slave address (Not used, reserved)\r
120	\r
121	#define R_PCH_SMBUS_SD 0x0A // Receive Slave Data Register R/W\r
122	\r
123	#define R_PCH_SMBUS_AUXS 0x0C // Auxiliary Status Register R/WC\r
124	#define B_PCH_SMBUS_CRCE BIT0 // CRC Error\r
125	//\r
126	#define R_PCH_SMBUS_AUXC 0x0D // Auxiliary Control Register R/W\r
127	#define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer\r
128	#define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC\r
129	\r
130	#define R_PCH_SMBUS_SMLC 0x0E // SMLINK Pin Control Register R/W\r
131	#define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported\r
132	#define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported\r
133	#define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported\r
134	\r
135	\r
136	#define R_PCH_SMBUS_SMBC 0x0F // SMBus Pin Control Register R/W\r
137	#define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control\r
138	#define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status\r
139	#define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status\r
140	\r
141	#define R_PCH_SMBUS_SSTS 0x10 // Slave Status Register R/WC\r
142	#define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status\r
143	\r
144	#define R_PCH_SMBUS_SCMD 0x11 // Slave Command Register R/W\r
145	#define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported\r
146	#define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable\r
147	#define B_PCH_SMBUS_HOST_NOTIFY_INTREN BIT0 // Host Notify Interrupt Enable\r
148	\r
149	#define R_PCH_SMBUS_NDA 0x14 // Notify Device Address Register RO\r
150	#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE // Device Address\r
151	\r
152	#define R_PCH_SMBUS_NDLB 0x16 // Notify Data Low Byte Register RO\r
153	#define R_PCH_SMBUS_NDHB 0x17 // Notify Data High Byte Register RO\r
154	\r
155	#endif\r