[mirror_edk2.git] / Vlv2TbltDevicePkg / Include / Platform.h

/*++\r
\r
  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  This program and the accompanying materials are licensed and made available under\r\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
  The full text of the license may be found at                                     \r\r
  http://opensource.org/licenses/bsd-license.php.                                  \r\r
                                                                                   \r\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
                                                                                   \r\r
\r
\r
Module Name:\r
\r
  Platform.h\r
\r
Abstract:\r
\r
  Pinetrail platform specific information.\r
\r
**/\r
\r
#ifndef _PLATFORM_H\r
#define _PLATFORM_H\r
\r
#include "ChipsetAccess.h"\r
#include "PlatformBaseAddresses.h"\r
\r
\r
//\r
// Number of P & T states supported.\r
//\r
#define NPTM_P_STATES_SUPPORTED         16\r
#define NPTM_T_STATES_SUPPORTED         8\r
\r
//\r
// I/O APIC IDs, the code uses math to generate the numbers\r
// instead of using these defines.\r
//\r
#define ICH_IOAPIC                     (1 << 0)\r
#define ICH_IOAPIC_ID                   0x08\r
\r
//\r
// Possible SMBus addresses that will be present.\r
//\r
#define SMBUS_ADDR_CH_A_1     0xA0\r
#define SMBUS_ADDR_CH_A_2     0xA2\r
#define SMBUS_ADDR_CH_B_1     0xA4\r
#define SMBUS_ADDR_CH_B_2     0xA6\r
#define SMBUS_ADDR_CH_C_1     0xA8\r
#define SMBUS_ADDR_CH_C_2     0xAA\r
#define SMBUS_ADDR_CH_D_1     0xAC\r
#define SMBUS_ADDR_CH_D_2     0xAE\r
#define SMBUS_ADDR_HOST_CLK_BUFFER  0xDC\r
#define SMBUS_ADDR_ICH_SLAVE        0x44\r
#define SMBUS_ADDR_HECETA     0x5C\r
#define SMBUS_ADDR_SMBARP     0xC2\r
#define SMBUS_ADDR_82573E     0xC6\r
#define SMBUS_ADDR_CLKCHIP    0xD2\r
#define SMBUS_ADDR_BRD_REV          0x4E\r
#define SMBUS_ADDR_DB803            0x82\r
\r
//\r
// SMBus addresses that used on this platform.\r
//\r
#define PLATFORM_SMBUS_RSVD_ADDRESSES { \\r
  SMBUS_ADDR_CH_A_1, \\r
  SMBUS_ADDR_CH_A_2, \\r
  SMBUS_ADDR_HOST_CLK_BUFFER, \\r
  SMBUS_ADDR_ICH_SLAVE, \\r
  SMBUS_ADDR_SMBARP, \\r
  SMBUS_ADDR_CLKCHIP, \\r
  SMBUS_ADDR_BRD_REV, \\r
  SMBUS_ADDR_DB803 \\r
  }\r
\r
//\r
// Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.\r
//\r
#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8\r
\r
//\r
// CMOS usage\r
//\r
#define CMOS_CPU_BSP_SELECT         0x10\r
#define CMOS_CPU_UP_MODE            0x11\r
#define CMOS_CPU_RATIO_OFFSET       0x12\r
#define CMOS_CPU_CORE_HT_OFFSET     0x13\r
#define CMOS_EFI_DEBUG              0x14\r
#define CMOS_CPU_BIST_OFFSET        0x15\r
#define CMOS_CPU_VMX_OFFSET         0x16\r
#define CMOS_ICH_PORT80_OFFSET      0x17\r
#define CMOS_PLATFORM_DESIGNATOR    0x18      // Second bank CMOS location of Platform ID.\r
#define CMOS_VALIDATION_TEST_BYTE   0x19      // BIT0 - Validation mailbox for UPonDP.\r
#define CMOS_SERIAL_BAUD_RATE       0x1A      // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600\r
#define CMOS_DCU_MODE_OFFSET        0x1B\r
#define CMOS_VR11_SET_OFFSET        0x1C\r
#define CMOS_SBSP_TO_AP_COMM        0x20      // SEC code use ONLY!!!\r
#define CMOS_RESET_TYPE_BY_OS       0x52\r
#define TCG_CMOS_MOR_AREA_OFFSET    0x65      // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &\r
#define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E\r
#define ACPI_TPM_REQUEST            0x75\r
#define ACPI_TPM_LAST_REQUEST       0x76\r
#define CMOS_BOOT_FLAG_ADDRESS      0x7E\r
\r
//\r
// GPIO Index Data Structure.\r
//\r
typedef struct {\r
  UINT8   Register;\r
  UINT32  Value;\r
} ICH_GPIO_DEV;\r
\r
//\r
// CPU Equates\r
//\r
#define MAX_THREAD                      2\r
#define MAX_CORE                        1\r
#define MAX_DIE                         2\r
#define MAX_CPU_SOCKET                  1\r
#define MAX_CPU_NUM                     (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)\r
\r
#define MEM64_LEN                       0x00100000000\r
#define RES_MEM64_36_BASE               0x01000000000 - MEM64_LEN   // 2^36\r
#define RES_MEM64_36_LIMIT              0x01000000000 - 1           // 2^36\r
#define RES_MEM64_39_BASE               0x08000000000 - MEM64_LEN   // 2^39\r
#define RES_MEM64_39_LIMIT              0x08000000000 - 1           // 2^39\r
#define RES_MEM64_40_BASE               0x10000000000 - MEM64_LEN   // 2^40\r
#define RES_MEM64_40_LIMIT              0x10000000000 - 1           // 2^40\r
\r
#define PLATFORM_MAX_BUS_NUM             0x3f\r
#define V_DEFAULT_SUBSYSTEM_DEVICE_ID    0x574d\r
#define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b\r
#define V_DEFAULT_SUBSYSTEM_VENDOR_ID    0x8086\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
	4	\r\r
	5	This program and the accompanying materials are licensed and made available under\r\r
	6	the terms and conditions of the BSD License that accompanies this distribution. \r\r
	7	The full text of the license may be found at \r\r
	8	http://opensource.org/licenses/bsd-license.php. \r\r
	9	\r\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
	12	\r\r
	13	\r
	14	\r
	15	Module Name:\r
	16	\r
	17	Platform.h\r
	18	\r
	19	Abstract:\r
	20	\r
	21	Pinetrail platform specific information.\r
	22	\r
	23	**/\r
	24	\r
	25	#ifndef _PLATFORM_H\r
	26	#define _PLATFORM_H\r
	27	\r
	28	#include "ChipsetAccess.h"\r
	29	#include "PlatformBaseAddresses.h"\r
	30	\r
	31	\r
	32	//\r
	33	// Number of P & T states supported.\r
	34	//\r
	35	#define NPTM_P_STATES_SUPPORTED 16\r
	36	#define NPTM_T_STATES_SUPPORTED 8\r
	37	\r
	38	//\r
	39	// I/O APIC IDs, the code uses math to generate the numbers\r
	40	// instead of using these defines.\r
	41	//\r
	42	#define ICH_IOAPIC (1 << 0)\r
	43	#define ICH_IOAPIC_ID 0x08\r
	44	\r
	45	//\r
	46	// Possible SMBus addresses that will be present.\r
	47	//\r
	48	#define SMBUS_ADDR_CH_A_1 0xA0\r
	49	#define SMBUS_ADDR_CH_A_2 0xA2\r
	50	#define SMBUS_ADDR_CH_B_1 0xA4\r
	51	#define SMBUS_ADDR_CH_B_2 0xA6\r
	52	#define SMBUS_ADDR_CH_C_1 0xA8\r
	53	#define SMBUS_ADDR_CH_C_2 0xAA\r
	54	#define SMBUS_ADDR_CH_D_1 0xAC\r
	55	#define SMBUS_ADDR_CH_D_2 0xAE\r
	56	#define SMBUS_ADDR_HOST_CLK_BUFFER 0xDC\r
	57	#define SMBUS_ADDR_ICH_SLAVE 0x44\r
	58	#define SMBUS_ADDR_HECETA 0x5C\r
	59	#define SMBUS_ADDR_SMBARP 0xC2\r
	60	#define SMBUS_ADDR_82573E 0xC6\r
	61	#define SMBUS_ADDR_CLKCHIP 0xD2\r
	62	#define SMBUS_ADDR_BRD_REV 0x4E\r
	63	#define SMBUS_ADDR_DB803 0x82\r
	64	\r
65	//\r
66	// SMBus addresses that used on this platform.\r
67	//\r
68	#define PLATFORM_SMBUS_RSVD_ADDRESSES { \\r
69	SMBUS_ADDR_CH_A_1, \\r
70	SMBUS_ADDR_CH_A_2, \\r
71	SMBUS_ADDR_HOST_CLK_BUFFER, \\r
72	SMBUS_ADDR_ICH_SLAVE, \\r
73	SMBUS_ADDR_SMBARP, \\r
74	SMBUS_ADDR_CLKCHIP, \\r
75	SMBUS_ADDR_BRD_REV, \\r
76	SMBUS_ADDR_DB803 \\r
77	}\r
78	\r
79	//\r
80	// Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.\r
81	//\r
82	#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8\r
83	\r
84	//\r
85	// CMOS usage\r
86	//\r
87	#define CMOS_CPU_BSP_SELECT 0x10\r
88	#define CMOS_CPU_UP_MODE 0x11\r
89	#define CMOS_CPU_RATIO_OFFSET 0x12\r
90	#define CMOS_CPU_CORE_HT_OFFSET 0x13\r
91	#define CMOS_EFI_DEBUG 0x14\r
92	#define CMOS_CPU_BIST_OFFSET 0x15\r
93	#define CMOS_CPU_VMX_OFFSET 0x16\r
94	#define CMOS_ICH_PORT80_OFFSET 0x17\r
95	#define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS location of Platform ID.\r
96	#define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation mailbox for UPonDP.\r
97	#define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600\r
98	#define CMOS_DCU_MODE_OFFSET 0x1B\r
99	#define CMOS_VR11_SET_OFFSET 0x1C\r
100	#define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!!\r
101	#define CMOS_RESET_TYPE_BY_OS 0x52\r
102	#define TCG_CMOS_MOR_AREA_OFFSET 0x65 // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &\r
103	#define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E\r
104	#define ACPI_TPM_REQUEST 0x75\r
105	#define ACPI_TPM_LAST_REQUEST 0x76\r
106	#define CMOS_BOOT_FLAG_ADDRESS 0x7E\r
107	\r
108	//\r
109	// GPIO Index Data Structure.\r
110	//\r
111	typedef struct {\r
112	UINT8 Register;\r
113	UINT32 Value;\r
114	} ICH_GPIO_DEV;\r
115	\r
116	//\r
117	// CPU Equates\r
118	//\r
119	#define MAX_THREAD 2\r
120	#define MAX_CORE 1\r
121	#define MAX_DIE 2\r
122	#define MAX_CPU_SOCKET 1\r
123	#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)\r
124	\r
125	#define MEM64_LEN 0x00100000000\r
126	#define RES_MEM64_36_BASE 0x01000000000 - MEM64_LEN // 2^36\r
127	#define RES_MEM64_36_LIMIT 0x01000000000 - 1 // 2^36\r
128	#define RES_MEM64_39_BASE 0x08000000000 - MEM64_LEN // 2^39\r
129	#define RES_MEM64_39_LIMIT 0x08000000000 - 1 // 2^39\r
130	#define RES_MEM64_40_BASE 0x10000000000 - MEM64_LEN // 2^40\r
131	#define RES_MEM64_40_LIMIT 0x10000000000 - 1 // 2^40\r
132	\r
133	#define PLATFORM_MAX_BUS_NUM 0x3f\r
134	#define V_DEFAULT_SUBSYSTEM_DEVICE_ID 0x574d\r
135	#define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b\r
136	#define V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086\r
137	\r
138	#endif\r