Vlv2TbltDevicePkg/Include/Platform.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15 Module Name:
  16
  17   Platform.h
  18
  19 Abstract:
  20
  21   Pinetrail platform specific information.
  22
  23 **/
  24
  25 #ifndef _PLATFORM_H
  26 #define _PLATFORM_H
  27
  28 #include "ChipsetAccess.h"
  29 #include "PlatformBaseAddresses.h"
  30
  31
  32 //
  33 // Number of P & T states supported.
  34 //
  35 #define NPTM_P_STATES_SUPPORTED         16
  36 #define NPTM_T_STATES_SUPPORTED         8
  37
  38 //
  39 // I/O APIC IDs, the code uses math to generate the numbers
  40 // instead of using these defines.
  41 //
  42 #define ICH_IOAPIC                     (1 << 0)
  43 #define ICH_IOAPIC_ID                   0x08
  44
  45 //
  46 // Possible SMBus addresses that will be present.
  47 //
  48 #define SMBUS_ADDR_CH_A_1     0xA0
  49 #define SMBUS_ADDR_CH_A_2     0xA2
  50 #define SMBUS_ADDR_CH_B_1     0xA4
  51 #define SMBUS_ADDR_CH_B_2     0xA6
  52 #define SMBUS_ADDR_CH_C_1     0xA8
  53 #define SMBUS_ADDR_CH_C_2     0xAA
  54 #define SMBUS_ADDR_CH_D_1     0xAC
  55 #define SMBUS_ADDR_CH_D_2     0xAE
  56 #define SMBUS_ADDR_HOST_CLK_BUFFER  0xDC
  57 #define SMBUS_ADDR_ICH_SLAVE        0x44
  58 #define SMBUS_ADDR_HECETA     0x5C
  59 #define SMBUS_ADDR_SMBARP     0xC2
  60 #define SMBUS_ADDR_82573E     0xC6
  61 #define SMBUS_ADDR_CLKCHIP    0xD2
  62 #define SMBUS_ADDR_BRD_REV          0x4E
  63 #define SMBUS_ADDR_DB803            0x82
  64
  65 //
  66 // SMBus addresses that used on this platform.
  67 //
  68 #define PLATFORM_SMBUS_RSVD_ADDRESSES { \
  69   SMBUS_ADDR_CH_A_1, \
  70   SMBUS_ADDR_CH_A_2, \
  71   SMBUS_ADDR_HOST_CLK_BUFFER, \
  72   SMBUS_ADDR_ICH_SLAVE, \
  73   SMBUS_ADDR_SMBARP, \
  74   SMBUS_ADDR_CLKCHIP, \
  75   SMBUS_ADDR_BRD_REV, \
  76   SMBUS_ADDR_DB803 \
  77   }
  78
  79 //
  80 // Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.
  81 //
  82 #define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8
  83
  84 //
  85 // CMOS usage
  86 //
  87 #define CMOS_CPU_BSP_SELECT         0x10
  88 #define CMOS_CPU_UP_MODE            0x11
  89 #define CMOS_CPU_RATIO_OFFSET       0x12
  90 #define CMOS_CPU_CORE_HT_OFFSET     0x13
  91 #define CMOS_EFI_DEBUG              0x14
  92 #define CMOS_CPU_BIST_OFFSET        0x15
  93 #define CMOS_CPU_VMX_OFFSET         0x16
  94 #define CMOS_ICH_PORT80_OFFSET      0x17
  95 #define CMOS_PLATFORM_DESIGNATOR    0x18      // Second bank CMOS location of Platform ID.
  96 #define CMOS_VALIDATION_TEST_BYTE   0x19      // BIT0 - Validation mailbox for UPonDP.
  97 #define CMOS_SERIAL_BAUD_RATE       0x1A      // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600
  98 #define CMOS_DCU_MODE_OFFSET        0x1B
  99 #define CMOS_VR11_SET_OFFSET        0x1C
 100 #define CMOS_SBSP_TO_AP_COMM        0x20      // SEC code use ONLY!!!
 101 #define CMOS_RESET_TYPE_BY_OS       0x52
 102 #define TCG_CMOS_MOR_AREA_OFFSET    0x65      // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &
 103 #define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E
 104 #define ACPI_TPM_REQUEST            0x75
 105 #define ACPI_TPM_LAST_REQUEST       0x76
 106 #define CMOS_BOOT_FLAG_ADDRESS      0x7E
 107
 108 //
 109 // GPIO Index Data Structure.
 110 //
 111 typedef struct {
 112   UINT8   Register;
 113   UINT32  Value;
 114 } ICH_GPIO_DEV;
 115
 116 //
 117 // CPU Equates
 118 //
 119 #define MAX_THREAD                      2
 120 #define MAX_CORE                        1
 121 #define MAX_DIE                         2
 122 #define MAX_CPU_SOCKET                  1
 123 #define MAX_CPU_NUM                     (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)
 124
 125 #define MEM64_LEN                       0x00100000000
 126 #define RES_MEM64_36_BASE               0x01000000000 - MEM64_LEN   // 2^36
 127 #define RES_MEM64_36_LIMIT              0x01000000000 - 1           // 2^36
 128 #define RES_MEM64_39_BASE               0x08000000000 - MEM64_LEN   // 2^39
 129 #define RES_MEM64_39_LIMIT              0x08000000000 - 1           // 2^39
 130 #define RES_MEM64_40_BASE               0x10000000000 - MEM64_LEN   // 2^40
 131 #define RES_MEM64_40_LIMIT              0x10000000000 - 1           // 2^40
 132
 133 #define PLATFORM_MAX_BUS_NUM             0x3f
 134 #define V_DEFAULT_SUBSYSTEM_DEVICE_ID    0x574d
 135 #define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b
 136 #define V_DEFAULT_SUBSYSTEM_VENDOR_ID    0x8086
 137
 138 #endif