projects / mirror_edk2.git / blame
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| 4e522096 DW |
1 | /** @file\r |
| 2 | Register Definitions for I2C Driver/PEIM.\r | |
| 3 | \r | |
| 4 | Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>\r | |
| 5 | \r | |
| 6 | This program and the accompanying materials are licensed and made available under\r | |
| 7 | the terms and conditions of the BSD License that accompanies this distribution. \r | |
| 8 | The full text of the license may be found at \r | |
| 9 | http://opensource.org/licenses/bsd-license.php. \r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 13 | \r | |
| 14 | --*/\r | |
| 15 | \r | |
| 16 | #ifndef I2C_REGS_H\r | |
| 17 | #define I2C_REGS_H\r | |
| 18 | \r | |
| 19 | //\r | |
| 20 | // FIFO write delay value.\r | |
| 21 | //\r | |
| 22 | #define FIFO_WRITE_DELAY 2\r | |
| 23 | \r | |
| 24 | //\r | |
| 25 | // MMIO Register Definitions.\r | |
| 26 | //\r | |
| 27 | #define R_IC_CON ( 0x00) // I2C Control \r | |
| 28 | #define B_IC_RESTART_EN BIT5\r | |
| 29 | #define B_IC_SLAVE_DISABLE BIT6\r | |
| 30 | #define V_SPEED_STANDARD 0x02\r | |
| 31 | #define V_SPEED_FAST 0x04\r | |
| 32 | #define V_SPEED_HIGH 0x06\r | |
| 33 | #define B_MASTER_MODE BIT0\r | |
| 34 | \r | |
| 35 | #define R_IC_TAR ( 0x04) // I2C Target Address\r | |
| 36 | #define IC_TAR_10BITADDR_MASTER BIT12\r | |
| 37 | \r | |
| 38 | #define R_IC_SAR ( 0x08) // I2C Slave Address\r | |
| 39 | #define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address\r | |
| 40 | #define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command\r | |
| 41 | \r | |
| 42 | #define B_READ_CMD BIT8 // 1 = read, 0 = write\r | |
| 43 | #define B_CMD_STOP BIT9 // 1 = STOP\r | |
| 44 | #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN\r | |
| 45 | \r | |
| 46 | #define V_WRITE_CMD_MASK ( 0xFF)\r | |
| 47 | \r | |
| 48 | #define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count\r | |
| 49 | #define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count\r | |
| 50 | #define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count\r | |
| 51 | #define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count\r | |
| 52 | #define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count\r | |
| 53 | #define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count\r | |
| 54 | #define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status\r | |
| 55 | #define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask\r | |
| 56 | #define I2C_INTR_GEN_CALL BIT11 // General call received\r | |
| 57 | #define I2C_INTR_START_DET BIT10\r | |
| 58 | #define I2C_INTR_STOP_DET BIT9\r | |
| 59 | #define I2C_INTR_ACTIVITY BIT8\r | |
| 60 | #define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r | |
| 61 | #define I2C_INTR_TX_EMPTY BIT4\r | |
| 62 | #define I2C_INTR_TX_OVER BIT3\r | |
| 63 | #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r | |
| 64 | #define I2C_INTR_RX_OVER BIT1\r | |
| 65 | #define I2C_INTR_RX_UNDER BIT0\r | |
| 66 | #define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status\r | |
| 67 | #define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold\r | |
| 68 | #define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold\r | |
| 69 | #define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts\r | |
| 70 | #define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt\r | |
| 71 | #define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt\r | |
| 72 | #define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt\r | |
| 73 | #define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt\r | |
| 74 | #define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt\r | |
| 75 | #define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt\r | |
| 76 | #define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt\r | |
| 77 | #define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt\r | |
| 78 | #define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt\r | |
| 79 | #define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt\r | |
| 80 | #define R_IC_ENABLE ( 0x6C) // I2C Enable\r | |
| 81 | #define R_IC_STATUS ( 0x70) // I2C Status\r | |
| 82 | \r | |
| 83 | #define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits\r | |
| 84 | \r | |
| 85 | #define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.\r | |
| 86 | #define STAT_RFF BIT4 // RX FIFO is completely full\r | |
| 87 | #define STAT_RFNE BIT3 // RX FIFO is not empty\r | |
| 88 | #define STAT_TFE BIT2 // TX FIFO is completely empty\r | |
| 89 | #define STAT_TFNF BIT1 // TX FIFO is not full\r | |
| 90 | \r | |
| 91 | #define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register\r | |
| 92 | #define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register\r | |
| 93 | #define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register\r | |
| 94 | #define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register\r | |
| 95 | #define R_IC_DMA_CR ( 0x88) // DMA Control Register\r | |
| 96 | #define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level\r | |
| 97 | #define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level\r | |
| 98 | #define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register\r | |
| 99 | #define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register\r | |
| 100 | #define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register\r | |
| 101 | #define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register\r | |
| 102 | #define R_IC_COMP_VERSION ( 0xF8) // Component Version ID\r | |
| 103 | #define R_IC_COMP_TYPE ( 0xFC) // Component Type\r | |
| 104 | \r | |
| 105 | #define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD\r | |
| 106 | #define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4\r | |
| 107 | #define I2C_FS_SCL_HCNT_VALUE_100M 0x54\r | |
| 108 | #define I2C_FS_SCL_LCNT_VALUE_100M 0x9a\r | |
| 109 | #define I2C_HS_SCL_HCNT_VALUE_100M 0x7\r | |
| 110 | #define I2C_HS_SCL_LCNT_VALUE_100M 0xE\r | |
| 111 | \r | |
| 112 | #define IC_TAR_10BITADDR_MASTER BIT12\r | |
| 113 | #define FIFO_SIZE 32\r | |
| 114 | #define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status\r | |
| 115 | #define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask\r | |
| 116 | #define I2C_INTR_GEN_CALL BIT11 // General call received\r | |
| 117 | #define I2C_INTR_START_DET BIT10\r | |
| 118 | #define I2C_INTR_STOP_DET BIT9\r | |
| 119 | #define I2C_INTR_ACTIVITY BIT8\r | |
| 120 | #define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r | |
| 121 | #define I2C_INTR_TX_EMPTY BIT4\r | |
| 122 | #define I2C_INTR_TX_OVER BIT3\r | |
| 123 | #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r | |
| 124 | #define I2C_INTR_RX_OVER BIT1\r | |
| 125 | #define I2C_INTR_RX_UNDER BIT0\r | |
| 126 | \r | |
| 127 | #define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset\r | |
| 128 | #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r | |
| 129 | #define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset\r | |
| 130 | #define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters\r | |
| 131 | \r | |
| 132 | #endif |