Vlv2TbltDevicePkg/Library/I2CLibDxe/I2CRegs.h

   1 /** @file
   2   Register Definitions for I2C Driver/PEIM.
   3
   4   Copyright (c) 2004  - 2015, Intel Corporation. All rights reserved.<BR>
   5
   6   This program and the accompanying materials are licensed and made available under
   7   the terms and conditions of the BSD License that accompanies this distribution.
   8   The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php.
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 --*/
  15
  16 #ifndef I2C_REGS_H
  17 #define I2C_REGS_H
  18
  19 //
  20 // FIFO write delay value.
  21 //
  22 #define FIFO_WRITE_DELAY    2
  23
  24 //
  25 // MMIO Register Definitions.
  26 //
  27 #define    R_IC_CON                          ( 0x00) // I2C Control
  28 #define     B_IC_RESTART_EN                  BIT5
  29 #define     B_IC_SLAVE_DISABLE               BIT6
  30 #define     V_SPEED_STANDARD                 0x02
  31 #define     V_SPEED_FAST                     0x04
  32 #define     V_SPEED_HIGH                     0x06
  33 #define     B_MASTER_MODE                    BIT0
  34
  35 #define    R_IC_TAR                          ( 0x04) // I2C Target Address
  36 #define     IC_TAR_10BITADDR_MASTER           BIT12
  37
  38 #define    R_IC_SAR                          ( 0x08) // I2C Slave Address
  39 #define    R_IC_HS_MADDR                     ( 0x0C) // I2C HS MasterMode Code Address
  40 #define    R_IC_DATA_CMD                     ( 0x10) // I2C Rx/Tx Data Buffer and Command
  41
  42 #define    B_READ_CMD                         BIT8    // 1 = read, 0 = write
  43 #define    B_CMD_STOP                         BIT9    // 1 = STOP
  44 #define    B_CMD_RESTART                      BIT10   // 1 = IC_RESTART_EN
  45
  46 #define    V_WRITE_CMD_MASK                  ( 0xFF)
  47
  48 #define    R_IC_SS_SCL_HCNT                  ( 0x14) // Standard Speed I2C Clock SCL High Count
  49 #define    R_IC_SS_SCL_LCNT                  ( 0x18) // Standard Speed I2C Clock SCL Low Count
  50 #define    R_IC_FS_SCL_HCNT                  ( 0x1C) // Full Speed I2C Clock SCL High Count
  51 #define    R_IC_FS_SCL_LCNT                  ( 0x20) // Full Speed I2C Clock SCL Low Count
  52 #define    R_IC_HS_SCL_HCNT                  ( 0x24) // High Speed I2C Clock SCL High Count
  53 #define    R_IC_HS_SCL_LCNT                  ( 0x28) // High Speed I2C Clock SCL Low Count
  54 #define    R_IC_INTR_STAT                    ( 0x2C) // I2C Inetrrupt Status
  55 #define    R_IC_INTR_MASK                    ( 0x30) // I2C Interrupt Mask
  56 #define     I2C_INTR_GEN_CALL                 BIT11  // General call received
  57 #define     I2C_INTR_START_DET                BIT10
  58 #define     I2C_INTR_STOP_DET                 BIT9
  59 #define     I2C_INTR_ACTIVITY                 BIT8
  60 #define     I2C_INTR_TX_ABRT                  BIT6   // Set on NACK
  61 #define     I2C_INTR_TX_EMPTY                 BIT4
  62 #define     I2C_INTR_TX_OVER                  BIT3
  63 #define     I2C_INTR_RX_FULL                  BIT2   // Data bytes in RX FIFO over threshold
  64 #define     I2C_INTR_RX_OVER                  BIT1
  65 #define     I2C_INTR_RX_UNDER                 BIT0
  66 #define    R_IC_RawIntrStat                ( 0x34) // I2C Raw Interrupt Status
  67 #define    R_IC_RX_TL                        ( 0x38) // I2C Receive FIFO Threshold
  68 #define    R_IC_TX_TL                        ( 0x3C) // I2C Transmit FIFO Threshold
  69 #define    R_IC_CLR_INTR                     ( 0x40) // Clear Combined and Individual Interrupts
  70 #define    R_IC_CLR_RX_UNDER                 ( 0x44) // Clear RX_UNDER Interrupt
  71 #define    R_IC_CLR_RX_OVER                  ( 0x48) // Clear RX_OVERinterrupt
  72 #define    R_IC_CLR_TX_OVER                  ( 0x4C) // Clear TX_OVER interrupt
  73 #define    R_IC_CLR_RD_REQ                   ( 0x50) // Clear RD_REQ interrupt
  74 #define    R_IC_CLR_TX_ABRT                  ( 0x54) // Clear TX_ABRT interrupt
  75 #define    R_IC_CLR_RX_DONE                  ( 0x58) // Clear RX_DONE interrupt
  76 #define    R_IC_CLR_ACTIVITY                 ( 0x5C) // Clear ACTIVITY interrupt
  77 #define    R_IC_CLR_STOP_DET                 ( 0x60) // Clear STOP_DET interrupt
  78 #define    R_IC_CLR_START_DET                ( 0x64) // Clear START_DET interrupt
  79 #define    R_IC_CLR_GEN_CALL                 ( 0x68) // Clear GEN_CALL interrupt
  80 #define    R_IC_ENABLE                       ( 0x6C) // I2C Enable
  81 #define    R_IC_STATUS                       ( 0x70) // I2C Status
  82
  83 #define    R_IC_SDA_HOLD                     ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
  84
  85 #define     STAT_MST_ACTIVITY                 BIT5   // Master FSM Activity Status.
  86 #define     STAT_RFF                          BIT4   // RX FIFO is completely full
  87 #define     STAT_RFNE                         BIT3   // RX FIFO is not empty
  88 #define     STAT_TFE                          BIT2   // TX FIFO is completely empty
  89 #define     STAT_TFNF                         BIT1   // TX FIFO is not full
  90
  91 #define    R_IC_TXFLR                        ( 0x74) // Transmit FIFO Level Register
  92 #define    R_IC_RXFLR                        ( 0x78) // Receive FIFO Level Register
  93 #define    R_IC_TX_ABRT_SOURCE               ( 0x80) // I2C Transmit Abort Status Register
  94 #define    R_IC_SLV_DATA_NACK_ONLY           ( 0x84) // Generate SLV_DATA_NACK Register
  95 #define    R_IC_DMA_CR                       ( 0x88) // DMA Control Register
  96 #define    R_IC_DMA_TDLR                     ( 0x8C) // DMA Transmit Data Level
  97 #define    R_IC_DMA_RDLR                     ( 0x90) // DMA Receive Data Level
  98 #define    R_IC_SDA_SETUP                    ( 0x94) // I2C SDA Setup Register
  99 #define    R_IC_ACK_GENERAL_CALL             ( 0x98) // I2C ACK General Call Register
 100 #define    R_IC_ENABLE_STATUS                ( 0x9C) // I2C Enable Status Register
 101 #define    R_IC_COMP_PARAM                   ( 0xF4) // Component Parameter Register
 102 #define    R_IC_COMP_VERSION                 ( 0xF8) // Component Version ID
 103 #define    R_IC_COMP_TYPE                    ( 0xFC) // Component Type
 104
 105 #define    I2C_SS_SCL_HCNT_VALUE_100M        0x1DD
 106 #define    I2C_SS_SCL_LCNT_VALUE_100M        0x1E4
 107 #define    I2C_FS_SCL_HCNT_VALUE_100M        0x54
 108 #define    I2C_FS_SCL_LCNT_VALUE_100M        0x9a
 109 #define    I2C_HS_SCL_HCNT_VALUE_100M        0x7
 110 #define    I2C_HS_SCL_LCNT_VALUE_100M        0xE
 111
 112 #define     IC_TAR_10BITADDR_MASTER           BIT12
 113 #define     FIFO_SIZE                         32
 114 #define     R_IC_INTR_STAT                    ( 0x2C) // I2c Inetrrupt Status
 115 #define     R_IC_INTR_MASK                    ( 0x30) // I2c Interrupt Mask
 116 #define     I2C_INTR_GEN_CALL                 BIT11  // General call received
 117 #define     I2C_INTR_START_DET                BIT10
 118 #define     I2C_INTR_STOP_DET                 BIT9
 119 #define     I2C_INTR_ACTIVITY                 BIT8
 120 #define     I2C_INTR_TX_ABRT                  BIT6   // Set on NACK
 121 #define     I2C_INTR_TX_EMPTY                 BIT4
 122 #define     I2C_INTR_TX_OVER                  BIT3
 123 #define     I2C_INTR_RX_FULL                  BIT2   // Data bytes in RX FIFO over threshold
 124 #define     I2C_INTR_RX_OVER                  BIT1
 125 #define     I2C_INTR_RX_UNDER                 BIT0
 126
 127 #define R_PCH_LPIO_I2C_MEM_RESETS                 0x804 // Software Reset
 128 #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC            BIT1  // Function Clock Domain Reset
 129 #define B_PCH_LPIO_I2C_MEM_RESETS_APB             BIT0  // APB Domain Reset
 130 #define R_PCH_LPSS_I2C_MEM_PCP                    0x800 // Private Clock Parameters
 131
 132 #endif