Vlv2TbltDevicePkg:Signal EndOfDxe Event.

[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / ResetSystemLib / ResetSystemLib.c

/** @file\r
\r
Copyright (c) 2007  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  This program and the accompanying materials are licensed and made available under\r\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
  The full text of the license may be found at                                     \r\r
  http://opensource.org/licenses/bsd-license.php.                                  \r\r
                                                                                   \r\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
                                                                                   \r\r
\r
\r
Module Name:\r
\r
  IdeBus.h\r
\r
Abstract:\r
\r
  System reset Library Services.  This library class provides a set of\r
  methods to reset whole system with manipulate ICH.\r
\r
**/\r
\r
\r
#include <Base.h>\r
\r
\r
#include <Library/ResetSystemLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PciLib.h>\r
\r
#include "PchRegs.h"\r
#include "Rsci.h"\r
#include "Platform.h"\r
\r
#define RESET_GENERATOR_PORT R_PCH_RST_CNT\r
\r
VOID\r
EFIAPI\r
PlatformResetHook (\r
  UINT8 ResetType\r
  )\r
{\r
  //\r
  // Platform need to save OS reset request/types for next Android boot\r
  //\r
  IoWrite8 (0x72, CMOS_RESET_TYPE_BY_OS);\r
  IoWrite8 (0x73, ResetType);\r
}\r
\r
/**\r
  Calling this function causes a system-wide reset. This sets\r
  all circuitry within the system to its initial state. This type of reset\r
  is asynchronous to system operation and operates without regard to\r
  cycle boundaries.\r
\r
  System reset should not return, if it returns, it means the system does\r
  not support cold reset.\r
**/\r
VOID\r
EFIAPI\r
ResetCold (\r
  VOID\r
  )\r
{\r
  PlatformResetHook(COLD_RESET);\r
  IoWrite8 (RESET_GENERATOR_PORT, 0x2);\r
  IoWrite8 (RESET_GENERATOR_PORT, 0x6);\r
}\r
\r
/**\r
  Calling this function causes a system-wide initialization. The processors\r
  are set to their initial state, and pending cycles are not corrupted.\r
\r
  System reset should not return, if it returns, it means the system does\r
  not support warm reset.\r
**/\r
VOID\r
EFIAPI\r
ResetWarm (\r
  VOID\r
  )\r
{\r
  PlatformResetHook(WARM_RESET);\r
  IoWrite8 (RESET_GENERATOR_PORT, 0x0);\r
  IoWrite8 (RESET_GENERATOR_PORT, 0x4);\r
}\r
\r
/**\r
  Calling this function causes the system to enter a power state equivalent\r
  to the ACPI G2/S5 or G3 states.\r
\r
  System shutdown should not return, if it returns, it means the system does\r
  not support shut down reset.\r
**/\r
VOID\r
EFIAPI\r
ResetShutdown (\r
  VOID\r
  )\r
{\r
  UINT16  PchPmioBase;\r
  UINT16  Data16;\r
  UINT32  Data32;\r
\r
  PchPmioBase = (UINT16) (PciRead16 (PCI_LIB_ADDRESS(0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ACPI_BASE)) & ~BIT0);\r
\r
  //\r
  // Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5\r
  //\r
  Data16 = 0;\r
  IoWrite16 (\r
    (UINTN)(PchPmioBase + R_PCH_ACPI_GPE0a_EN),\r
    (UINT16)Data16\r
    );\r
\r
  //\r
  // Clear Sleep SMI Status\r
  //\r
  IoWrite16 (PchPmioBase + R_PCH_SMI_STS,\r
             (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_STS) | B_PCH_SMI_STS_ON_SLP_EN));\r
  //\r
  // Clear Sleep Type Enable\r
  //\r
  IoWrite16 (PchPmioBase + R_PCH_SMI_EN,\r
             (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_EN) & (~B_PCH_SMI_EN_ON_SLP_EN)));\r
  //\r
  // Clear Power Button Status\r
  //\r
  IoWrite16(PchPmioBase + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);\r
\r
  //\r
  // Secondly, Power Button Status bit must be cleared\r
  //\r
  // Write a "1" to bit[8] of power button status register at\r
  // (ABASE + PM1_STS) to clear this bit\r
  // Clear it through SMI Status register\r
  //\r
  Data16 = B_PCH_SMI_STS_PM1_STS_REG;\r
  IoWrite16 ((UINTN) (PchPmioBase + R_PCH_SMI_STS), Data16);\r
\r
  //\r
  // Finally, transform system into S5 sleep state\r
  //\r
  Data32  = IoRead32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT));\r
\r
  Data32  = (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5);\r
\r
  IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);\r
\r
  Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN;\r
\r
  IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);\r
\r
  return;\r
}\r
\r
/**\r
  Calling this function causes the system to enter a power state for capsule\r
  update.\r
\r
  Reset update should not return, if it returns, it means the system does\r
  not support capsule update.\r
\r
**/\r
VOID\r
EFIAPI\r
EnterS3WithImmediateWake (\r
  VOID\r
  )\r
{\r
  ASSERT (FALSE);\r
}\r
\r