Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.c

   1 /** @file
   2
   3 Copyright (c) 2007  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15 Module Name:
  16
  17   IdeBus.h
  18
  19 Abstract:
  20
  21   System reset Library Services.  This library class provides a set of
  22   methods to reset whole system with manipulate ICH.
  23
  24 **/
  25
  26
  27 #include <Base.h>
  28
  29
  30 #include <Library/ResetSystemLib.h>
  31 #include <Library/BaseLib.h>
  32 #include <Library/IoLib.h>
  33 #include <Library/DebugLib.h>
  34 #include <Library/PciLib.h>
  35
  36 #include "PchRegs.h"
  37 #include "Rsci.h"
  38 #include "Platform.h"
  39
  40 #define RESET_GENERATOR_PORT R_PCH_RST_CNT
  41
  42 VOID
  43 EFIAPI
  44 PlatformResetHook (
  45   UINT8 ResetType
  46   )
  47 {
  48   //
  49   // Platform need to save OS reset request/types for next Android boot
  50   //
  51   IoWrite8 (0x72, CMOS_RESET_TYPE_BY_OS);
  52   IoWrite8 (0x73, ResetType);
  53 }
  54
  55 /**
  56   Calling this function causes a system-wide reset. This sets
  57   all circuitry within the system to its initial state. This type of reset
  58   is asynchronous to system operation and operates without regard to
  59   cycle boundaries.
  60
  61   System reset should not return, if it returns, it means the system does
  62   not support cold reset.
  63 **/
  64 VOID
  65 EFIAPI
  66 ResetCold (
  67   VOID
  68   )
  69 {
  70   PlatformResetHook(COLD_RESET);
  71   IoWrite8 (RESET_GENERATOR_PORT, 0x2);
  72   IoWrite8 (RESET_GENERATOR_PORT, 0x6);
  73 }
  74
  75 /**
  76   Calling this function causes a system-wide initialization. The processors
  77   are set to their initial state, and pending cycles are not corrupted.
  78
  79   System reset should not return, if it returns, it means the system does
  80   not support warm reset.
  81 **/
  82 VOID
  83 EFIAPI
  84 ResetWarm (
  85   VOID
  86   )
  87 {
  88   PlatformResetHook(WARM_RESET);
  89   IoWrite8 (RESET_GENERATOR_PORT, 0x0);
  90   IoWrite8 (RESET_GENERATOR_PORT, 0x4);
  91 }
  92
  93 /**
  94   Calling this function causes the system to enter a power state equivalent
  95   to the ACPI G2/S5 or G3 states.
  96
  97   System shutdown should not return, if it returns, it means the system does
  98   not support shut down reset.
  99 **/
 100 VOID
 101 EFIAPI
 102 ResetShutdown (
 103   VOID
 104   )
 105 {
 106   UINT16  PchPmioBase;
 107   UINT16  Data16;
 108   UINT32  Data32;
 109
 110   PchPmioBase = (UINT16) (PciRead16 (PCI_LIB_ADDRESS(0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ACPI_BASE)) & ~BIT0);
 111
 112   //
 113   // Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5
 114   //
 115   Data16 = 0;
 116   IoWrite16 (
 117     (UINTN)(PchPmioBase + R_PCH_ACPI_GPE0a_EN),
 118     (UINT16)Data16
 119     );
 120
 121   //
 122   // Clear Sleep SMI Status
 123   //
 124   IoWrite16 (PchPmioBase + R_PCH_SMI_STS,
 125              (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_STS) | B_PCH_SMI_STS_ON_SLP_EN));
 126   //
 127   // Clear Sleep Type Enable
 128   //
 129   IoWrite16 (PchPmioBase + R_PCH_SMI_EN,
 130              (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_EN) & (~B_PCH_SMI_EN_ON_SLP_EN)));
 131   //
 132   // Clear Power Button Status
 133   //
 134   IoWrite16(PchPmioBase + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);
 135
 136   //
 137   // Secondly, Power Button Status bit must be cleared
 138   //
 139   // Write a "1" to bit[8] of power button status register at
 140   // (ABASE + PM1_STS) to clear this bit
 141   // Clear it through SMI Status register
 142   //
 143   Data16 = B_PCH_SMI_STS_PM1_STS_REG;
 144   IoWrite16 ((UINTN) (PchPmioBase + R_PCH_SMI_STS), Data16);
 145
 146   //
 147   // Finally, transform system into S5 sleep state
 148   //
 149   Data32  = IoRead32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT));
 150
 151   Data32  = (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5);
 152
 153   IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);
 154
 155   Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN;
 156
 157   IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);
 158
 159   return;
 160 }
 161
 162 /**
 163   Calling this function causes the system to enter a power state for capsule
 164   update.
 165
 166   Reset update should not return, if it returns, it means the system does
 167   not support capsule update.
 168
 169 **/
 170 VOID
 171 EFIAPI
 172 EnterS3WithImmediateWake (
 173   VOID
 174   )
 175 {
 176   ASSERT (FALSE);
 177 }
 178