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1/** @file\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
5 This program and the accompanying materials are licensed and made available under\r\r
6 the terms and conditions of the BSD License that accompanies this distribution. \r\r
7 The full text of the license may be found at \r\r
8 http://opensource.org/licenses/bsd-license.php. \r\r
9 \r\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
12 \r\r
13\r
14Module Name:\r
15\r
16\r
17 ClockControl.c\r
18\r
19Abstract:\r
20\r
21 Sets platform/SKU specific clock routing information.\r
22\r
23\r
24\r
25--*/\r
26\r
27#include "PlatformDxe.h"\r
28#include <Protocol/CK505ClockPlatformInfo.h>\r
29\r
30//\r
31// Default clock routing informtion (All On)\r
32//\r
33EFI_CLOCK_PLATFORM_INFO mDefClockPolicy = {NULL, 0, NULL, 0, NULL, 0};\r
34\r
35//\r
36// Clock Settings\r
37//\r
38// Static clock table.\r
39// This should be used to define any clock settings that are static\r
40// (Always On or Always Off). Dynamic clocks should be set to enabled\r
41// in this table.\r
42//\r
43EFI_STATIC_SIGNALS mAtxStaticClocks[] = {\r
44 {SrcClk8, Enabled, All},\r
45 {SrcClk7, Enabled, All},\r
46 {SrcClk6, Enabled, All},\r
47 {SrcClk5, Enabled, All},\r
48 {SrcClk4, Enabled, All},\r
49 {SrcClk3, Enabled, All},\r
50 {SrcClk2, Enabled, All},\r
51 {SrcClk1, Enabled, All},\r
52 {SrcClk0, Enabled, All},\r
53 {Ref0, Enabled, All},\r
54 {Dot96, Enabled, All},\r
55 {Usb48, Enabled, All},\r
56 {PciClkF5, Enabled, All},\r
57 {PciClk0, Enabled, All},\r
58 {PciClk2, Enabled, All},\r
59 {PciClk3, Enabled, All},\r
60 {PciClk4, Disabled, All},\r
61 {Cr_B, EnabledWithSwitch, All},\r
62};\r
63\r
64//\r
65// ClockSxInfo Table\r
66// This is a list of clocks that need to be set to a known state when the\r
67// system enters S4 or S5.\r
68//\r
69EFI_STATIC_SIGNALS mAtxSxClocks[] = {\r
70 {SaveClockConfiguration, Disabled, All}\r
71};\r
72\r
73//\r
74// ATX settings structure\r
75//\r
76EFI_CLOCK_PLATFORM_INFO mAtxClockSettings = {\r
77 mAtxStaticClocks,\r
78 sizeof(mAtxStaticClocks) / sizeof(mAtxStaticClocks[0]),\r
79 mAtxSxClocks,\r
80 sizeof(mAtxSxClocks) / sizeof(mAtxSxClocks[0])\r
81};\r
82\r
83#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
84//\r
85// RVP Clock Settings\r
86//\r
87// Static clock table.\r
88// This should be used to define any clock settings that are static\r
89// (Always On or Always Off). Dynamic clocks should be set to enabled\r
90// in this table.\r
91//\r
92//UPSD_TBD Check with Jan if any porting required.\r
93//\r
94EFI_STATIC_SIGNALS mRvpStaticClocks[] = {\r
95 {SrcClk11, Enabled, All}, // Not used/not present but leave coding enabled\r
96 {SrcClk10, Enabled, All}, // Not used/not present but leave coding enabled\r
97 {SrcClk9, Enabled, All}, // Not used/not present but leave coding enabled\r
98 {SrcClk8, Enabled, All}, // ICHSATAII\r
99 {SrcClk7, Enabled, All}, // DPL_REFSSCLKIN\r
100 {SrcClk6, Enabled, All}, // 100M_MCH\r
101 {SrcClk5, Enabled, All}, // Mini-PCIe //TODO PNV: Need to check ICH GPIO38:\r
102 // 0: turn on; 1: turn off\r
103 {SrcClk4, Enabled, All}, // ICHSATA\r
104 {SrcClk3, Enabled, All}, // 100M_ICH\r
105 {SrcClk2, Enabled, All}, // 100M_LAN\r
106 {SrcClk1, Enabled, All}, // 25M_LAN\r
107 {SrcClk0, Enabled, All}, // 96M_DREF\r
108 {Ref0, Enabled, All},\r
109 {Dot96, Enabled, All},\r
110 {Usb48, Enabled, All},\r
111 {PciClkF5, Enabled, All}, // 33M_ICH\r
112 {PciClk0, Enabled, All}, // 33M_RISER\r
113 {PciClk1, Enabled, All}, // 33M_RISER\r
114 {PciClk2, Enabled, All}, // VDD_Clock\r
115 {PciClk3, Enabled, All}, // 33M_S1\r
116 {PciClk4, Enabled, All}, // 33M_PA\r
117};\r
118\r
119//\r
120// Dynamic clock table\r
121// This is used to determine if a clock should be left on or turned off based\r
122// on the presence of a device. The bridge information is used so the bus\r
123// number for the device to be detected can be found.\r
124//\r
125\r
126//\r
127// ClockSxInfo Table\r
128// This is a list of clocks that need to be set to a known state when the\r
129// system enters S4 or S5.\r
130//\r
131EFI_STATIC_SIGNALS mRvpSxClocks[] = {\r
132 {SaveClockConfiguration, Disabled, All}\r
133};\r
134\r
135//\r
136// RVP settings structure\r
137//\r
138EFI_CLOCK_PLATFORM_INFO mRvpClockSettings = {\r
139 mRvpStaticClocks,\r
140 sizeof(mRvpStaticClocks) / sizeof(mRvpStaticClocks[0]),\r
141 0, // No clocks will be turned off mRvpDynamicClocks,\r
142 0, // No clocks will be turned off sizeof(mRvpDynamicClocks) / sizeof(mRvpDynamicClocks[0]),\r
143 mRvpSxClocks,\r
144 sizeof(mRvpSxClocks) / sizeof(mRvpSxClocks[0])\r
145};\r
146#endif\r
147\r
148VOID\r
149InitializeClockRouting(\r
150 )\r
151{\r
152 EFI_STATUS Status;\r
153 UINTN BoardIdVarSize;\r
154 EFI_BOARD_FEATURES BoardIdVar;\r
155 EFI_CLOCK_PLATFORM_INFO *ClockPolicy;\r
156 EFI_HANDLE Handle;\r
157\r
158 ClockPolicy = &mDefClockPolicy;\r
159\r
160 //\r
161 // Do modifications based on board type\r
162 //\r
163 BoardIdVarSize = sizeof (EFI_BOARD_FEATURES);\r
164 Status = gRT->GetVariable (\r
165 BOARD_FEATURES_NAME,\r
166 &gEfiBoardFeaturesGuid,\r
167 NULL,\r
168 &BoardIdVarSize,\r
169 &BoardIdVar\r
170 );\r
171 if (!EFI_ERROR (Status)) {\r
172\r
173#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
174 if (BoardIdVar & B_BOARD_FEATURES_RVP) {\r
175 ClockPolicy = &mRvpClockSettings;\r
176 }\r
177#else\r
178\r
179 //\r
180 // Isolate board type information\r
181 //\r
182 BoardIdVar = BoardIdVar & (B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
183 B_BOARD_FEATURES_FORM_FACTOR_BTX |\r
184 B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX |\r
185 B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX);\r
186\r
187 if (BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_ATX ||\r
188 BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX) {\r
189 ClockPolicy = &mAtxClockSettings;\r
190 }\r
191\r
192#endif\r
193\r
194 }\r
195\r
196 Handle = NULL;\r
197 Status = gBS->InstallProtocolInterface (\r
198 &Handle,\r
199 &gEfiCk505ClockPlatformInfoGuid,\r
200 EFI_NATIVE_INTERFACE,\r
201 ClockPolicy\r
202 );\r
203 ASSERT_EFI_ERROR(Status);\r
204\r
205}\r
206\r
207\r