EmulatorPkg: Change the cpu frequency to a non-zero value

[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformInitPei / PchInitPeim.c

/** @file\r
\r
  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
                                                                                   \r\r
\r
\r
Module Name:\r
\r
  PchInitPeim.c\r
\r
Abstract:\r
\r
  Do Early PCH platform initialization.\r
\r
\r
--*/\r
\r
#include "PlatformEarlyInit.h"\r
#include "Ppi/PchPlatformPolicy.h"\r
#include "PchRegs.h"\r
#include <Ppi/PchUsbPolicy.h>\r
#include "Ppi/PchInit.h"\r
#include <Library/PcdLib.h>\r
\r
EFI_GUID  gPchPlatformPolicyPpiGuid = PCH_PLATFORM_POLICY_PPI_GUID;\r
\r
#define MC_PMSTS_OFFSET                 0xC\r
\r
#define DEFAULT_BUS_INFO                0x2020\r
\r
\r
#define PCI_LPC_BASE    (0x8000F800)\r
#define PCI_LPC_REG(x)  (PCI_LPC_BASE + (x))\r
#define PCIEX_BASE_ADDRESS                        0xE0000000\r
#define PciD31F0RegBase                           PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
\r
VOID\r
PchPolicySetupInit (\r
  IN CONST EFI_PEI_SERVICES **PeiServices,\r
  IN SYSTEM_CONFIGURATION   *SystemConfiguration\r
  );\r
\r
VOID\r
PchInitInterrupt (\r
  IN SYSTEM_CONFIGURATION  *SystemConfiguration\r
  );\r
\r
EFI_STATUS\r
InstallPeiPchUsbPolicy (\r
  IN CONST  EFI_PEI_SERVICES  **PeiServices\r
  );\r
\r
#ifndef __GNUC__\r
#pragma warning (push)\r
#pragma warning (disable : 4245)\r
#pragma warning (pop)\r
#endif\r
\r
UINT8\r
ReadCmosBank1Byte (\r
  IN UINT8                      Address\r
  )\r
{\r
  UINT8                           Data;\r
\r
  IoWrite8(R_PCH_RTC_EXT_INDEX, Address);\r
  Data = IoRead8 (R_PCH_RTC_EXT_TARGET);\r
  return Data;\r
}\r
\r
VOID\r
WriteCmosBank1Byte (\r
  IN UINT8                     Address,\r
  IN UINT8                     Data\r
  )\r
{\r
  IoWrite8(R_PCH_RTC_EXT_INDEX, Address);\r
  IoWrite8(R_PCH_RTC_EXT_TARGET, Data);\r
}\r
\r
/**\r
  Turn off system if needed.\r
\r
  @param PeiServices Pointer to PEI Services\r
  @param CpuIo       Pointer to CPU I/O Protocol\r
\r
  @retval None.\r
\r
**/\r
VOID\r
CheckPowerOffNow (\r
  VOID\r
  )\r
{\r
  UINT16  Pm1Sts;\r
\r
  //\r
  // Read and check the ACPI registers\r
  //\r
  Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
  if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) {\r
    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);\r
    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);\r
    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN);\r
\r
    //\r
    // Should not return\r
    //\r
    CpuDeadLoop();\r
  }\r
}\r
\r
VOID\r
ClearPowerState (\r
  IN SYSTEM_CONFIGURATION        *SystemConfiguration\r
  )\r
{\r
  UINT8   Data8;\r
  UINT16  Data16;\r
  UINT32  Data32;\r
\r
  //\r
  // Check for PowerState option for AC power loss and program the chipset\r
  //\r
\r
  //\r
  // Clear PWROK (Set to Clear)\r
  //\r
  MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_PWROK_FLR);\r
\r
  //\r
  // Clear Power Failure Bit (Set to Clear)\r
  //\r
  // TODO: Check if it is OK to clear here\r
  //\r
\r
  MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR);\r
\r
  //\r
  // Clear the GPE and PM enable\r
  //\r
  IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_EN, (UINT16) 0x00);\r
  IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_EN, (UINT32) 0x00);\r
\r
  //\r
  // Halt the TCO timer\r
  //\r
  Data16 = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT);\r
  Data16 |= B_PCH_TCO_CNT_TMR_HLT;\r
  IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT, Data16);\r
\r
  //\r
  // if NMI_NOW_STS is set\r
  // NMI NOW bit is "Write '1' to clear"\r
  //\r
  Data8 = MmioRead8(ILB_BASE_ADDRESS + R_PCH_ILB_GNMI);\r
  if ((Data8 & B_PCH_ILB_GNMI_NMINS) == B_PCH_ILB_GNMI_NMINS) {\r
    MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_GNMI, B_PCH_ILB_GNMI_NMIN);\r
  }\r
\r
  //\r
  // Before we clear the TO status bit here we need to save the results in a CMOS bit for later use.\r
  //\r
  Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS);\r
  if ((Data32 & B_PCH_TCO_STS_SECOND_TO) == B_PCH_TCO_STS_SECOND_TO)\r
  {\r
#if (defined(HW_WATCHDOG_TIMER_SUPPORT) && (HW_WATCHDOG_TIMER_SUPPORT != 0))\r
    WriteCmosBank1Byte (\r
      EFI_CMOS_PERFORMANCE_FLAGS,\r
      ReadCmosBank1Byte (EFI_CMOS_PERFORMANCE_FLAGS) | B_CMOS_TCO_WDT_RESET\r
      );\r
#endif\r
  }\r
}\r
\r
/*++\r
\r
  Clear any SMI status or wake status left over from boot.\r
\r
**/\r
VOID\r
ClearSmiAndWake (\r
  VOID\r
  )\r
{\r
  UINT16  Pm1Sts;\r
  UINT32  Gpe0Sts;\r
  UINT32  SmiSts;\r
\r
  //\r
  // Read the ACPI registers\r
  //\r
  Pm1Sts  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
  Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);\r
  SmiSts  = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS);\r
\r
  //\r
  // Register Wake up reason for S4.  This information is used to notify\r
  // WinXp of wake up reason because S4 wake up path doesn't keep SCI.\r
  // This is important for Viiv(Quick resume) platform.\r
  //\r
\r
  //\r
  // First Clear CMOS S4 Wake up flag.\r
  //\r
  WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 0);\r
\r
  //\r
  // Check wake up reason and set CMOS accordingly.  Currently checks\r
  // Power button, USB, PS/2.\r
  // Note : PS/2 wake up is using GPI13 (IO_PME).  This must be changed depending\r
  // on board design.\r
  //\r
  if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) || (Gpe0Sts & (B_PCH_ACPI_GPE0a_STS_CORE_GPIO | B_PCH_ACPI_GPE0a_STS_SUS_GPIO))) {\r
    WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 1);\r
  }\r
\r
  //\r
  // Clear any SMI or wake state from the boot\r
  //\r
  Pm1Sts = (B_PCH_ACPI_PM1_STS_PRBTNOR | B_PCH_ACPI_PM1_STS_PWRBTN);\r
\r
  Gpe0Sts |=\r
    (\r
      B_PCH_ACPI_GPE0a_STS_CORE_GPIO |\r
      B_PCH_ACPI_GPE0a_STS_SUS_GPIO |\r
      B_PCH_ACPI_GPE0a_STS_PME_B0 |\r
      B_PCH_ACPI_GPE0a_STS_BATLOW |\r
      B_PCH_ACPI_GPE0a_STS_PCI_EXP |\r
      B_PCH_ACPI_GPE0a_STS_GUNIT_SCI |\r
      B_PCH_ACPI_GPE0a_STS_PUNIT_SCI |\r
      B_PCH_ACPI_GPE0a_STS_SWGPE |\r
      B_PCH_ACPI_GPE0a_STS_HOT_PLUG\r
    );\r
\r
  SmiSts |=\r
    (\r
      B_PCH_SMI_STS_SMBUS |\r
      B_PCH_SMI_STS_PERIODIC |\r
      B_PCH_SMI_STS_TCO |\r
      B_PCH_SMI_STS_SWSMI_TMR |\r
      B_PCH_SMI_STS_APM |\r
      B_PCH_SMI_STS_ON_SLP_EN |\r
      B_PCH_SMI_STS_BIOS\r
    );\r
\r
  //\r
  // Write them back\r
  //\r
  IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, Pm1Sts);\r
  IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS, Gpe0Sts);\r
  IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS, SmiSts);\r
}\r
\r
/**\r
  Issue PCI-E Secondary Bus Reset\r
\r
  @param Bus  Bus number of the bridge\r
  @param Dev  Devices number of the bridge\r
  @param Fun  Function number of the bridge\r
\r
  @retval EFI_SUCCESS\r
\r
**/\r
EFI_STATUS\r
PcieSecondaryBusReset (\r
  IN CONST EFI_PEI_SERVICES  **PeiServices,\r
  IN UINT8             Bus,\r
  IN UINT8             Dev,\r
  IN UINT8             Fun\r
  )\r
{\r
  EFI_PEI_STALL_PPI   *PeiStall;\r
  EFI_STATUS          Status;\r
\r
  Status = (**PeiServices).LocatePpi (\r
                             PeiServices,\r
                             &gEfiPeiStallPpiGuid,\r
                             0,\r
                             NULL,\r
                    (void **)&PeiStall\r
                             );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Issue secondary bus reset\r
  //\r
  MmPci16Or(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS);\r
\r
  //\r
  // Wait 1ms\r
  //\r
  PeiStall->Stall (PeiServices, PeiStall, 1000);\r
\r
\r
  //\r
  // Clear the reset bit\r
  // Note: The PCIe spec suggests 100ms delay between clearing this bit and accessing\r
  // the device's config space. Since we will not access the config space until we enter DXE\r
  // we don't put delay expressly here.\r
  //\r
  MmPci16And(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, ~(EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS));\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Provide hard reset PPI service.\r
  To generate full hard reset, write 0x0E to ICH RESET_GENERATOR_PORT (0xCF9).\r
\r
  @param PeiServices        General purpose services available to every PEIM.\r
\r
  @retval Not return        System reset occured.\r
  @retval EFI_DEVICE_ERROR  Device error, could not reset the system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
IchReset (\r
  IN CONST EFI_PEI_SERVICES          **PeiServices\r
  )\r
{\r
  IoWrite8 (\r
    R_PCH_RST_CNT,\r
    V_PCH_RST_CNT_HARDSTARTSTATE\r
    );\r
\r
  IoWrite8 (\r
    R_PCH_RST_CNT,\r
    V_PCH_RST_CNT_HARDRESET\r
    );\r
\r
  //\r
  // System reset occured, should never reach at this line.\r
  //\r
  ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);\r
  CpuDeadLoop();\r
\r
  return EFI_DEVICE_ERROR;\r
}\r
\r
VOID\r
PchPlatformLpcInit (\r
  IN  CONST EFI_PEI_SERVICES          **PeiServices,\r
  IN SYSTEM_CONFIGURATION       *SystemConfiguration\r
  )\r
{\r
  EFI_BOOT_MODE BootMode;\r
  UINT8         Data8;\r
  UINT16                Data16;\r
\r
  (*PeiServices)->GetBootMode(PeiServices, &BootMode);\r
\r
  if ((BootMode != BOOT_ON_S3_RESUME)) {\r
\r
    //\r
    // Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI\r
    //\r
    ClearSmiAndWake ();\r
  }\r
\r
  ClearPowerState (SystemConfiguration);\r
\r
  //\r
  // Need to set and clear SET bit (RTC_REGB Bit 7) as requested by the ICH EDS\r
  // early in POST after each power up directly after coin-cell battery insertion.\r
  // This is to avoid the UIP bit (RTC_REGA Bit 7) from stuck at "1".\r
  // The UIP bit status may be polled by software (i.e ME FW) during POST.\r
  //\r
  if (MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) {\r
  	//\r
    // Set and clear SET bit in RTC_REGB\r
    //\r
    IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB);\r
    Data8 = IoRead8(R_PCH_RTC_TARGET);\r
    Data8 |= B_PCH_RTC_REGISTERB_SET;\r
    IoWrite8(R_PCH_RTC_TARGET, Data8);\r
\r
    IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB);\r
    Data8 &= (~B_PCH_RTC_REGISTERB_SET);\r
    IoWrite8(R_PCH_RTC_TARGET, Data8);\r
\r
    //\r
    // Clear the UIP bit in RTC_REGA\r
    //\r
    IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERA);\r
    IoWrite8(R_PCH_RTC_TARGET, 0x00);\r
  }\r
\r
  //\r
  // Disable SERR NMI and IOCHK# NMI in port 61\r
  //\r
  Data8 = IoRead8 (R_PCH_NMI_SC);\r
  IoWrite8(R_PCH_NMI_SC, (UINT8) (Data8 | B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN));\r
\r
  //\r
  // Enable Bus Master, I/O, Mem, and SERR on LPC bridge\r
  //\r
  Data16 = PchLpcPciCfg16 (R_PCH_LPC_COMMAND);\r
  MmioWrite16 (\r
    MmPciAddress (0,\r
      DEFAULT_PCI_BUS_NUMBER_PCH,\r
      PCI_DEVICE_NUMBER_PCH_LPC,\r
      PCI_FUNCTION_NUMBER_PCH_LPC,\r
      R_PCH_LPC_COMMAND\r
    ),\r
    (Data16 |\r
     B_PCH_LPC_COMMAND_IOSE |\r
     B_PCH_LPC_COMMAND_MSE |\r
     B_PCH_LPC_COMMAND_BME |\r
     B_PCH_LPC_COMMAND_SERR_EN)\r
  );\r
\r
  //\r
  // Set Stretch S4 to 1-2s per marketing request.\r
  // Note: This register is powered by RTC well.\r
  //\r
  MmioAndThenOr8 (\r
    PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 ,\r
    (UINT8) (~B_PCH_PMC_GEN_PMCON_SLP_S4_MAW),\r
    (UINT8) (B_PCH_PMC_GEN_PMCON_SLP_S4_ASE | V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S)\r
    );\r
\r
}\r
\r
#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3 // UART IRQ3 Enable\r
\r
VOID\r
UARTInit (\r
  IN SYSTEM_CONFIGURATION        *SystemConfiguration\r
  )\r
{\r
  if (0) { // for fix cr4 issue\r
    //\r
    // Program and enable PMC Base.\r
    //\r
    IoWrite32 (0xCF8,  PCI_LPC_REG(R_PCH_LPC_PMC_BASE));\r
    IoWrite32 (0xCFC,  (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));\r
\r
    if( (SystemConfiguration->PcuUart1 == 1) &&\r
        (SystemConfiguration->LpssHsuart0Enabled == 0)){\r
      //\r
      // Enable COM1 for debug message output.\r
      //\r
      MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, BIT24);\r
\r
      //\r
      //Enable internal UART3 port(COM1)\r
      //\r
      MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
      MmioOr32 (IO_BASE_ADDRESS + 0x0520, 0x01); // UART3_RXD-L\r
      MmioOr32 (IO_BASE_ADDRESS + 0x0530, 0x01); // UART3_TXD-0\r
      MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);\r
    } else {\r
    	//\r
      //Disable UART3(COM1)\r
      //\r
      MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
      MmioAnd32 (IO_BASE_ADDRESS + 0x0520, ~(UINT32)0x07);\r
      MmioAnd32 (IO_BASE_ADDRESS + 0x0530, ~(UINT32)0x07);\r
      MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) ~B_PCH_LPC_UART_CTRL_COM1_EN);\r
\r
\r
      if (SystemConfiguration->LpssHsuart0Enabled == 1){\r
        //\r
        //Valleyview BIOS Specification Vol2,17.2\r