[mirror_edk2.git] / ArmPkg / ArmPkg.dec

#/** @file\r
# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.\r
#\r
#    This program and the accompanying materials\r
#    are licensed and made available under the terms and conditions of the BSD License\r
#    which accompanies this distribution. The full text of the license may be found at\r
#    http://opensource.org/licenses/bsd-license.php\r
#\r
#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#**/\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = ArmPkg\r
  PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
  PACKAGE_VERSION                = 0.1\r
\r
################################################################################\r
#\r
# Include Section - list of Include Paths that are provided by this package.\r
#                   Comments are used for Keywords and Module Types.\r
#\r
# Supported Module Types:\r
#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
#\r
################################################################################\r
[Includes.common]\r
  Include                        # Root include for the package\r
\r
[LibraryClasses.common]\r
  ArmLib|Include/Library/ArmLib.h\r
  ArmMmuLib|Include/Library/ArmMmuLib.h\r
  SemihostLib|Include/Library/Semihosting.h\r
  DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
  ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
  ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
  ArmSvcLib|Include/Library/ArmSvcLib.h\r
\r
[Guids.common]\r
  gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
\r
  ## ARM MPCore table\r
  # Include/Guid/ArmMpCoreInfo.h\r
  gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
\r
  gArmGicDxeFileGuid = { 0xde371f7c, 0xdec4, 0x4d21, { 0xad, 0xf1, 0x59, 0x3a, 0xbc, 0xc1, 0x58, 0x82 } }\r
\r
[Ppis]\r
  ## Include/Ppi/ArmMpCoreInfo.h\r
  gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
\r
[PcdsFeatureFlag.common]\r
  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
\r
  # On ARM Architecture with the Security Extension, the address for the\r
  # Vector Table can be mapped anywhere in the memory map. It means we can\r
  # point the Exception Vector Table to its location in CpuDxe.\r
  # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)\r
  gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r
  # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
  # it has been configured by the CPU DXE\r
  gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
\r
  # Define if the spin-table mechanism is used by the secondary cores when booting\r
  # Linux (instead of PSCI)\r
  gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033\r
\r
  # Define if the GICv3 controller should use the GICv2 legacy\r
  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
\r
[PcdsFeatureFlag.ARM]\r
  # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
  # TRUE may be appropriate to fix performance problems if you don't care about\r
  # hardware coherency (i.e., no virtualization or cache coherent DMA)\r
  gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r
\r
[PcdsFixedAtBuild.common]\r
  gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
\r
  # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
  # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
  gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
\r
  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r
  gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
  #\r
  # ARM Secure Firmware PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r
  gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
  gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r
  gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
\r
  #\r
  # ARM Hypervisor Firmware PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r
  gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
  gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
  gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r
\r
  # Use ClusterId + CoreId to identify the PrimaryCore\r
  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
  # The Primary Core is ClusterId[0] & CoreId[0]\r
  gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
\r
  #\r
  # ARM L2x0 PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
\r
  #\r
  # ARM Normal (or Non Secure) Firmware PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
  gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
\r
  #\r
  # Value to add to a host address to obtain a device address, using\r
  # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r
  # means we can rely on truncation on overflow to specify negative\r
  # offsets.\r
  #\r
  gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r
\r
[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
  gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
  gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
\r
[PcdsFixedAtBuild.ARM]\r
  #\r
  # ARM Security Extension\r
  #\r
\r
  # Secure Configuration Register\r
  # - BIT0 : NS - Non Secure bit\r
  # - BIT1 : IRQ Handler\r
  # - BIT2 : FIQ Handler\r
  # - BIT3 : EA - External Abort\r
  # - BIT4 : FW - F bit writable\r
  # - BIT5 : AW - A bit writable\r
  # - BIT6 : nET - Not Early Termination\r
  # - BIT7 : SCD - Secure Monitor Call Disable\r
  # - BIT8 : HCE - Hyp Call enable\r
  # - BIT9 : SIF - Secure Instruction Fetch\r
  # 0x31 = NS | EA | FW\r
  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
\r
  # By default we do not do a transition to non-secure mode\r
  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
\r
  # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
  gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
\r
  # If the fixed FDT address is not available, then it should be loaded below the kernel.\r
  # The recommendation from the Linux kernel is to have the FDT below 16KB.\r
  # (see the kernel doc: Documentation/arm/Booting)\r
  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r
  # The FDT blob must be loaded at a 64bit aligned address.\r
  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
\r
  # Non Secure Access Control Register\r
  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
  # 0xC00 = cp10 | cp11\r
  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
\r
[PcdsFixedAtBuild.AARCH64]\r
  #\r
  # AArch64 Security Extension\r
  #\r
\r
  # Secure Configuration Register\r
  # - BIT0 : NS - Non Secure bit\r
  # - BIT1 : IRQ Handler\r
  # - BIT2 : FIQ Handler\r
  # - BIT3 : EA - External Abort\r
  # - BIT4 : FW - F bit writable\r
  # - BIT5 : AW - A bit writable\r
  # - BIT6 : nET - Not Early Termination\r
  # - BIT7 : SCD - Secure Monitor Call Disable\r
  # - BIT8 : HCE - Hyp Call enable\r
  # - BIT9 : SIF - Secure Instruction Fetch\r
  # - BIT10: RW -  Register width control for lower exception levels\r
  # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
  # - BIT12: TWI - Trap WFI\r
  # - BIT13: TWE - Trap WFE\r
  # 0x501 = NS | HCE | RW\r
  gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
\r
  # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
  #        Mode Description              Bits\r
  # NS EL2 SP2 all interrupts disabled =  0x3c9\r
  # NS EL1 SP1 all interrupts disabled =  0x3c5\r
  # Other modes include using SP0 or switching to Aarch32, but these are\r
  # not currently supported.\r
  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
  # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
  # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
  # (see the kernel doc: Documentation/arm64/booting.txt)\r
  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
  # The FDT blob must be loaded at a 2MB aligned address.\r
  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
\r
\r
#\r
# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
# redefined when using UEFI in a context of virtual machine.\r
#\r
[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
\r
  # System Memory (DRAM): These PCDs define the region of in-built system memory\r
  # Some platforms can get DRAM extensions, these additional regions may be\r
  # declared to UEFI using separate resource descriptor HOBs\r
  gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
  gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
\r
[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
  #\r
  # ARM Architectural Timer\r
  #\r
  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
\r
  # ARM Architectural Timer Interrupt(GIC PPI) numbers\r
  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
\r
  #\r
  # ARM Generic Watchdog\r
  #\r
\r
  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r
  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r
  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
\r
  #\r
  # ARM Generic Interrupt Controller\r
  #\r
  gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r
  # Base address for the GIC Redistributor region that contains the boot CPU\r
  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r
  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r
  gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
\r
  #\r
  # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
  # Note that "IO" is just another MMIO range that simulates IO space; there\r
  # are no special instructions to access it.\r
  #\r
  # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
  # specific to their containing address spaces. In order to get the physical\r
  # address for the CPU, for a given access, the respective translation value\r
  # has to be added.\r
  #\r
  # The translations always have to be initialized like this, using UINT64:\r
  #\r
  #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space\r
  #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
  #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
  #\r
  #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;\r
  #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
  #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
  #\r
  # because (a) the target address space (ie. the cpu-physical space) is\r
  # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
  # arithmetic.\r
  #\r
  # Accordingly, the translation itself needs to be implemented as:\r
  #\r
  #   UINT64 UntranslatedIoAddress;     // input parameter\r
  #   UINT32 UntranslatedMmio32Address; // input parameter\r
  #   UINT64 UntranslatedMmio64Address; // input parameter\r
  #\r
  #   UINT64 TranslatedIoAddress;       // output parameter\r
  #   UINT64 TranslatedMmio32Address;   // output parameter\r
  #   UINT64 TranslatedMmio64Address;   // output parameter\r
  #\r
  #   TranslatedIoAddress     = UntranslatedIoAddress +\r
  #                             PcdPciIoTranslation;\r
  #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
  #                             PcdPciMmio32Translation;\r
  #   TranslatedMmio64Address = UntranslatedMmio64Address +\r
  #                             PcdPciMmio64Translation;\r
  #\r
  #  The modular arithmetic performed in UINT64 ensures that the translation\r
  #  works correctly regardless of the relation between IoCpuBase and\r
  #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
  #  PcdPciMmio64Base.\r
  #\r
  gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
  gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
  gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
  gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
  gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
  gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
  gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
  gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
  gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
\r
  #\r
  # Inclusive range of allowed PCI buses.\r
  #\r
  gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
  gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r
Commit	Line	Data
	1	#/** @file\r
	2	# ARM processor package.\r
	3	#\r
	4	# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
	5	# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.\r
	6	#\r
	7	# This program and the accompanying materials\r
	8	# are licensed and made available under the terms and conditions of the BSD License\r
	9	# which accompanies this distribution. The full text of the license may be found at\r
	10	# http://opensource.org/licenses/bsd-license.php\r
	11	#\r
	12	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	#\r
	15	#**/\r
	16	\r
	17	[Defines]\r
	18	DEC_SPECIFICATION = 0x00010005\r
	19	PACKAGE_NAME = ArmPkg\r
	20	PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
	21	PACKAGE_VERSION = 0.1\r
	22	\r
	23	################################################################################\r
	24	#\r
	25	# Include Section - list of Include Paths that are provided by this package.\r
	26	# Comments are used for Keywords and Module Types.\r
	27	#\r
	28	# Supported Module Types:\r
	29	# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
	30	#\r
	31	################################################################################\r
	32	[Includes.common]\r
	33	Include # Root include for the package\r
	34	\r
	35	[LibraryClasses.common]\r
	36	ArmLib\|Include/Library/ArmLib.h\r
	37	ArmMmuLib\|Include/Library/ArmMmuLib.h\r
	38	SemihostLib\|Include/Library/Semihosting.h\r
	39	DefaultExceptionHandlerLib\|Include/Library/DefaultExceptionHandlerLib.h\r
	40	ArmDisassemblerLib\|Include/Library/ArmDisassemblerLib.h\r
	41	ArmGicArchLib\|Include/Library/ArmGicArchLib.h\r
	42	ArmSvcLib\|Include/Library/ArmSvcLib.h\r
	43	\r
	44	[Guids.common]\r
	45	gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
	46	\r
	47	## ARM MPCore table\r
	48	# Include/Guid/ArmMpCoreInfo.h\r
	49	gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
	50	\r
	51	gArmGicDxeFileGuid = { 0xde371f7c, 0xdec4, 0x4d21, { 0xad, 0xf1, 0x59, 0x3a, 0xbc, 0xc1, 0x58, 0x82 } }\r
	52	\r
	53	[Ppis]\r
	54	## Include/Ppi/ArmMpCoreInfo.h\r
	55	gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
	56	\r
	57	[PcdsFeatureFlag.common]\r
	58	gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport\|FALSE\|BOOLEAN\|0x00000001\r
	59	\r
	60	# On ARM Architecture with the Security Extension, the address for the\r
	61	# Vector Table can be mapped anywhere in the memory map. It means we can\r
	62	# point the Exception Vector Table to its location in CpuDxe.\r
	63	# By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r
	64	gArmTokenSpaceGuid.PcdRelocateVectorTable\|TRUE\|BOOLEAN\|0x00000022\r
	65	# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
	66	# it has been configured by the CPU DXE\r
	67	gArmTokenSpaceGuid.PcdDebuggerExceptionSupport\|FALSE\|BOOLEAN\|0x00000032\r
	68	\r
	69	# Define if the spin-table mechanism is used by the secondary cores when booting\r
	70	# Linux (instead of PSCI)\r
	71	gArmTokenSpaceGuid.PcdArmLinuxSpinTable\|FALSE\|BOOLEAN\|0x00000033\r
	72	\r
	73	# Define if the GICv3 controller should use the GICv2 legacy\r
	74	gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy\|FALSE\|BOOLEAN\|0x00000042\r
	75	\r
	76	[PcdsFeatureFlag.ARM]\r
	77	# Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
	78	# TRUE may be appropriate to fix performance problems if you don't care about\r
	79	# hardware coherency (i.e., no virtualization or cache coherent DMA)\r
	80	gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride\|FALSE\|BOOLEAN\|0x00000043\r
	81	\r
	82	[PcdsFixedAtBuild.common]\r
	83	gArmTokenSpaceGuid.PcdTrustzoneSupport\|FALSE\|BOOLEAN\|0x00000006\r
	84	\r
	85	# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
	86	# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
	87	gArmTokenSpaceGuid.PcdVFPEnabled\|0\|UINT32\|0x00000024\r
	88	\r
	89	gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\|0xffff0000\|UINT64\|0x00000004\r
	90	gArmTokenSpaceGuid.PcdCpuResetAddress\|0x00000000\|UINT32\|0x00000005\r
	91	\r
	92	#\r
	93	# ARM Secure Firmware PCDs\r
	94	#\r
	95	gArmTokenSpaceGuid.PcdSecureFdBaseAddress\|0\|UINT64\|0x00000015\r
	96	gArmTokenSpaceGuid.PcdSecureFdSize\|0\|UINT32\|0x00000016\r
	97	gArmTokenSpaceGuid.PcdSecureFvBaseAddress\|0x0\|UINT64\|0x0000002F\r
	98	gArmTokenSpaceGuid.PcdSecureFvSize\|0x0\|UINT32\|0x00000030\r
	99	\r
	100	#\r
	101	# ARM Hypervisor Firmware PCDs\r
	102	#\r
	103	gArmTokenSpaceGuid.PcdHypFdBaseAddress\|0\|UINT32\|0x0000003A\r
	104	gArmTokenSpaceGuid.PcdHypFdSize\|0\|UINT32\|0x0000003B\r
	105	gArmTokenSpaceGuid.PcdHypFvBaseAddress\|0\|UINT32\|0x0000003C\r
	106	gArmTokenSpaceGuid.PcdHypFvSize\|0\|UINT32\|0x0000003D\r
	107	\r
	108	# Use ClusterId + CoreId to identify the PrimaryCore\r
	109	gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\|0xF03\|UINT32\|0x00000031\r
	110	# The Primary Core is ClusterId[0] & CoreId[0]\r
	111	gArmTokenSpaceGuid.PcdArmPrimaryCore\|0\|UINT32\|0x00000037\r
	112	\r
	113	#\r
	114	# ARM L2x0 PCDs\r
	115	#\r
	116	gArmTokenSpaceGuid.PcdL2x0ControllerBase\|0\|UINT32\|0x0000001B\r
	117	\r
	118	#\r
	119	# ARM Normal (or Non Secure) Firmware PCDs\r
	120	#\r
	121	gArmTokenSpaceGuid.PcdFdSize\|0\|UINT32\|0x0000002C\r
	122	gArmTokenSpaceGuid.PcdFvSize\|0\|UINT32\|0x0000002E\r
	123	\r
	124	#\r
	125	# Value to add to a host address to obtain a device address, using\r
	126	# unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r
	127	# means we can rely on truncation on overflow to specify negative\r
	128	# offsets.\r
	129	#\r
	130	gArmTokenSpaceGuid.PcdArmDmaDeviceOffset\|0x0\|UINT64\|0x0000044\r
	131	\r
	132	[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
	133	gArmTokenSpaceGuid.PcdFdBaseAddress\|0\|UINT64\|0x0000002B\r
	134	gArmTokenSpaceGuid.PcdFvBaseAddress\|0\|UINT64\|0x0000002D\r
	135	\r
	136	[PcdsFixedAtBuild.ARM]\r
	137	#\r
	138	# ARM Security Extension\r
	139	#\r
	140	\r
	141	# Secure Configuration Register\r
	142	# - BIT0 : NS - Non Secure bit\r
	143	# - BIT1 : IRQ Handler\r
	144	# - BIT2 : FIQ Handler\r
	145	# - BIT3 : EA - External Abort\r
	146	# - BIT4 : FW - F bit writable\r
	147	# - BIT5 : AW - A bit writable\r
	148	# - BIT6 : nET - Not Early Termination\r
	149	# - BIT7 : SCD - Secure Monitor Call Disable\r
	150	# - BIT8 : HCE - Hyp Call enable\r
	151	# - BIT9 : SIF - Secure Instruction Fetch\r
	152	# 0x31 = NS \| EA \| FW\r
	153	gArmTokenSpaceGuid.PcdArmScr\|0x31\|UINT32\|0x00000038\r
	154	\r
	155	# By default we do not do a transition to non-secure mode\r
	156	gArmTokenSpaceGuid.PcdArmNonSecModeTransition\|0x0\|UINT32\|0x0000003E\r
	157	\r
	158	# The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
	159	gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset\|0x4000\|UINT32\|0x00000020\r
	160	\r
	161	# If the fixed FDT address is not available, then it should be loaded below the kernel.\r
	162	# The recommendation from the Linux kernel is to have the FDT below 16KB.\r
	163	# (see the kernel doc: Documentation/arm/Booting)\r
	164	gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset\|0x4000\|UINT32\|0x00000023\r
	165	# The FDT blob must be loaded at a 64bit aligned address.\r
	166	gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment\|0x8\|UINT32\|0x00000026\r
	167	\r
	168	# Non Secure Access Control Register\r
	169	# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
	170	# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
	171	# - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
	172	# - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
	173	# 0xC00 = cp10 \| cp11\r
	174	gArmTokenSpaceGuid.PcdArmNsacr\|0xC00\|UINT32\|0x00000039\r
	175	\r
	176	[PcdsFixedAtBuild.AARCH64]\r
	177	#\r
	178	# AArch64 Security Extension\r
	179	#\r
	180	\r
	181	# Secure Configuration Register\r
	182	# - BIT0 : NS - Non Secure bit\r
	183	# - BIT1 : IRQ Handler\r
	184	# - BIT2 : FIQ Handler\r
	185	# - BIT3 : EA - External Abort\r
	186	# - BIT4 : FW - F bit writable\r
	187	# - BIT5 : AW - A bit writable\r
	188	# - BIT6 : nET - Not Early Termination\r
	189	# - BIT7 : SCD - Secure Monitor Call Disable\r
	190	# - BIT8 : HCE - Hyp Call enable\r
	191	# - BIT9 : SIF - Secure Instruction Fetch\r
	192	# - BIT10: RW - Register width control for lower exception levels\r
	193	# - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
	194	# - BIT12: TWI - Trap WFI\r
	195	# - BIT13: TWE - Trap WFE\r
	196	# 0x501 = NS \| HCE \| RW\r
	197	gArmTokenSpaceGuid.PcdArmScr\|0x501\|UINT32\|0x00000038\r
	198	\r
	199	# By default we do transition to EL2 non-secure mode with Stack for EL2.\r
	200	# Mode Description Bits\r
	201	# NS EL2 SP2 all interrupts disabled = 0x3c9\r
	202	# NS EL1 SP1 all interrupts disabled = 0x3c5\r
	203	# Other modes include using SP0 or switching to Aarch32, but these are\r
	204	# not currently supported.\r
	205	gArmTokenSpaceGuid.PcdArmNonSecModeTransition\|0x3c9\|UINT32\|0x0000003E\r
	206	# If the fixed FDT address is not available, then it should be loaded above the kernel.\r
	207	# The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
	208	# (see the kernel doc: Documentation/arm64/booting.txt)\r
	209	gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset\|0x20000000\|UINT32\|0x00000023\r
	210	# The FDT blob must be loaded at a 2MB aligned address.\r
	211	gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment\|0x00200000\|UINT32\|0x00000026\r
	212	\r
	213	\r
	214	#\r
	215	# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
	216	# redefined when using UEFI in a context of virtual machine.\r
	217	#\r
	218	[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
	219	\r
	220	# System Memory (DRAM): These PCDs define the region of in-built system memory\r
	221	# Some platforms can get DRAM extensions, these additional regions may be\r
	222	# declared to UEFI using separate resource descriptor HOBs\r
	223	gArmTokenSpaceGuid.PcdSystemMemoryBase\|0\|UINT64\|0x00000029\r
	224	gArmTokenSpaceGuid.PcdSystemMemorySize\|0\|UINT64\|0x0000002A\r
	225	\r
	226	[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
	227	#\r
	228	# ARM Architectural Timer\r
	229	#\r
	230	gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz\|0\|UINT32\|0x00000034\r
	231	\r
	232	# ARM Architectural Timer Interrupt(GIC PPI) numbers\r
	233	gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum\|29\|UINT32\|0x00000035\r
	234	gArmTokenSpaceGuid.PcdArmArchTimerIntrNum\|30\|UINT32\|0x00000036\r
	235	gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum\|26\|UINT32\|0x00000040\r
	236	gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum\|27\|UINT32\|0x00000041\r
	237	\r
	238	#\r
	239	# ARM Generic Watchdog\r
	240	#\r
	241	\r
	242	gArmTokenSpaceGuid.PcdGenericWatchdogControlBase\|0x2A440000\|UINT64\|0x00000007\r
	243	gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase\|0x2A450000\|UINT64\|0x00000008\r
	244	gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum\|93\|UINT32\|0x00000009\r
	245	\r
	246	#\r
	247	# ARM Generic Interrupt Controller\r
	248	#\r
	249	gArmTokenSpaceGuid.PcdGicDistributorBase\|0\|UINT64\|0x0000000C\r
	250	# Base address for the GIC Redistributor region that contains the boot CPU\r
	251	gArmTokenSpaceGuid.PcdGicRedistributorsBase\|0\|UINT64\|0x0000000E\r
	252	gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\|0\|UINT64\|0x0000000D\r
	253	gArmTokenSpaceGuid.PcdGicSgiIntId\|0\|UINT32\|0x00000025\r
	254	\r
	255	#\r
	256	# Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
	257	# Note that "IO" is just another MMIO range that simulates IO space; there\r
	258	# are no special instructions to access it.\r
	259	#\r
	260	# The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
	261	# specific to their containing address spaces. In order to get the physical\r
	262	# address for the CPU, for a given access, the respective translation value\r
	263	# has to be added.\r
	264	#\r
	265	# The translations always have to be initialized like this, using UINT64:\r
	266	#\r
	267	# UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
	268	# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
	269	# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
	270	#\r
	271	# PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
	272	# PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
	273	# PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
	274	#\r
	275	# because (a) the target address space (ie. the cpu-physical space) is\r
	276	# 64-bit, and (b) the translation values are meant as offsets for modular\r
	277	# arithmetic.\r
	278	#\r
	279	# Accordingly, the translation itself needs to be implemented as:\r
	280	#\r
	281	# UINT64 UntranslatedIoAddress; // input parameter\r
	282	# UINT32 UntranslatedMmio32Address; // input parameter\r
	283	# UINT64 UntranslatedMmio64Address; // input parameter\r
	284	#\r
	285	# UINT64 TranslatedIoAddress; // output parameter\r
	286	# UINT64 TranslatedMmio32Address; // output parameter\r
	287	# UINT64 TranslatedMmio64Address; // output parameter\r
	288	#\r
	289	# TranslatedIoAddress = UntranslatedIoAddress +\r
	290	# PcdPciIoTranslation;\r
	291	# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
	292	# PcdPciMmio32Translation;\r
	293	# TranslatedMmio64Address = UntranslatedMmio64Address +\r
	294	# PcdPciMmio64Translation;\r
	295	#\r
	296	# The modular arithmetic performed in UINT64 ensures that the translation\r
	297	# works correctly regardless of the relation between IoCpuBase and\r
	298	# PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
	299	# PcdPciMmio64Base.\r
	300	#\r
	301	gArmTokenSpaceGuid.PcdPciIoBase\|0x0\|UINT64\|0x00000050\r
	302	gArmTokenSpaceGuid.PcdPciIoSize\|0x0\|UINT64\|0x00000051\r
	303	gArmTokenSpaceGuid.PcdPciIoTranslation\|0x0\|UINT64\|0x00000052\r
	304	gArmTokenSpaceGuid.PcdPciMmio32Base\|0x0\|UINT32\|0x00000053\r
	305	gArmTokenSpaceGuid.PcdPciMmio32Size\|0x0\|UINT32\|0x00000054\r
	306	gArmTokenSpaceGuid.PcdPciMmio32Translation\|0x0\|UINT64\|0x00000055\r
	307	gArmTokenSpaceGuid.PcdPciMmio64Base\|0x0\|UINT64\|0x00000056\r
	308	gArmTokenSpaceGuid.PcdPciMmio64Size\|0x0\|UINT64\|0x00000057\r
	309	gArmTokenSpaceGuid.PcdPciMmio64Translation\|0x0\|UINT64\|0x00000058\r
	310	\r
	311	#\r
	312	# Inclusive range of allowed PCI buses.\r
	313	#\r
	314	gArmTokenSpaceGuid.PcdPciBusMin\|0x0\|UINT32\|0x00000059\r
	315	gArmTokenSpaceGuid.PcdPciBusMax\|0x0\|UINT32\|0x0000005A\r