ArmPkg/TimerDxe: Add ISB for timer compare value reload
authorHeyi Guo <heyi.guo@linaro.org>
Thu, 15 Mar 2018 07:17:43 +0000 (15:17 +0800)
committerArd Biesheuvel <ard.biesheuvel@linaro.org>
Thu, 15 Mar 2018 08:07:14 +0000 (08:07 +0000)
commitac9b530e6b47c0957345e421b618d8bdd2bf21cf
tree53a8feec5f18fc9773412f4dce8f639d8737f97a
parentb3fa393f477a12fe0e1aedb36395ca9b345ae110
ArmPkg/TimerDxe: Add ISB for timer compare value reload

If timer interrupt is level sensitive, reloading timer compare
register has a side effect of clearing GIC pending status, so a "ISB"
is needed to make sure this instruction is executed before enabling
CPU IRQ, or else we may get spurious timer interrupts.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
ArmPkg/Drivers/TimerDxe/TimerDxe.c