ArmPkg/TimerDxe: Add ISB for timer compare value reload

If timer interrupt is level sensitive, reloading timer compare
register has a side effect of clearing GIC pending status, so a "ISB"
is needed to make sure this instruction is executed before enabling
CPU IRQ, or else we may get spurious timer interrupts.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
index 33d7c922221fa18c8f1ac7353487a60c77437d0c..a3202fa056f3026cd1c6ab3781649923d848d62c 100644 (file)
--- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c
+++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
@@ -338,6 +338,7 @@ TimerInterruptHandler (
     // Set next compare value\r
     ArmGenericTimerSetCompareVal (CompareValue);\r
     ArmGenericTimerEnableTimer ();\r
+    ArmInstructionSynchronizationBarrier ();\r
   }\r
 \r
   gBS->RestoreTPL (OriginalTPL);\r