[mirror_edk2.git] / PerformancePkg / Library / TscTimerLib / TscTimerLibShare.c

/** @file\r
  The Timer Library implementation which uses the Time Stamp Counter in the processor.\r
\r
  For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);\r
    for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);\r
    for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);\r
    for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);\r
    for Intel Atom processors (family [06H], display_model [1CH]):\r
  the time-stamp counter increments at a constant rate.\r
  That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by\r
  the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may\r
  differ from the maximum qualified frequency of the processor.\r
\r
  The specific processor configuration determines the behavior. Constant TSC behavior ensures that the\r
  duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if\r
  the processor core changes frequency. This is the architectural behavior moving forward.\r
\r
  A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].\r
\r
  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution. The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "TscTimerLibInternal.h"\r
\r
/**  Calculate TSC frequency.\r
\r
  The TSC counting frequency is determined by comparing how far it counts\r
  during a 1ms period as determined by the ACPI timer. The ACPI timer is\r
  used because it counts at a known frequency.\r
  If ACPI I/O space not enabled, this function will enable it. Then the\r
  TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.\r
  The TSC is then sampled again. The difference multiplied by 1000 is the TSC\r
  frequency. There will be a small error because of the overhead of reading\r
  the ACPI timer. An attempt is made to determine and compensate for this error.\r
\r
  @return The number of TSC counts per second.\r
\r
**/\r
UINT64\r
InternalCalculateTscFrequency (\r
  VOID\r
  )\r
{\r
  UINT64      StartTSC;\r
  UINT64      EndTSC;\r
  UINT32      TimerAddr;\r
  UINT32      Ticks;\r
  UINT64      TscFrequency;\r
\r
  //\r
  // If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.\r
  //\r
  if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {\r
    PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));\r
    PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);\r
  }\r
\r
  //\r
  // ACPI I/O space should be enabled now, locate the ACPI Timer.\r
  // ACPI I/O base address maybe have be initialized by other driver with different value,\r
  // So get it from PCI space directly.\r
  //\r
  TimerAddr = ((PciRead16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE))) & B_ICH_LPC_ACPI_BASE_BAR) + R_ACPI_PM1_TMR;\r
  Ticks    = IoRead32 (TimerAddr) + (3579);   // Set Ticks to 1ms in the future\r
  StartTSC = AsmReadTsc();                    // Get base value for the TSC\r
  //\r
  // Wait until the ACPI timer has counted 1ms.\r
  // Timer wrap-arounds are handled correctly by this function.\r
  // When the current ACPI timer value is greater than 'Ticks', the while loop will exit.\r
  //\r
  while (((Ticks - IoRead32 (TimerAddr)) & BIT23) == 0) {\r
    CpuPause();\r
  }\r
  EndTSC = AsmReadTsc();    // TSC value 1ms later\r
\r
  TscFrequency =   MultU64x32 (\r
                      (EndTSC - StartTSC),    // Number of TSC counts in 1ms\r
                      1000                    // Number of ms in a second\r
                    );\r
\r
  return TscFrequency;\r
}\r
\r
/**  Stalls the CPU for at least the given number of ticks.\r
\r
  Stalls the CPU for at least the given number of ticks. It's invoked by\r
  MicroSecondDelay() and NanoSecondDelay().\r
\r
  @param[in]  Delay     A period of time to delay in ticks.\r
\r
**/\r
VOID\r
InternalX86Delay (\r
  IN      UINT64                    Delay\r
  )\r
{\r
  UINT64                             Ticks;\r
\r
  //\r
  // The target timer count is calculated here\r
  //\r
  Ticks = AsmReadTsc() + Delay;\r
\r
  //\r
  // Wait until time out\r
  // Timer wrap-arounds are NOT handled correctly by this function.\r
  // Thus, this function must be called within 10 years of reset since\r
  // Intel guarantees a minimum of 10 years before the TSC wraps.\r
  //\r
  while (AsmReadTsc() <= Ticks) CpuPause();\r
}\r
\r
/**  Stalls the CPU for at least the specified number of MicroSeconds.\r
\r
  @param[in]  MicroSeconds  The minimum number of microseconds to delay.\r
\r
  @return The value of MicroSeconds input.\r
\r
**/\r
UINTN\r
EFIAPI\r
MicroSecondDelay (\r
  IN      UINTN                     MicroSeconds\r
  )\r
{\r
  InternalX86Delay (\r
    DivU64x32 (\r
      MultU64x64 (\r
        InternalGetTscFrequency (),\r
        MicroSeconds\r
      ),\r
      1000000u\r
    )\r
  );\r
  return MicroSeconds;\r
}\r
\r
/**  Stalls the CPU for at least the specified number of NanoSeconds.\r
\r
  @param[in]  NanoSeconds The minimum number of nanoseconds to delay.\r
\r
  @return The value of NanoSeconds input.\r
\r
**/\r
UINTN\r
EFIAPI\r
NanoSecondDelay (\r
  IN      UINTN                     NanoSeconds\r
  )\r
{\r
  InternalX86Delay (\r
    DivU64x32 (\r
      MultU64x32 (\r
        InternalGetTscFrequency (),\r
        (UINT32)NanoSeconds\r
      ),\r
    1000000000u\r
    )\r
  );\r
  return NanoSeconds;\r
}\r
\r
/**  Retrieves the current value of the 64-bit free running Time-Stamp counter.\r
\r
  The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,\r
  Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and\r
  later processors) is a 64-bit counter that is set to 0 following a RESET of\r
  the processor.  Following a RESET, the counter increments even when the\r
  processor is halted by the HLT instruction or the external STPCLK# pin. Note\r
  that the assertion of the external DPSLP# pin may cause the time-stamp\r
  counter to stop.\r
\r
  The properties of the counter can be retrieved by the\r
  GetPerformanceCounterProperties() function.\r
\r
  @return The current value of the free running performance counter.\r
\r
**/\r
UINT64\r
EFIAPI\r
GetPerformanceCounter (\r
  VOID\r
  )\r
{\r
  return AsmReadTsc();\r
}\r
\r
/**  Retrieves the 64-bit frequency in Hz and the range of performance counter\r
  values.\r
\r
  If StartValue is not NULL, then the value that the performance counter starts\r
  with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value\r
  that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in\r
  EndValue.\r
\r
  The 64-bit frequency of the performance counter, in Hz, is always returned.\r
  To determine average processor clock frequency, Intel recommends the use of\r
  EMON logic to count processor core clocks over the period of time for which\r
  the average is required.\r
\r
\r
  @param[out]   StartValue  Pointer to where the performance counter's starting value is saved, or NULL.\r
  @param[out]   EndValue    Pointer to where the performance counter's ending value is saved, or NULL.\r
\r
  @return The frequency in Hz.\r
\r
**/\r
UINT64\r
EFIAPI\r
GetPerformanceCounterProperties (\r
  OUT      UINT64                    *StartValue,  OPTIONAL\r
  OUT      UINT64                    *EndValue     OPTIONAL\r
  )\r
{\r
  if (StartValue != NULL) {\r
    *StartValue = 0;\r
  }\r
  if (EndValue != NULL) {\r
    *EndValue = 0xFFFFFFFFFFFFFFFFull;\r
  }\r
\r
  return InternalGetTscFrequency ();\r
}\r
\r
/**\r
  Converts elapsed ticks of performance counter to time in nanoseconds.\r
\r
  This function converts the elapsed ticks of running performance counter to\r
  time value in unit of nanoseconds.\r
\r
  @param  Ticks     The number of elapsed ticks of running performance counter.\r
\r
  @return The elapsed time in nanoseconds.\r
\r
**/\r
UINT64\r
EFIAPI\r
GetTimeInNanoSecond (\r
  IN      UINT64                     Ticks\r
  )\r
{\r
  UINT64  Frequency;\r
  UINT64  NanoSeconds;\r
  UINT64  Remainder;\r
  INTN    Shift;\r
\r
  Frequency = GetPerformanceCounterProperties (NULL, NULL);\r
\r
  //\r
  //          Ticks\r
  // Time = --------- x 1,000,000,000\r
  //        Frequency\r
  //\r
  NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);\r
\r
  //\r
  // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.\r
  // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
  // i.e. highest bit set in Remainder should <= 33.\r
  //\r
  Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
  Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
  Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
  NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
\r
  return NanoSeconds;\r
}\r
Commit	Line	Data
	1	/** @file\r
	2	The Timer Library implementation which uses the Time Stamp Counter in the processor.\r
	3	\r
	4	For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);\r
	5	for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);\r
	6	for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);\r
	7	for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);\r
	8	for Intel Atom processors (family [06H], display_model [1CH]):\r
	9	the time-stamp counter increments at a constant rate.\r
	10	That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by\r
	11	the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may\r
	12	differ from the maximum qualified frequency of the processor.\r
	13	\r
	14	The specific processor configuration determines the behavior. Constant TSC behavior ensures that the\r
	15	duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if\r
	16	the processor core changes frequency. This is the architectural behavior moving forward.\r
	17	\r
	18	A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].\r
	19	\r
	20	Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>\r
	21	This program and the accompanying materials\r
	22	are licensed and made available under the terms and conditions of the BSD License\r
	23	which accompanies this distribution. The full text of the license may be found at\r
	24	http://opensource.org/licenses/bsd-license.php\r
	25	\r
	26	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	27	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	28	\r
	29	**/\r
	30	\r
	31	#include "TscTimerLibInternal.h"\r
	32	\r
	33	/** Calculate TSC frequency.\r
	34	\r
	35	The TSC counting frequency is determined by comparing how far it counts\r
	36	during a 1ms period as determined by the ACPI timer. The ACPI timer is\r
	37	used because it counts at a known frequency.\r
	38	If ACPI I/O space not enabled, this function will enable it. Then the\r
	39	TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.\r
	40	The TSC is then sampled again. The difference multiplied by 1000 is the TSC\r
	41	frequency. There will be a small error because of the overhead of reading\r
	42	the ACPI timer. An attempt is made to determine and compensate for this error.\r
	43	\r
	44	@return The number of TSC counts per second.\r
	45	\r
	46	**/\r
	47	UINT64\r
	48	InternalCalculateTscFrequency (\r
	49	VOID\r
	50	)\r
	51	{\r
	52	UINT64 StartTSC;\r
	53	UINT64 EndTSC;\r
	54	UINT32 TimerAddr;\r
	55	UINT32 Ticks;\r
	56	UINT64 TscFrequency;\r
	57	\r
	58	//\r
	59	// If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.\r
	60	//\r
	61	if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {\r
	62	PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));\r
	63	PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);\r
	64	}\r
	65	\r
	66	//\r
	67	// ACPI I/O space should be enabled now, locate the ACPI Timer.\r
	68	// ACPI I/O base address maybe have be initialized by other driver with different value,\r
	69	// So get it from PCI space directly.\r
	70	//\r
	71	TimerAddr = ((PciRead16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE))) & B_ICH_LPC_ACPI_BASE_BAR) + R_ACPI_PM1_TMR;\r
	72	Ticks = IoRead32 (TimerAddr) + (3579); // Set Ticks to 1ms in the future\r
	73	StartTSC = AsmReadTsc(); // Get base value for the TSC\r
	74	//\r
	75	// Wait until the ACPI timer has counted 1ms.\r
	76	// Timer wrap-arounds are handled correctly by this function.\r
	77	// When the current ACPI timer value is greater than 'Ticks', the while loop will exit.\r
	78	//\r
	79	while (((Ticks - IoRead32 (TimerAddr)) & BIT23) == 0) {\r
	80	CpuPause();\r
	81	}\r
	82	EndTSC = AsmReadTsc(); // TSC value 1ms later\r
	83	\r
	84	TscFrequency = MultU64x32 (\r
	85	(EndTSC - StartTSC), // Number of TSC counts in 1ms\r
	86	1000 // Number of ms in a second\r
	87	);\r
	88	\r
	89	return TscFrequency;\r
	90	}\r
	91	\r
	92	/** Stalls the CPU for at least the given number of ticks.\r
	93	\r
	94	Stalls the CPU for at least the given number of ticks. It's invoked by\r
	95	MicroSecondDelay() and NanoSecondDelay().\r
	96	\r
	97	@param[in] Delay A period of time to delay in ticks.\r
	98	\r
	99	**/\r
	100	VOID\r
	101	InternalX86Delay (\r
	102	IN UINT64 Delay\r
	103	)\r
	104	{\r
	105	UINT64 Ticks;\r
	106	\r
	107	//\r
	108	// The target timer count is calculated here\r
	109	//\r
	110	Ticks = AsmReadTsc() + Delay;\r
	111	\r
	112	//\r
	113	// Wait until time out\r
	114	// Timer wrap-arounds are NOT handled correctly by this function.\r
	115	// Thus, this function must be called within 10 years of reset since\r
	116	// Intel guarantees a minimum of 10 years before the TSC wraps.\r
	117	//\r
	118	while (AsmReadTsc() <= Ticks) CpuPause();\r
	119	}\r
	120	\r
	121	/** Stalls the CPU for at least the specified number of MicroSeconds.\r
	122	\r
	123	@param[in] MicroSeconds The minimum number of microseconds to delay.\r
	124	\r
	125	@return The value of MicroSeconds input.\r
	126	\r
	127	**/\r
	128	UINTN\r
	129	EFIAPI\r
	130	MicroSecondDelay (\r
	131	IN UINTN MicroSeconds\r
	132	)\r
	133	{\r
	134	InternalX86Delay (\r
	135	DivU64x32 (\r
	136	MultU64x64 (\r
	137	InternalGetTscFrequency (),\r
	138	MicroSeconds\r
	139	),\r
	140	1000000u\r
	141	)\r
	142	);\r
	143	return MicroSeconds;\r
	144	}\r
	145	\r
	146	/** Stalls the CPU for at least the specified number of NanoSeconds.\r
	147	\r
	148	@param[in] NanoSeconds The minimum number of nanoseconds to delay.\r
	149	\r
	150	@return The value of NanoSeconds input.\r
	151	\r
	152	**/\r
	153	UINTN\r
	154	EFIAPI\r
	155	NanoSecondDelay (\r
	156	IN UINTN NanoSeconds\r
	157	)\r
	158	{\r
	159	InternalX86Delay (\r
	160	DivU64x32 (\r
	161	MultU64x32 (\r
	162	InternalGetTscFrequency (),\r
	163	(UINT32)NanoSeconds\r
	164	),\r
	165	1000000000u\r
	166	)\r
	167	);\r
	168	return NanoSeconds;\r
	169	}\r
	170	\r
	171	/** Retrieves the current value of the 64-bit free running Time-Stamp counter.\r
	172	\r
	173	The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,\r
	174	Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and\r
	175	later processors) is a 64-bit counter that is set to 0 following a RESET of\r
	176	the processor. Following a RESET, the counter increments even when the\r
	177	processor is halted by the HLT instruction or the external STPCLK# pin. Note\r
	178	that the assertion of the external DPSLP# pin may cause the time-stamp\r
	179	counter to stop.\r
	180	\r
	181	The properties of the counter can be retrieved by the\r
	182	GetPerformanceCounterProperties() function.\r
	183	\r
	184	@return The current value of the free running performance counter.\r
	185	\r
	186	**/\r
	187	UINT64\r
	188	EFIAPI\r
	189	GetPerformanceCounter (\r
	190	VOID\r
	191	)\r
	192	{\r
	193	return AsmReadTsc();\r
	194	}\r
	195	\r
	196	/** Retrieves the 64-bit frequency in Hz and the range of performance counter\r
	197	values.\r
	198	\r
	199	If StartValue is not NULL, then the value that the performance counter starts\r
	200	with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value\r
	201	that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in\r
	202	EndValue.\r
	203	\r
	204	The 64-bit frequency of the performance counter, in Hz, is always returned.\r
	205	To determine average processor clock frequency, Intel recommends the use of\r
	206	EMON logic to count processor core clocks over the period of time for which\r
	207	the average is required.\r
	208	\r
	209	\r
	210	@param[out] StartValue Pointer to where the performance counter's starting value is saved, or NULL.\r
	211	@param[out] EndValue Pointer to where the performance counter's ending value is saved, or NULL.\r
	212	\r
	213	@return The frequency in Hz.\r
	214	\r
	215	**/\r
	216	UINT64\r
	217	EFIAPI\r
	218	GetPerformanceCounterProperties (\r
	219	OUT UINT64 *StartValue, OPTIONAL\r
	220	OUT UINT64 *EndValue OPTIONAL\r
	221	)\r
	222	{\r
	223	if (StartValue != NULL) {\r
	224	*StartValue = 0;\r
	225	}\r
	226	if (EndValue != NULL) {\r
	227	*EndValue = 0xFFFFFFFFFFFFFFFFull;\r
	228	}\r
	229	\r
	230	return InternalGetTscFrequency ();\r
	231	}\r
	232	\r
	233	/**\r
	234	Converts elapsed ticks of performance counter to time in nanoseconds.\r
	235	\r
	236	This function converts the elapsed ticks of running performance counter to\r
	237	time value in unit of nanoseconds.\r
	238	\r
	239	@param Ticks The number of elapsed ticks of running performance counter.\r
	240	\r
	241	@return The elapsed time in nanoseconds.\r
	242	\r
	243	**/\r
	244	UINT64\r
	245	EFIAPI\r
	246	GetTimeInNanoSecond (\r
	247	IN UINT64 Ticks\r
	248	)\r
	249	{\r
	250	UINT64 Frequency;\r
	251	UINT64 NanoSeconds;\r
	252	UINT64 Remainder;\r
	253	INTN Shift;\r
	254	\r
	255	Frequency = GetPerformanceCounterProperties (NULL, NULL);\r
	256	\r
	257	//\r
	258	// Ticks\r
	259	// Time = --------- x 1,000,000,000\r
	260	// Frequency\r
	261	//\r
	262	NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);\r
	263	\r
	264	//\r
	265	// Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.\r
	266	// Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
	267	// i.e. highest bit set in Remainder should <= 33.\r
	268	//\r
	269	Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
	270	Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
	271	Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
	272	NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
	273	\r
	274	return NanoSeconds;\r
	275	}\r