QuarkSocPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / platform.c

/** @file\r
The interface layer for memory controller access.\r
It is supporting both real hardware platform and simulation environment.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#include "mrc.h"\r
#include "memory_options.h"\r
#include "meminit_utils.h"\r
#include "io.h"\r
\r
#ifdef SIM\r
\r
void SimMmio32Write (\r
    uint32_t be,\r
    uint32_t address,\r
    uint32_t data );\r
\r
void SimMmio32Read (\r
    uint32_t be,\r
    uint32_t address,\r
    uint32_t *data );\r
\r
void SimDelayClk (\r
    uint32_t x2clk );\r
\r
// This is a simple delay function.\r
// It takes "nanoseconds" as a parameter.\r
void delay_n(uint32_t nanoseconds)\r
{\r
  SimDelayClk( 800*nanoseconds/1000);\r
}\r
#endif\r
\r
/****\r
 *\r
 ***/\r
uint32_t Rd32(\r
    uint32_t unit,\r
    uint32_t addr)\r
{\r
  uint32_t data;\r
\r
  switch (unit)\r
  {\r
  case MEM:\r
    case MMIO:\r
#ifdef SIM\r
    SimMmio32Read( 1, addr, &data);\r
#else\r
    data = *PTR32(addr);\r
#endif\r
    break;\r
\r
  case MCU:\r
    case HOST_BRIDGE:\r
    case MEMORY_MANAGER:\r
    case HTE:\r
    // Handle case addr bigger than 8bit\r
    pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);\r
    addr &= 0x00FF;\r
\r
    pciwrite32(0, 0, 0, SB_PACKET_REG,\r
        SB_COMMAND(SB_REG_READ_OPCODE, unit, addr));\r
    data = pciread32(0, 0, 0, SB_DATA_REG);\r
    break;\r
\r
  case DDRPHY:\r
    // Handle case addr bigger than 8bit\r
    pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);\r
    addr &= 0x00FF;\r
\r
    pciwrite32(0, 0, 0, SB_PACKET_REG,\r
        SB_COMMAND(SB_DDRIO_REG_READ_OPCODE, unit, addr));\r
    data = pciread32(0, 0, 0, SB_DATA_REG);\r
    break;\r
\r
  default:\r
    DEAD_LOOP()\r
    ;\r
  }\r
\r
  if (unit < MEM)\r
    DPF(D_REGRD, "RD32 %03X %08X %08X\n", unit, addr, data);\r
\r
  return data;\r
}\r
\r
/****\r
 *\r
 ***/\r
void Wr32(\r
    uint32_t unit,\r
    uint32_t addr,\r
    uint32_t data)\r
{\r
  if (unit < MEM)\r
    DPF(D_REGWR, "WR32 %03X %08X %08X\n", unit, addr, data);\r
\r
  switch (unit)\r
  {\r
  case MEM:\r
    case MMIO:\r
#ifdef SIM\r
    SimMmio32Write( 1, addr, data);\r
#else\r
    *PTR32(addr) = data;\r
#endif\r
    break;\r
\r
  case MCU:\r
    case HOST_BRIDGE:\r
    case MEMORY_MANAGER:\r
    case HTE:\r
    // Handle case addr bigger than 8bit\r
    pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);\r
    addr &= 0x00FF;\r
\r
    pciwrite32(0, 0, 0, SB_DATA_REG, data);\r
    pciwrite32(0, 0, 0, SB_PACKET_REG,\r
        SB_COMMAND(SB_REG_WRITE_OPCODE, unit, addr));\r
    break;\r
\r
  case DDRPHY:\r
    // Handle case addr bigger than 8bit\r
    pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);\r
    addr &= 0x00FF;\r
\r
    pciwrite32(0, 0, 0, SB_DATA_REG, data);\r
    pciwrite32(0, 0, 0, SB_PACKET_REG,\r
        SB_COMMAND(SB_DDRIO_REG_WRITE_OPCODE, unit, addr));\r
    break;\r
\r
  case DCMD:\r
    pciwrite32(0, 0, 0, SB_HADR_REG, 0);\r
    pciwrite32(0, 0, 0, SB_DATA_REG, data);\r
    pciwrite32(0, 0, 0, SB_PACKET_REG,\r
        SB_COMMAND(SB_DRAM_CMND_OPCODE, MCU, 0));\r
    break;\r
\r
  default:\r
    DEAD_LOOP()\r
    ;\r
  }\r
}\r
\r
/****\r
 *\r
 ***/\r
void WrMask32(\r
    uint32_t unit,\r
    uint32_t addr,\r
    uint32_t data,\r
    uint32_t mask)\r
{\r
  Wr32(unit, addr, ((Rd32(unit, addr) & ~mask) | (data & mask)));\r
}\r
\r
/****\r
 *\r
 ***/\r
void pciwrite32(\r
    uint32_t bus,\r
    uint32_t dev,\r
    uint32_t fn,\r
    uint32_t reg,\r
    uint32_t data)\r
{\r
  Wr32(MMIO, PCIADDR(bus,dev,fn,reg), data);\r
}\r
\r
/****\r
 *\r
 ***/\r
uint32_t pciread32(\r
    uint32_t bus,\r
    uint32_t dev,\r
    uint32_t fn,\r
    uint32_t reg)\r
{\r
  return Rd32(MMIO, PCIADDR(bus,dev,fn,reg));\r
}\r
\r