| | 1 | /*++\r |
| | 2 | \r |
| | 3 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r |
| | 4 | \r |
| | 5 | This program and the accompanying materials are licensed and made available under\r |
| | 6 | the terms and conditions of the BSD License that accompanies this distribution.\r |
| | 7 | The full text of the license may be found at\r |
| | 8 | http://opensource.org/licenses/bsd-license.php.\r |
| | 9 | \r |
| | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| | 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| | 12 | \r |
| | 13 | \r |
| | 14 | \r |
| | 15 | Module Name:\r |
| | 16 | \r |
| | 17 | PlatformMemoryRange.h\r |
| | 18 | \r |
| | 19 | Abstract:\r |
| | 20 | \r |
| | 21 | Platform Memory Range PPI as defined in EFI 2.0\r |
| | 22 | \r |
| | 23 | PPI for reserving special purpose memory ranges.\r |
| | 24 | \r |
| | 25 | --*/\r |
| | 26 | //\r |
| | 27 | //\r |
| | 28 | #ifndef _PEI_PLATFORM_MEMORY_RANGE_H_\r |
| | 29 | #define _PEI_PLATFORM_MEMORY_RANGE_H_\r |
| | 30 | \r |
| | 31 | #define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \\r |
| | 32 | { \\r |
| | 33 | 0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \\r |
| | 34 | }\r |
| | 35 | \r |
| | 36 | typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI ;\r |
| | 37 | \r |
| | 38 | #define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r |
| | 39 | \r |
| | 40 | #define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF\r |
| | 41 | #define PEI_MR_OPTION_ROM_NONE 0x00000000\r |
| | 42 | #define PEI_MR_OPTION_ROM_C0000_16K 0x00000001\r |
| | 43 | #define PEI_MR_OPTION_ROM_C4000_16K 0x00000002\r |
| | 44 | #define PEI_MR_OPTION_ROM_C8000_16K 0x00000004\r |
| | 45 | #define PEI_MR_OPTION_ROM_CC000_16K 0x00000008\r |
| | 46 | #define PEI_MR_OPTION_ROM_D0000_16K 0x00000010\r |
| | 47 | #define PEI_MR_OPTION_ROM_D4000_16K 0x00000020\r |
| | 48 | #define PEI_MR_OPTION_ROM_D8000_16K 0x00000040\r |
| | 49 | #define PEI_MR_OPTION_ROM_DC000_16K 0x00000080\r |
| | 50 | #define PEI_MR_OPTION_ROM_E0000_16K 0x00000100\r |
| | 51 | #define PEI_MR_OPTION_ROM_E4000_16K 0x00000200\r |
| | 52 | #define PEI_MR_OPTION_ROM_E8000_16K 0x00000400\r |
| | 53 | #define PEI_MR_OPTION_ROM_EC000_16K 0x00000800\r |
| | 54 | #define PEI_MR_OPTION_ROM_F0000_16K 0x00001000\r |
| | 55 | #define PEI_MR_OPTION_ROM_F4000_16K 0x00002000\r |
| | 56 | #define PEI_MR_OPTION_ROM_F8000_16K 0x00004000\r |
| | 57 | #define PEI_MR_OPTION_ROM_FC000_16K 0x00008000\r |
| | 58 | \r |
| | 59 | //\r |
| | 60 | // SMRAM Memory Range\r |
| | 61 | //\r |
| | 62 | #define PEI_MEMORY_RANGE_SMRAM UINT32\r |
| | 63 | #define PEI_MR_SMRAM_ALL 0xFFFFFFFF\r |
| | 64 | #define PEI_MR_SMRAM_NONE 0x00000000\r |
| | 65 | #define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r |
| | 66 | #define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000\r |
| | 67 | #define PEI_MR_SMRAM_ABSEG_MASK 0x00010000\r |
| | 68 | #define PEI_MR_SMRAM_HSEG_MASK 0x00020000\r |
| | 69 | #define PEI_MR_SMRAM_TSEG_MASK 0x00040000\r |
| | 70 | //\r |
| | 71 | // If adding additional entries, SMRAM Size\r |
| | 72 | // is a multiple of 128KB.\r |
| | 73 | //\r |
| | 74 | #define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF\r |
| | 75 | #define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001\r |
| | 76 | #define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002\r |
| | 77 | #define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004\r |
| | 78 | #define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008\r |
| | 79 | #define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010\r |
| | 80 | #define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020\r |
| | 81 | #define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040\r |
| | 82 | \r |
| | 83 | #define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001\r |
| | 84 | #define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001\r |
| | 85 | #define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001\r |
| | 86 | #define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001\r |
| | 87 | #define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001\r |
| | 88 | #define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002\r |
| | 89 | #define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002\r |
| | 90 | #define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004\r |
| | 91 | #define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004\r |
| | 92 | #define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008\r |
| | 93 | #define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008\r |
| | 94 | \r |
| | 95 | //\r |
| | 96 | // Graphics Memory Range\r |
| | 97 | //\r |
| | 98 | #define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32\r |
| | 99 | #define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF\r |
| | 100 | #define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000\r |
| | 101 | #define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000\r |
| | 102 | //\r |
| | 103 | // If adding additional entries, Graphics Memory Size\r |
| | 104 | // is a multiple of 512KB.\r |
| | 105 | //\r |
| | 106 | #define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF\r |
| | 107 | #define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001\r |
| | 108 | #define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001\r |
| | 109 | #define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002\r |
| | 110 | #define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002\r |
| | 111 | #define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008\r |
| | 112 | #define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008\r |
| | 113 | #define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010\r |
| | 114 | #define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010\r |
| | 115 | #define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020\r |
| | 116 | #define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020\r |
| | 117 | #define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040\r |
| | 118 | #define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040\r |
| | 119 | #define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060\r |
| | 120 | #define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060\r |
| | 121 | #define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080\r |
| | 122 | #define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080\r |
| | 123 | #define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100\r |
| | 124 | #define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100\r |
| | 125 | #define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200\r |
| | 126 | #define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200\r |
| | 127 | //\r |
| | 128 | // Pci Memory Hole\r |
| | 129 | //\r |
| | 130 | #define PEI_MEMORY_RANGE_PCI_MEMORY UINT32\r |
| | 131 | #define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001\r |
| | 132 | \r |
| | 133 | typedef\r |
| | 134 | EFI_STATUS\r |
| | 135 | (EFIAPI *PEI_CHOOSE_RANGES) (\r |
| | 136 | IN EFI_PEI_SERVICES **PeiServices,\r |
| | 137 | IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,\r |
| | 138 | IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,\r |
| | 139 | IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,\r |
| | 140 | IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,\r |
| | 141 | IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask\r |
| | 142 | );\r |
| | 143 | \r |
| | 144 | struct _PEI_PLATFORM_MEMORY_RANGE_PPI {\r |
| | 145 | PEI_CHOOSE_RANGES ChooseRanges;\r |
| | 146 | };\r |
| | 147 | \r |
| | 148 | extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;\r |
| | 149 | \r |
| | 150 | #endif\r |
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