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1 //
2 // Copyright (c) 2011, ARM Limited. All rights reserved.
3 //
4 // This program and the accompanying materials
5 // are licensed and made available under the terms and conditions of the BSD License
6 // which accompanies this distribution. The full text of the license may be found at
7 // http://opensource.org/licenses/bsd-license.php
8 //
9 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11 //
12 //
13
14 #include <Library/ArmCpuLib.h>
15
16 .text
17 .align 3
18
19 GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
20 GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
21
22 // VOID
23 // ArmCpuSynchronizeWait (
24 // IN ARM_CPU_SYNCHRONIZE_EVENT Event
25 // );
26 ASM_PFX(ArmCpuSynchronizeWait):
27 cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
28 // The SCU enabled is the event to tell us the Init Boot Memory is initialized
29 bx lr
30 b ASM_PFX(CArmCpuSynchronizeWait)
31
32
33 #if 0
34 GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
35 GCC_ASM_EXPORT(ArmGetScuBaseAddress)
36 GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
37
38 // VOID
39 // ArmCpuSynchronizeWait (
40 // IN ARM_CPU_SYNCHRONIZE_EVENT Event
41 // );
42 ASM_PFX(ArmCpuSynchronizeWait):
43 cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
44 // The SCU enabled is the event to tell us the Init Boot Memory is initialized
45 beq ArmWaitScuEnabled
46 b ASM_PFX(CArmCpuSynchronizeWait)
47
48 // IN None
49 // OUT r0 = SCU Base Address
50 ASM_PFX(ArmGetScuBaseAddress):
51 // Read Configuration Base Address Register. ArmCBar cannot be called to get
52 // the Configuration BAR as a stack is not necessary setup. The SCU is at the
53 // offset 0x0000 from the Private Memory Region.
54 mrc p15, 4, r0, c15, c0, 0
55 bx lr
56
57 ASM_PFX(ArmWaitScuEnabled):
58 // Read Configuration Base Address Register. ArmCBar cannot be called to get
59 // the Configuration BAR as a stack is not necessary setup. The SCU is at the
60 // offset 0x0000 from the Private Memory Region.
61 mrc p15, 4, r0, c15, c0, 0
62 add r0, r0, #A9_SCU_CONTROL_OFFSET
63 ldr r0, [r0]
64 cmp r0, #1
65 bne ArmWaitScuEnabled
66 bx lr
67 #endif