2 // Copyright (c) 2011, ARM Limited. All rights reserved.
4 // This program and the accompanying materials
5 // are licensed and made available under the terms and conditions of the BSD License
6 // which accompanies this distribution. The full text of the license may be found at
7 // http://opensource.org/licenses/bsd-license.php
9 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #include <Library/ArmCpuLib.h>
15 #include <Chipset/ArmCortexA9.h>
17 EXPORT ArmCpuSynchronizeWait
18 EXPORT ArmGetScuBaseAddress
19 IMPORT CArmCpuSynchronizeWait
22 AREA ArmCortexA9Helper, CODE, READONLY
25 // ArmCpuSynchronizeWait (
26 // IN ARM_CPU_SYNCHRONIZE_EVENT Event
29 cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
30 // The SCU enabled is the event to tell us the Init Boot Memory is initialized
32 b CArmCpuSynchronizeWait
35 // OUT r0 = SCU Base Address
37 // Read Configuration Base Address Register. ArmCBar cannot be called to get
38 // the Configuration BAR as a stack is not necessary setup. The SCU is at the
39 // offset 0x0000 from the Private Memory Region.
40 mrc p15, 4, r0, c15, c0, 0
44 // Read Configuration Base Address Register. ArmCBar cannot be called to get
45 // the Configuration BAR as a stack is not necessary setup. The SCU is at the
46 // offset 0x0000 from the Private Memory Region.
47 mrc p15, 4, r0, c15, c0, 0
48 add r0, r0, #A9_SCU_CONTROL_OFFSET