ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include "ArmGicDxe.h"
  16 #include "GicV3/ArmGicV3Lib.h"
  17
  18 #define ARM_GIC_DEFAULT_PRIORITY  0x80
  19
  20 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
  21
  22 STATIC UINTN mGicDistributorBase;
  23 STATIC UINTN mGicRedistributorsBase;
  24
  25 /**
  26   Enable interrupt source Source.
  27
  28   @param This     Instance pointer for this protocol
  29   @param Source   Hardware source of the interrupt
  30
  31   @retval EFI_SUCCESS       Source interrupt enabled.
  32   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
  33
  34 **/
  35 EFI_STATUS
  36 EFIAPI
  37 GicV3EnableInterruptSource (
  38   IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
  39   IN HARDWARE_INTERRUPT_SOURCE          Source
  40   )
  41 {
  42   if (Source > mGicNumInterrupts) {
  43     ASSERT(FALSE);
  44     return EFI_UNSUPPORTED;
  45   }
  46
  47   ArmGicEnableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);
  48
  49   return EFI_SUCCESS;
  50 }
  51
  52 /**
  53   Disable interrupt source Source.
  54
  55   @param This     Instance pointer for this protocol
  56   @param Source   Hardware source of the interrupt
  57
  58   @retval EFI_SUCCESS       Source interrupt disabled.
  59   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
  60
  61 **/
  62 EFI_STATUS
  63 EFIAPI
  64 GicV3DisableInterruptSource (
  65   IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
  66   IN HARDWARE_INTERRUPT_SOURCE          Source
  67   )
  68 {
  69   if (Source > mGicNumInterrupts) {
  70     ASSERT(FALSE);
  71     return EFI_UNSUPPORTED;
  72   }
  73
  74   ArmGicDisableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);
  75
  76   return EFI_SUCCESS;
  77 }
  78
  79 /**
  80   Return current state of interrupt source Source.
  81
  82   @param This     Instance pointer for this protocol
  83   @param Source   Hardware source of the interrupt
  84   @param InterruptState  TRUE: source enabled, FALSE: source disabled.
  85
  86   @retval EFI_SUCCESS       InterruptState is valid
  87   @retval EFI_DEVICE_ERROR  InterruptState is not valid
  88
  89 **/
  90 EFI_STATUS
  91 EFIAPI
  92 GicV3GetInterruptSourceState (
  93   IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
  94   IN HARDWARE_INTERRUPT_SOURCE          Source,
  95   IN BOOLEAN                            *InterruptState
  96   )
  97 {
  98   if (Source > mGicNumInterrupts) {
  99     ASSERT(FALSE);
 100     return EFI_UNSUPPORTED;
 101   }
 102
 103   *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, mGicRedistributorsBase, Source);
 104
 105   return EFI_SUCCESS;
 106 }
 107
 108 /**
 109   Signal to the hardware that the End Of Interrupt state
 110   has been reached.
 111
 112   @param This     Instance pointer for this protocol
 113   @param Source   Hardware source of the interrupt
 114
 115   @retval EFI_SUCCESS       Source interrupt EOI'ed.
 116   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
 117
 118 **/
 119 EFI_STATUS
 120 EFIAPI
 121 GicV3EndOfInterrupt (
 122   IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
 123   IN HARDWARE_INTERRUPT_SOURCE          Source
 124   )
 125 {
 126   if (Source > mGicNumInterrupts) {
 127     ASSERT(FALSE);
 128     return EFI_UNSUPPORTED;
 129   }
 130
 131   ArmGicV3EndOfInterrupt (Source);
 132   return EFI_SUCCESS;
 133 }
 134
 135 /**
 136   EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
 137
 138   @param  InterruptType    Defines the type of interrupt or exception that
 139                            occurred on the processor.This parameter is processor architecture specific.
 140   @param  SystemContext    A pointer to the processor context when
 141                            the interrupt occurred on the processor.
 142
 143   @return None
 144
 145 **/
 146 VOID
 147 EFIAPI
 148 GicV3IrqInterruptHandler (
 149   IN EFI_EXCEPTION_TYPE           InterruptType,
 150   IN EFI_SYSTEM_CONTEXT           SystemContext
 151   )
 152 {
 153   UINT32                      GicInterrupt;
 154   HARDWARE_INTERRUPT_HANDLER  InterruptHandler;
 155
 156   GicInterrupt = ArmGicV3AcknowledgeInterrupt ();
 157
 158   // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
 159   // number of interrupt (ie: Spurious interrupt).
 160   if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
 161     // The special interrupt do not need to be acknowledge
 162     return;
 163   }
 164
 165   InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
 166   if (InterruptHandler != NULL) {
 167     // Call the registered interrupt handler.
 168     InterruptHandler (GicInterrupt, SystemContext);
 169   } else {
 170     DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
 171   }
 172
 173   GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);
 174 }
 175
 176 //
 177 // The protocol instance produced by this driver
 178 //
 179 EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
 180   RegisterInterruptSource,
 181   GicV3EnableInterruptSource,
 182   GicV3DisableInterruptSource,
 183   GicV3GetInterruptSourceState,
 184   GicV3EndOfInterrupt
 185 };
 186
 187 /**
 188   Shutdown our hardware
 189
 190   DXE Core will disable interrupts and turn off the timer and disable interrupts
 191   after all the event handlers have run.
 192
 193   @param[in]  Event   The Event that is being processed
 194   @param[in]  Context Event Context
 195 **/
 196 VOID
 197 EFIAPI
 198 GicV3ExitBootServicesEvent (
 199   IN EFI_EVENT  Event,
 200   IN VOID       *Context
 201   )
 202 {
 203   UINTN    Index;
 204
 205   // Acknowledge all pending interrupts
 206   for (Index = 0; Index < mGicNumInterrupts; Index++) {
 207     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
 208   }
 209
 210   for (Index = 0; Index < mGicNumInterrupts; Index++) {
 211     GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index);
 212   }
 213
 214   // Disable Gic Interface
 215   ArmGicV3DisableInterruptInterface ();
 216
 217   // Disable Gic Distributor
 218   ArmGicDisableDistributor (mGicDistributorBase);
 219 }
 220
 221 /**
 222   Initialize the state information for the CPU Architectural Protocol
 223
 224   @param  ImageHandle   of the loaded driver
 225   @param  SystemTable   Pointer to the System Table
 226
 227   @retval EFI_SUCCESS           Protocol registered
 228   @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
 229   @retval EFI_DEVICE_ERROR      Hardware problems
 230
 231 **/
 232 EFI_STATUS
 233 GicV3DxeInitialize (
 234   IN EFI_HANDLE         ImageHandle,
 235   IN EFI_SYSTEM_TABLE   *SystemTable
 236   )
 237 {
 238   EFI_STATUS              Status;
 239   UINTN                   Index;
 240   UINT32                  RegOffset;
 241   UINTN                   RegShift;
 242   UINT64                  CpuTarget;
 243   UINT64                  MpId;
 244
 245   // Make sure the Interrupt Controller Protocol is not already installed in the system.
 246   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
 247
 248   mGicDistributorBase    = PcdGet32 (PcdGicDistributorBase);
 249   mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase);
 250   mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
 251
 252   //
 253   // We will be driving this GIC in native v3 mode, i.e., with Affinity
 254   // Routing enabled. So ensure that the ARE bit is set.
 255   //
 256   if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
 257     MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
 258   }
 259
 260   for (Index = 0; Index < mGicNumInterrupts; Index++) {
 261     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
 262
 263     // Set Priority
 264     RegOffset = Index / 4;
 265     RegShift = (Index % 4) * 8;
 266     MmioAndThenOr32 (
 267       mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
 268       ~(0xff << RegShift),
 269       ARM_GIC_DEFAULT_PRIORITY << RegShift
 270       );
 271   }
 272
 273   //
 274   // Targets the interrupts to the Primary Cpu
 275   //
 276
 277   MpId = ArmReadMpidr ();
 278   CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
 279
 280   // Route the SPIs to the primary CPU. SPIs start at the INTID 32
 281   for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
 282     MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);
 283   }
 284
 285   // Set binary point reg to 0x7 (no preemption)
 286   ArmGicV3SetBinaryPointer (0x7);
 287
 288   // Set priority mask reg to 0xff to allow all priorities through
 289   ArmGicV3SetPriorityMask (0xff);
 290
 291   // Enable gic cpu interface
 292   ArmGicV3EnableInterruptInterface ();
 293
 294   // Enable gic distributor
 295   ArmGicEnableDistributor (mGicDistributorBase);
 296
 297   Status = InstallAndRegisterInterruptService (
 298           &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent);
 299
 300   return Status;
 301 }