ArmPkg/Include/Chipset/ArmV7.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_V7_H__
  17 #define __ARM_V7_H__
  18
  19 #include <Chipset/ArmV7Mmu.h>
  20
  21 // ARM Interrupt ID in Exception Table
  22 #define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_ARM_IRQ
  23
  24 // ID_PFR1 - ARM Processor Feature Register 1 definitions
  25 #define ARM_PFR1_SEC        (0xFUL << 4)
  26 #define ARM_PFR1_TIMER      (0xFUL << 16)
  27 #define ARM_PFR1_GIC        (0xFUL << 28)
  28
  29 // Domain Access Control Register
  30 #define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))
  31 #define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))
  32 #define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))
  33 #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
  34 #define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))
  35
  36 // CPSR - Coprocessor Status Register definitions
  37 #define CPSR_MODE_USER       0x10
  38 #define CPSR_MODE_FIQ        0x11
  39 #define CPSR_MODE_IRQ        0x12
  40 #define CPSR_MODE_SVC        0x13
  41 #define CPSR_MODE_ABORT      0x17
  42 #define CPSR_MODE_HYP        0x1A
  43 #define CPSR_MODE_UNDEFINED  0x1B
  44 #define CPSR_MODE_SYSTEM     0x1F
  45 #define CPSR_MODE_MASK       0x1F
  46 #define CPSR_ASYNC_ABORT     (1 << 8)
  47 #define CPSR_IRQ             (1 << 7)
  48 #define CPSR_FIQ             (1 << 6)
  49
  50
  51 // CPACR - Coprocessor Access Control Register definitions
  52 #define CPACR_CP_DENIED(cp)     0x00
  53 #define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
  54 #define CPACR_CP_FULL(cp)       ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
  55 #define CPACR_ASEDIS            (1 << 31)
  56 #define CPACR_D32DIS            (1 << 30)
  57 #define CPACR_CP_FULL_ACCESS    0x0FFFFFFF
  58
  59 // NSACR - Non-Secure Access Control Register definitions
  60 #define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)
  61 #define NSACR_NSD32DIS          (1 << 14)
  62 #define NSACR_NSASEDIS          (1 << 15)
  63 #define NSACR_PLE               (1 << 16)
  64 #define NSACR_TL                (1 << 17)
  65 #define NSACR_NS_SMP            (1 << 18)
  66 #define NSACR_RFR               (1 << 19)
  67
  68 // SCR - Secure Configuration Register definitions
  69 #define SCR_NS                  (1 << 0)
  70 #define SCR_IRQ                 (1 << 1)
  71 #define SCR_FIQ                 (1 << 2)
  72 #define SCR_EA                  (1 << 3)
  73 #define SCR_FW                  (1 << 4)
  74 #define SCR_AW                  (1 << 5)
  75
  76 // MIDR - Main ID Register definitions
  77 #define ARM_CPU_TYPE_SHIFT      4
  78 #define ARM_CPU_TYPE_MASK       0xFFF
  79 #define ARM_CPU_TYPE_AEMv8      0xD0F
  80 #define ARM_CPU_TYPE_A53        0xD03
  81 #define ARM_CPU_TYPE_A57        0xD07
  82 #define ARM_CPU_TYPE_A15        0xC0F
  83 #define ARM_CPU_TYPE_A12        0xC0D
  84 #define ARM_CPU_TYPE_A9         0xC09
  85 #define ARM_CPU_TYPE_A7         0xC07
  86 #define ARM_CPU_TYPE_A5         0xC05
  87
  88 #define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )
  89 #define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  90
  91 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
  92
  93 VOID
  94 EFIAPI
  95 ArmEnableSWPInstruction (
  96   VOID
  97   );
  98
  99 UINTN
 100 EFIAPI
 101 ArmReadCbar (
 102   VOID
 103   );
 104
 105 UINTN
 106 EFIAPI
 107 ArmReadTpidrurw (
 108   VOID
 109   );
 110
 111 VOID
 112 EFIAPI
 113 ArmWriteTpidrurw (
 114   UINTN Value
 115   );
 116
 117 UINT32
 118 EFIAPI
 119 ArmReadNsacr (
 120   VOID
 121   );
 122
 123 VOID
 124 EFIAPI
 125 ArmWriteNsacr (
 126   IN  UINT32   Nsacr
 127   );
 128
 129 #endif // __ARM_V7_H__