ArmPkg/Include/Library/ArmGicLib.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __ARMGIC_H
  16 #define __ARMGIC_H
  17
  18 #include <Library/ArmGicArchLib.h>
  19
  20 // GIC Distributor
  21 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register
  22 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register
  23 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register
  24
  25 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
  26 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers
  27 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers
  28 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers
  29 #define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers
  30 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers
  31 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers
  32
  33 // Each reg base below repeats for Number of interrupts / 4
  34 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers
  35
  36 // Each reg base below repeats for Number of interrupts
  37 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers
  38 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers
  39
  40 #define ARM_GIC_ICDPPISR        0xD00 // PPI Status register
  41
  42 // just one of these
  43 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
  44
  45 // GICv3 specific registers
  46 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers
  47
  48 // GICD_CTLR bits
  49 #define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)
  50 #define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)
  51
  52 // GIC Redistributor
  53
  54 #define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB
  55 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
  56
  57 // GIC Redistributor Control frame
  58 #define ARM_GICR_TYPER          0x0008  // Redistributor Type Register
  59
  60 // GIC SGI & PPI Redistributor frame
  61 #define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers
  62 #define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers
  63
  64 // GIC Cpu interface
  65 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register
  66 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register
  67 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register
  68 #define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register
  69 #define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register
  70 #define ARM_GIC_ICCRPR          0x14  // Running Priority Register
  71 #define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register
  72 #define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register
  73 #define ARM_GIC_ICCIIDR         0xFC  // Identification Register
  74
  75 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0
  76 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1
  77 #define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2
  78
  79 // Bit-masks to configure the CPU Interface Control register
  80 #define ARM_GIC_ICCICR_ENABLE_SECURE            0x01
  81 #define ARM_GIC_ICCICR_ENABLE_NS                0x02
  82 #define ARM_GIC_ICCICR_ACK_CTL                  0x04
  83 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08
  84 #define ARM_GIC_ICCICR_USE_SBPR                 0x10
  85
  86 // Bit Mask for GICC_IIDR
  87 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)
  88 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
  89 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)
  90 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)
  91
  92 // Bit Mask for
  93 #define ARM_GIC_ICCIAR_ACKINTID                 0x3FF
  94
  95 UINTN
  96 EFIAPI
  97 ArmGicGetInterfaceIdentification (
  98   IN  INTN          GicInterruptInterfaceBase
  99   );
 100
 101 // GIC Secure interfaces
 102 VOID
 103 EFIAPI
 104 ArmGicSetupNonSecure (
 105   IN  UINTN         MpId,
 106   IN  INTN          GicDistributorBase,
 107   IN  INTN          GicInterruptInterfaceBase
 108   );
 109
 110 VOID
 111 EFIAPI
 112 ArmGicSetSecureInterrupts (
 113   IN  UINTN         GicDistributorBase,
 114   IN  UINTN*        GicSecureInterruptMask,
 115   IN  UINTN         GicSecureInterruptMaskSize
 116   );
 117
 118 VOID
 119 EFIAPI
 120 ArmGicEnableInterruptInterface (
 121   IN  INTN          GicInterruptInterfaceBase
 122   );
 123
 124 VOID
 125 EFIAPI
 126 ArmGicDisableInterruptInterface (
 127   IN  INTN          GicInterruptInterfaceBase
 128   );
 129
 130 VOID
 131 EFIAPI
 132 ArmGicEnableDistributor (
 133   IN  INTN          GicDistributorBase
 134   );
 135
 136 VOID
 137 EFIAPI
 138 ArmGicDisableDistributor (
 139   IN  INTN          GicDistributorBase
 140   );
 141
 142 UINTN
 143 EFIAPI
 144 ArmGicGetMaxNumInterrupts (
 145   IN  INTN          GicDistributorBase
 146   );
 147
 148 VOID
 149 EFIAPI
 150 ArmGicSendSgiTo (
 151   IN  INTN          GicDistributorBase,
 152   IN  INTN          TargetListFilter,
 153   IN  INTN          CPUTargetList,
 154   IN  INTN          SgiId
 155   );
 156
 157 /*
 158  * Acknowledge and return the value of the Interrupt Acknowledge Register
 159  *
 160  * InterruptId is returned separately from the register value because in
 161  * the GICv2 the register value contains the CpuId and InterruptId while
 162  * in the GICv3 the register value is only the InterruptId.
 163  *
 164  * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface
 165  * @param InterruptId                 InterruptId read from the Interrupt
 166  *                                    Acknowledge Register
 167  *
 168  * @retval value returned by the Interrupt Acknowledge Register
 169  *
 170  */
 171 UINTN
 172 EFIAPI
 173 ArmGicAcknowledgeInterrupt (
 174   IN  UINTN          GicInterruptInterfaceBase,
 175   OUT UINTN          *InterruptId
 176   );
 177
 178 VOID
 179 EFIAPI
 180 ArmGicEndOfInterrupt (
 181   IN  UINTN                 GicInterruptInterfaceBase,
 182   IN UINTN                  Source
 183   );
 184
 185 UINTN
 186 EFIAPI
 187 ArmGicSetPriorityMask (
 188   IN  INTN          GicInterruptInterfaceBase,
 189   IN  INTN          PriorityMask
 190   );
 191
 192 VOID
 193 EFIAPI
 194 ArmGicEnableInterrupt (
 195   IN UINTN                  GicDistributorBase,
 196   IN UINTN                  GicRedistributorBase,
 197   IN UINTN                  Source
 198   );
 199
 200 VOID
 201 EFIAPI
 202 ArmGicDisableInterrupt (
 203   IN UINTN                  GicDistributorBase,
 204   IN UINTN                  GicRedistributorBase,
 205   IN UINTN                  Source
 206   );
 207
 208 BOOLEAN
 209 EFIAPI
 210 ArmGicIsInterruptEnabled (
 211   IN UINTN                  GicDistributorBase,
 212   IN UINTN                  GicRedistributorBase,
 213   IN UINTN                  Source
 214   );
 215
 216 // GIC revision 2 specific declarations
 217
 218 // Interrupts from 1020 to 1023 are considered as special interrupts
 219 // (eg: spurious interrupts)
 220 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
 221           (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
 222
 223 VOID
 224 EFIAPI
 225 ArmGicV2SetupNonSecure (
 226   IN  UINTN         MpId,
 227   IN  INTN          GicDistributorBase,
 228   IN  INTN          GicInterruptInterfaceBase
 229   );
 230
 231 VOID
 232 EFIAPI
 233 ArmGicV2EnableInterruptInterface (
 234   IN  INTN          GicInterruptInterfaceBase
 235   );
 236
 237 VOID
 238 EFIAPI
 239 ArmGicV2DisableInterruptInterface (
 240   IN  INTN          GicInterruptInterfaceBase
 241   );
 242
 243 UINTN
 244 EFIAPI
 245 ArmGicV2AcknowledgeInterrupt (
 246   IN  UINTN          GicInterruptInterfaceBase
 247   );
 248
 249 VOID
 250 EFIAPI
 251 ArmGicV2EndOfInterrupt (
 252   IN UINTN                  GicInterruptInterfaceBase,
 253   IN UINTN                  Source
 254   );
 255
 256 // GIC revision 3 specific declarations
 257
 258 #define ICC_SRE_EL2_SRE         (1 << 0)
 259
 260 #define ARM_GICD_IROUTER_IRM BIT31
 261
 262 UINT32
 263 EFIAPI
 264 ArmGicV3GetControlSystemRegisterEnable (
 265   VOID
 266   );
 267
 268 VOID
 269 EFIAPI
 270 ArmGicV3SetControlSystemRegisterEnable (
 271   IN UINT32         ControlSystemRegisterEnable
 272   );
 273
 274 VOID
 275 EFIAPI
 276 ArmGicV3EnableInterruptInterface (
 277   VOID
 278   );
 279
 280 VOID
 281 EFIAPI
 282 ArmGicV3DisableInterruptInterface (
 283   VOID
 284   );
 285
 286 UINTN
 287 EFIAPI
 288 ArmGicV3AcknowledgeInterrupt (
 289   VOID
 290   );
 291
 292 VOID
 293 EFIAPI
 294 ArmGicV3EndOfInterrupt (
 295   IN UINTN                  Source
 296   );
 297
 298 VOID
 299 ArmGicV3SetBinaryPointer (
 300   IN UINTN                  BinaryPoint
 301   );
 302
 303 VOID
 304 ArmGicV3SetPriorityMask (
 305   IN UINTN                  Priority
 306   );
 307
 308 #endif