ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef __ARM_LIB__
  11 #define __ARM_LIB__
  12
  13 #include <Uefi/UefiBaseType.h>
  14
  15 #ifdef MDE_CPU_ARM
  16   #include <Chipset/ArmV7.h>
  17 #elif defined(MDE_CPU_AARCH64)
  18   #include <Chipset/AArch64.h>
  19 #else
  20  #error "Unknown chipset."
  21 #endif
  22
  23 #define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \
  24                                      EFI_MEMORY_WT | EFI_MEMORY_WB | \
  25                                      EFI_MEMORY_UCE)
  26
  27 /**
  28  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  29  *
  30  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  31  * be used in Secure World to distinguished Secure to Non-Secure memory.
  32  */
  33 typedef enum {
  34   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  35   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  36   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  37   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  38
  39   // On some platforms, memory mapped flash region is designed as not supporting
  40   // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
  41   // need.
  42   // Do NOT use below two attributes if you are not sure.
  43   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
  44   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
  45
  46   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  47   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  48   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  49   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  50 } ARM_MEMORY_REGION_ATTRIBUTES;
  51
  52 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  53
  54 typedef struct {
  55   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  56   EFI_VIRTUAL_ADDRESS           VirtualBase;
  57   UINT64                        Length;
  58   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  59 } ARM_MEMORY_REGION_DESCRIPTOR;
  60
  61 typedef VOID (*CACHE_OPERATION)(VOID);
  62 typedef VOID (*LINE_OPERATION)(UINTN);
  63
  64 //
  65 // ARM Processor Mode
  66 //
  67 typedef enum {
  68   ARM_PROCESSOR_MODE_USER       = 0x10,
  69   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  70   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  71   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  72   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  73   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  74   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  75   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  76   ARM_PROCESSOR_MODE_MASK       = 0x1F
  77 } ARM_PROCESSOR_MODE;
  78
  79 //
  80 // ARM Cpu IDs
  81 //
  82 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  83 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
  84 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
  85 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
  86 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
  87 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
  88
  89 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
  90 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
  91 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
  92 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
  93 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
  94 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
  95
  96 //
  97 // ARM MP Core IDs
  98 //
  99 #define ARM_CORE_AFF0         0xFF
 100 #define ARM_CORE_AFF1         (0xFF << 8)
 101 #define ARM_CORE_AFF2         (0xFF << 16)
 102 #define ARM_CORE_AFF3         (0xFFULL << 32)
 103
 104 #define ARM_CORE_MASK         ARM_CORE_AFF0
 105 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 106 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 107 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 108 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 109 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 110
 111 UINTN
 112 EFIAPI
 113 ArmDataCacheLineLength (
 114   VOID
 115   );
 116
 117 UINTN
 118 EFIAPI
 119 ArmInstructionCacheLineLength (
 120   VOID
 121   );
 122
 123 UINTN
 124 EFIAPI
 125 ArmCacheWritebackGranule (
 126   VOID
 127   );
 128
 129 UINTN
 130 EFIAPI
 131 ArmIsArchTimerImplemented (
 132   VOID
 133   );
 134
 135 UINTN
 136 EFIAPI
 137 ArmReadIdPfr0 (
 138   VOID
 139   );
 140
 141 UINTN
 142 EFIAPI
 143 ArmReadIdPfr1 (
 144   VOID
 145   );
 146
 147 UINTN
 148 EFIAPI
 149 ArmCacheInfo (
 150   VOID
 151   );
 152
 153 BOOLEAN
 154 EFIAPI
 155 ArmIsMpCore (
 156   VOID
 157   );
 158
 159 VOID
 160 EFIAPI
 161 ArmInvalidateDataCache (
 162   VOID
 163   );
 164
 165
 166 VOID
 167 EFIAPI
 168 ArmCleanInvalidateDataCache (
 169   VOID
 170   );
 171
 172 VOID
 173 EFIAPI
 174 ArmCleanDataCache (
 175   VOID
 176   );
 177
 178 VOID
 179 EFIAPI
 180 ArmInvalidateInstructionCache (
 181   VOID
 182   );
 183
 184 VOID
 185 EFIAPI
 186 ArmInvalidateDataCacheEntryByMVA (
 187   IN  UINTN   Address
 188   );
 189
 190 VOID
 191 EFIAPI
 192 ArmCleanDataCacheEntryToPoUByMVA (
 193   IN  UINTN   Address
 194   );
 195
 196 VOID
 197 EFIAPI
 198 ArmInvalidateInstructionCacheEntryToPoUByMVA (
 199   IN  UINTN   Address
 200   );
 201
 202 VOID
 203 EFIAPI
 204 ArmCleanDataCacheEntryByMVA (
 205 IN  UINTN   Address
 206 );
 207
 208 VOID
 209 EFIAPI
 210 ArmCleanInvalidateDataCacheEntryByMVA (
 211   IN  UINTN   Address
 212   );
 213
 214 VOID
 215 EFIAPI
 216 ArmInvalidateDataCacheEntryBySetWay (
 217   IN  UINTN  SetWayFormat
 218   );
 219
 220 VOID
 221 EFIAPI
 222 ArmCleanDataCacheEntryBySetWay (
 223   IN  UINTN  SetWayFormat
 224   );
 225
 226 VOID
 227 EFIAPI
 228 ArmCleanInvalidateDataCacheEntryBySetWay (
 229   IN  UINTN   SetWayFormat
 230   );
 231
 232 VOID
 233 EFIAPI
 234 ArmEnableDataCache (
 235   VOID
 236   );
 237
 238 VOID
 239 EFIAPI
 240 ArmDisableDataCache (
 241   VOID
 242   );
 243
 244 VOID
 245 EFIAPI
 246 ArmEnableInstructionCache (
 247   VOID
 248   );
 249
 250 VOID
 251 EFIAPI
 252 ArmDisableInstructionCache (
 253   VOID
 254   );
 255
 256 VOID
 257 EFIAPI
 258 ArmEnableMmu (
 259   VOID
 260   );
 261
 262 VOID
 263 EFIAPI
 264 ArmDisableMmu (
 265   VOID
 266   );
 267
 268 VOID
 269 EFIAPI
 270 ArmEnableCachesAndMmu (
 271   VOID
 272   );
 273
 274 VOID
 275 EFIAPI
 276 ArmDisableCachesAndMmu (
 277   VOID
 278   );
 279
 280 VOID
 281 EFIAPI
 282 ArmEnableInterrupts (
 283   VOID
 284   );
 285
 286 UINTN
 287 EFIAPI
 288 ArmDisableInterrupts (
 289   VOID
 290   );
 291
 292 BOOLEAN
 293 EFIAPI
 294 ArmGetInterruptState (
 295   VOID
 296   );
 297
 298 VOID
 299 EFIAPI
 300 ArmEnableAsynchronousAbort (
 301   VOID
 302   );
 303
 304 UINTN
 305 EFIAPI
 306 ArmDisableAsynchronousAbort (
 307   VOID
 308   );
 309
 310 VOID
 311 EFIAPI
 312 ArmEnableIrq (
 313   VOID
 314   );
 315
 316 UINTN
 317 EFIAPI
 318 ArmDisableIrq (
 319   VOID
 320   );
 321
 322 VOID
 323 EFIAPI
 324 ArmEnableFiq (
 325   VOID
 326   );
 327
 328 UINTN
 329 EFIAPI
 330 ArmDisableFiq (
 331   VOID
 332   );
 333
 334 BOOLEAN
 335 EFIAPI
 336 ArmGetFiqState (
 337   VOID
 338   );
 339
 340 /**
 341  * Invalidate Data and Instruction TLBs
 342  */
 343 VOID
 344 EFIAPI
 345 ArmInvalidateTlb (
 346   VOID
 347   );
 348
 349 VOID
 350 EFIAPI
 351 ArmUpdateTranslationTableEntry (
 352   IN  VOID     *TranslationTableEntry,
 353   IN  VOID     *Mva
 354   );
 355
 356 VOID
 357 EFIAPI
 358 ArmSetDomainAccessControl (
 359   IN  UINT32  Domain
 360   );
 361
 362 VOID
 363 EFIAPI
 364 ArmSetTTBR0 (
 365   IN  VOID  *TranslationTableBase
 366   );
 367
 368 VOID
 369 EFIAPI
 370 ArmSetTTBCR (
 371   IN  UINT32 Bits
 372   );
 373
 374 VOID *
 375 EFIAPI
 376 ArmGetTTBR0BaseAddress (
 377   VOID
 378   );
 379
 380 BOOLEAN
 381 EFIAPI
 382 ArmMmuEnabled (
 383   VOID
 384   );
 385
 386 VOID
 387 EFIAPI
 388 ArmEnableBranchPrediction (
 389   VOID
 390   );
 391
 392 VOID
 393 EFIAPI
 394 ArmDisableBranchPrediction (
 395   VOID
 396   );
 397
 398 VOID
 399 EFIAPI
 400 ArmSetLowVectors (
 401   VOID
 402   );
 403
 404 VOID
 405 EFIAPI
 406 ArmSetHighVectors (
 407   VOID
 408   );
 409
 410 VOID
 411 EFIAPI
 412 ArmDataMemoryBarrier (
 413   VOID
 414   );
 415
 416 VOID
 417 EFIAPI
 418 ArmDataSynchronizationBarrier (
 419   VOID
 420   );
 421
 422 VOID
 423 EFIAPI
 424 ArmInstructionSynchronizationBarrier (
 425   VOID
 426   );
 427
 428 VOID
 429 EFIAPI
 430 ArmWriteVBar (
 431   IN  UINTN   VectorBase
 432   );
 433
 434 UINTN
 435 EFIAPI
 436 ArmReadVBar (
 437   VOID
 438   );
 439
 440 VOID
 441 EFIAPI
 442 ArmWriteAuxCr (
 443   IN  UINT32    Bit
 444   );
 445
 446 UINT32
 447 EFIAPI
 448 ArmReadAuxCr (
 449   VOID
 450   );
 451
 452 VOID
 453 EFIAPI
 454 ArmSetAuxCrBit (
 455   IN  UINT32    Bits
 456   );
 457
 458 VOID
 459 EFIAPI
 460 ArmUnsetAuxCrBit (
 461   IN  UINT32    Bits
 462   );
 463
 464 VOID
 465 EFIAPI
 466 ArmCallSEV (
 467   VOID
 468   );
 469
 470 VOID
 471 EFIAPI
 472 ArmCallWFE (
 473   VOID
 474   );
 475
 476 VOID
 477 EFIAPI
 478 ArmCallWFI (
 479
 480   VOID
 481   );
 482
 483 UINTN
 484 EFIAPI
 485 ArmReadMpidr (
 486   VOID
 487   );
 488
 489 UINTN
 490 EFIAPI
 491 ArmReadMidr (
 492   VOID
 493   );
 494
 495 UINT32
 496 EFIAPI
 497 ArmReadCpacr (
 498   VOID
 499   );
 500
 501 VOID
 502 EFIAPI
 503 ArmWriteCpacr (
 504   IN  UINT32   Access
 505   );
 506
 507 VOID
 508 EFIAPI
 509 ArmEnableVFP (
 510   VOID
 511   );
 512
 513 /**
 514   Get the Secure Configuration Register value
 515
 516   @return   Value read from the Secure Configuration Register
 517
 518 **/
 519 UINT32
 520 EFIAPI
 521 ArmReadScr (
 522   VOID
 523   );
 524
 525 /**
 526   Set the Secure Configuration Register
 527
 528   @param Value   Value to write to the Secure Configuration Register
 529
 530 **/
 531 VOID
 532 EFIAPI
 533 ArmWriteScr (
 534   IN  UINT32   Value
 535   );
 536
 537 UINT32
 538 EFIAPI
 539 ArmReadMVBar (
 540   VOID
 541   );
 542
 543 VOID
 544 EFIAPI
 545 ArmWriteMVBar (
 546   IN  UINT32   VectorMonitorBase
 547   );
 548
 549 UINT32
 550 EFIAPI
 551 ArmReadSctlr (
 552   VOID
 553   );
 554
 555 VOID
 556 EFIAPI
 557 ArmWriteSctlr (
 558   IN  UINT32   Value
 559   );
 560
 561 UINTN
 562 EFIAPI
 563 ArmReadHVBar (
 564   VOID
 565   );
 566
 567 VOID
 568 EFIAPI
 569 ArmWriteHVBar (
 570   IN  UINTN   HypModeVectorBase
 571   );
 572
 573
 574 //
 575 // Helper functions for accessing CPU ACTLR
 576 //
 577
 578 UINTN
 579 EFIAPI
 580 ArmReadCpuActlr (
 581   VOID
 582   );
 583
 584 VOID
 585 EFIAPI
 586 ArmWriteCpuActlr (
 587   IN  UINTN Val
 588   );
 589
 590 VOID
 591 EFIAPI
 592 ArmSetCpuActlrBit (
 593   IN  UINTN    Bits
 594   );
 595
 596 VOID
 597 EFIAPI
 598 ArmUnsetCpuActlrBit (
 599   IN  UINTN    Bits
 600   );
 601
 602 //
 603 // Accessors for the architected generic timer registers
 604 //
 605
 606 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)
 607 #define ARM_ARCH_TIMER_IMASK            (1 << 1)
 608 #define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
 609
 610 UINTN
 611 EFIAPI
 612 ArmReadCntFrq (
 613   VOID
 614   );
 615
 616 VOID
 617 EFIAPI
 618 ArmWriteCntFrq (
 619   UINTN   FreqInHz
 620   );
 621
 622 UINT64
 623 EFIAPI
 624 ArmReadCntPct (
 625   VOID
 626   );
 627
 628 UINTN
 629 EFIAPI
 630 ArmReadCntkCtl (
 631   VOID
 632   );
 633
 634 VOID
 635 EFIAPI
 636 ArmWriteCntkCtl (
 637   UINTN   Val
 638   );
 639
 640 UINTN
 641 EFIAPI
 642 ArmReadCntpTval (
 643   VOID
 644   );
 645
 646 VOID
 647 EFIAPI
 648 ArmWriteCntpTval (
 649   UINTN   Val
 650   );
 651
 652 UINTN
 653 EFIAPI
 654 ArmReadCntpCtl (
 655   VOID
 656   );
 657
 658 VOID
 659 EFIAPI
 660 ArmWriteCntpCtl (
 661   UINTN   Val
 662   );
 663
 664 UINTN
 665 EFIAPI
 666 ArmReadCntvTval (
 667   VOID
 668   );
 669
 670 VOID
 671 EFIAPI
 672 ArmWriteCntvTval (
 673   UINTN   Val
 674   );
 675
 676 UINTN
 677 EFIAPI
 678 ArmReadCntvCtl (
 679   VOID
 680   );
 681
 682 VOID
 683 EFIAPI
 684 ArmWriteCntvCtl (
 685   UINTN   Val
 686   );
 687
 688 UINT64
 689 EFIAPI
 690 ArmReadCntvCt (
 691   VOID
 692   );
 693
 694 UINT64
 695 EFIAPI
 696 ArmReadCntpCval (
 697   VOID
 698   );
 699
 700 VOID
 701 EFIAPI
 702 ArmWriteCntpCval (
 703   UINT64   Val
 704   );
 705
 706 UINT64
 707 EFIAPI
 708 ArmReadCntvCval (
 709   VOID
 710   );
 711
 712 VOID
 713 EFIAPI
 714 ArmWriteCntvCval (
 715   UINT64   Val
 716   );
 717
 718 UINT64
 719 EFIAPI
 720 ArmReadCntvOff (
 721   VOID
 722   );
 723
 724 VOID
 725 EFIAPI
 726 ArmWriteCntvOff (
 727   UINT64   Val
 728   );
 729
 730 UINTN
 731 EFIAPI
 732 ArmGetPhysicalAddressBits (
 733   VOID
 734   );
 735
 736 #endif // __ARM_LIB__