3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include <Uefi/UefiBaseType.h>
23 #include <Chipset/ARM1176JZ-S.h>
25 #include <Chipset/ArmV7.h>
27 #elif defined(MDE_CPU_AARCH64)
28 #include <Chipset/AArch64.h>
30 #error "Unknown chipset."
34 ARM_CACHE_TYPE_WRITE_BACK
,
35 ARM_CACHE_TYPE_UNKNOWN
39 ARM_CACHE_ARCHITECTURE_UNIFIED
,
40 ARM_CACHE_ARCHITECTURE_SEPARATE
,
41 ARM_CACHE_ARCHITECTURE_UNKNOWN
42 } ARM_CACHE_ARCHITECTURE
;
46 ARM_CACHE_ARCHITECTURE Architecture
;
47 BOOLEAN DataCachePresent
;
49 UINTN DataCacheAssociativity
;
50 UINTN DataCacheLineLength
;
51 BOOLEAN InstructionCachePresent
;
52 UINTN InstructionCacheSize
;
53 UINTN InstructionCacheAssociativity
;
54 UINTN InstructionCacheLineLength
;
58 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
60 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
61 * be used in Secure World to distinguished Secure to Non-Secure memory.
64 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
65 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
66 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
67 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
68 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
69 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
70 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
71 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
72 } ARM_MEMORY_REGION_ATTRIBUTES
;
74 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
77 EFI_PHYSICAL_ADDRESS PhysicalBase
;
78 EFI_VIRTUAL_ADDRESS VirtualBase
;
80 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
81 } ARM_MEMORY_REGION_DESCRIPTOR
;
83 typedef VOID (*CACHE_OPERATION
)(VOID
);
84 typedef VOID (*LINE_OPERATION
)(UINTN
);
90 ARM_PROCESSOR_MODE_USER
= 0x10,
91 ARM_PROCESSOR_MODE_FIQ
= 0x11,
92 ARM_PROCESSOR_MODE_IRQ
= 0x12,
93 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
94 ARM_PROCESSOR_MODE_ABORT
= 0x17,
95 ARM_PROCESSOR_MODE_HYP
= 0x1A,
96 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
97 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
98 ARM_PROCESSOR_MODE_MASK
= 0x1F
104 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
105 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
106 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
107 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
108 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
109 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
111 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
112 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
113 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
114 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
115 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
116 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
121 #define ARM_CORE_AFF0 0xFF
122 #define ARM_CORE_AFF1 (0xFF << 8)
123 #define ARM_CORE_AFF2 (0xFF << 16)
124 #define ARM_CORE_AFF3 (0xFFULL << 32)
126 #define ARM_CORE_MASK ARM_CORE_AFF0
127 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
128 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
129 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
130 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
131 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
139 ARM_CACHE_ARCHITECTURE
141 ArmCacheArchitecture (
147 ArmCacheInformation (
148 OUT ARM_CACHE_INFO
*CacheInfo
153 ArmDataCachePresent (
165 ArmDataCacheAssociativity (
171 ArmDataCacheLineLength (
177 ArmInstructionCachePresent (
183 ArmInstructionCacheSize (
189 ArmInstructionCacheAssociativity (
195 ArmInstructionCacheLineLength (
201 ArmIsArchTimerImplemented (
231 ArmInvalidateDataCache (
238 ArmCleanInvalidateDataCache (
250 ArmCleanDataCacheToPoU (
256 ArmInvalidateInstructionCache (
262 ArmInvalidateDataCacheEntryByMVA (
268 ArmCleanDataCacheEntryByMVA (
274 ArmCleanInvalidateDataCacheEntryByMVA (
280 ArmInvalidateDataCacheEntryBySetWay (
281 IN UINTN SetWayFormat
286 ArmCleanDataCacheEntryBySetWay (
287 IN UINTN SetWayFormat
292 ArmCleanInvalidateDataCacheEntryBySetWay (
293 IN UINTN SetWayFormat
304 ArmDisableDataCache (
310 ArmEnableInstructionCache (
316 ArmDisableInstructionCache (
334 ArmEnableCachesAndMmu (
340 ArmDisableCachesAndMmu (
346 ArmEnableInterrupts (
352 ArmDisableInterrupts (
358 ArmGetInterruptState (
364 ArmEnableAsynchronousAbort (
370 ArmDisableAsynchronousAbort (
405 * Invalidate Data and Instruction TLBs
415 ArmUpdateTranslationTableEntry (
416 IN VOID
*TranslationTableEntry
,
422 ArmSetDomainAccessControl (
429 IN VOID
*TranslationTableBase
434 ArmGetTTBR0BaseAddress (
441 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
442 OUT VOID
**TranslationTableBase OPTIONAL
,
443 OUT UINTN
*TranslationTableSize OPTIONAL
454 ArmEnableBranchPrediction (
460 ArmDisableBranchPrediction (
478 ArmDrainWriteBuffer (
484 ArmDataMemoryBarrier (
490 ArmDataSyncronizationBarrier (
496 ArmInstructionSynchronizationBarrier (
586 Get the Secure Configuration Register value
588 @return Value read from the Secure Configuration Register
598 Set the Secure Configuration Register
600 @param Value Value to write to the Secure Configuration Register
618 IN UINT32 VectorMonitorBase
636 IN UINTN HypModeVectorBase
641 // Helper functions for accessing CPU ACTLR
664 ArmUnsetCpuActlrBit (
668 #endif // __ARM_LIB__