[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __ARM_LIB__\r
#define __ARM_LIB__\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #ifdef ARM_CPU_ARMv6\r
    #include <Chipset/ARM1176JZ-S.h>\r
  #else\r
    #include <Chipset/ArmV7.h>\r
  #endif\r
#elif defined(MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
 #error "Unknown chipset."\r
#endif\r
\r
typedef enum {\r
  ARM_CACHE_TYPE_WRITE_BACK,\r
  ARM_CACHE_TYPE_UNKNOWN\r
} ARM_CACHE_TYPE;\r
\r
typedef enum {\r
  ARM_CACHE_ARCHITECTURE_UNIFIED,\r
  ARM_CACHE_ARCHITECTURE_SEPARATE,\r
  ARM_CACHE_ARCHITECTURE_UNKNOWN\r
} ARM_CACHE_ARCHITECTURE;\r
\r
typedef struct {\r
  ARM_CACHE_TYPE          Type;\r
  ARM_CACHE_ARCHITECTURE  Architecture;\r
  BOOLEAN                 DataCachePresent;\r
  UINTN                   DataCacheSize;\r
  UINTN                   DataCacheAssociativity;\r
  UINTN                   DataCacheLineLength;\r
  BOOLEAN                 InstructionCachePresent;\r
  UINTN                   InstructionCacheSize;\r
  UINTN                   InstructionCacheAssociativity;\r
  UINTN                   InstructionCacheLineLength;\r
} ARM_CACHE_INFO;\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
  UINT64                        Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(VOID);\r
typedef VOID (*LINE_OPERATION)(UINTN);\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0         0xFF\r
#define ARM_CORE_AFF1         (0xFF << 8)\r
#define ARM_CORE_AFF2         (0xFF << 16)\r
#define ARM_CORE_AFF3         (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK         ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
ARM_CACHE_TYPE\r
EFIAPI\r
ArmCacheType (\r
  VOID\r
  );\r
\r
ARM_CACHE_ARCHITECTURE\r
EFIAPI\r
ArmCacheArchitecture (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCacheInformation (\r
  OUT ARM_CACHE_INFO  *CacheInfo\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmDataCachePresent (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheSize (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheAssociativity (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmInstructionCachePresent (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheSize (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheAssociativity (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr0 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr1 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheToPoU (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN   SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID     *TranslationTableEntry,\r
  IN  VOID     *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
RETURN_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,\r
  OUT VOID                         **TranslationTableBase OPTIONAL,\r
  OUT UINTN                         *TranslationTableSize  OPTIONAL\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDrainWriteBuffer (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSyncronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN   VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32    Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32   Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32   Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32   VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN   HypModeVectorBase\r
  );\r
\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
#endif // __ARM_LIB__\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
90ed18ca	4	Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r
1e57a462	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef __ARM_LIB__\r
	17	#define __ARM_LIB__\r
	18	\r
	19	#include <Uefi/UefiBaseType.h>\r
	20	\r
25402f5d HL	21	#ifdef MDE_CPU_ARM\r
	22	#ifdef ARM_CPU_ARMv6\r
	23	#include <Chipset/ARM1176JZ-S.h>\r
	24	#else\r
	25	#include <Chipset/ArmV7.h>\r
	26	#endif\r
	27	#elif defined(MDE_CPU_AARCH64)\r
	28	#include <Chipset/AArch64.h>\r
1e57a462	29	#else\r
25402f5d	30	#error "Unknown chipset."\r
1e57a462	31	#endif\r
	32	\r
	33	typedef enum {\r
	34	ARM_CACHE_TYPE_WRITE_BACK,\r
	35	ARM_CACHE_TYPE_UNKNOWN\r
	36	} ARM_CACHE_TYPE;\r
	37	\r
	38	typedef enum {\r
	39	ARM_CACHE_ARCHITECTURE_UNIFIED,\r
	40	ARM_CACHE_ARCHITECTURE_SEPARATE,\r
	41	ARM_CACHE_ARCHITECTURE_UNKNOWN\r
	42	} ARM_CACHE_ARCHITECTURE;\r
	43	\r
	44	typedef struct {\r
	45	ARM_CACHE_TYPE Type;\r
	46	ARM_CACHE_ARCHITECTURE Architecture;\r
	47	BOOLEAN DataCachePresent;\r
	48	UINTN DataCacheSize;\r
	49	UINTN DataCacheAssociativity;\r
	50	UINTN DataCacheLineLength;\r
	51	BOOLEAN InstructionCachePresent;\r
	52	UINTN InstructionCacheSize;\r
	53	UINTN InstructionCacheAssociativity;\r
	54	UINTN InstructionCacheLineLength;\r
	55	} ARM_CACHE_INFO;\r
	56	\r
	57	/**\r
	58	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	59	*\r
	60	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	61	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	62	*/\r
	63	typedef enum {\r
	64	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	65	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	66	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	67	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
	68	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	69	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	70	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	71	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	72	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	73	\r
	74	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
	75	\r
	76	typedef struct {\r
	77	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	78	EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a	79	UINT64 Length;\r
1e57a462	80	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
	81	} ARM_MEMORY_REGION_DESCRIPTOR;\r
	82	\r
	83	typedef VOID (*CACHE_OPERATION)(VOID);\r
	84	typedef VOID (*LINE_OPERATION)(UINTN);\r
	85	\r
	86	//\r
	87	// ARM Processor Mode\r
	88	//\r
	89	typedef enum {\r
	90	ARM_PROCESSOR_MODE_USER = 0x10,\r
	91	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	92	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	93	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	94	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	95	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	96	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	97	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	98	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	99	} ARM_PROCESSOR_MODE;\r
	100	\r
	101	//\r
	102	// ARM Cpu IDs\r
	103	//\r
	104	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	105	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	106	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	107	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	108	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	109	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	110	\r
	111	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	112	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	113	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	114	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	115	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	116	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
	117	\r
	118	//\r
	119	// ARM MP Core IDs\r
	120	//\r
90ed18ca OM	121	#define ARM_CORE_AFF0 0xFF\r
	122	#define ARM_CORE_AFF1 (0xFF << 8)\r
	123	#define ARM_CORE_AFF2 (0xFF << 16)\r
	124	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	125	\r
	126	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	127	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
1e57a462	128	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
1e57a462	129	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e	130	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
1e57a462	131	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
	132	\r
	133	ARM_CACHE_TYPE\r
	134	EFIAPI\r
	135	ArmCacheType (\r
	136	VOID\r
	137	);\r
	138	\r
	139	ARM_CACHE_ARCHITECTURE\r
	140	EFIAPI\r
	141	ArmCacheArchitecture (\r
	142	VOID\r
	143	);\r
	144	\r
	145	VOID\r
	146	EFIAPI\r
	147	ArmCacheInformation (\r
	148	OUT ARM_CACHE_INFO *CacheInfo\r
	149	);\r
	150	\r
	151	BOOLEAN\r
	152	EFIAPI\r
	153	ArmDataCachePresent (\r
	154	VOID\r
	155	);\r
3402aac7	156	\r
1e57a462	157	UINTN\r
	158	EFIAPI\r
	159	ArmDataCacheSize (\r
	160	VOID\r
	161	);\r
3402aac7	162	\r
1e57a462	163	UINTN\r
	164	EFIAPI\r
	165	ArmDataCacheAssociativity (\r
	166	VOID\r
	167	);\r
3402aac7	168	\r
1e57a462	169	UINTN\r
	170	EFIAPI\r
	171	ArmDataCacheLineLength (\r
	172	VOID\r
	173	);\r
3402aac7	174	\r
1e57a462	175	BOOLEAN\r
	176	EFIAPI\r
	177	ArmInstructionCachePresent (\r
	178	VOID\r
	179	);\r
3402aac7	180	\r
1e57a462	181	UINTN\r
	182	EFIAPI\r
	183	ArmInstructionCacheSize (\r
	184	VOID\r
	185	);\r
3402aac7	186	\r
1e57a462	187	UINTN\r
	188	EFIAPI\r
	189	ArmInstructionCacheAssociativity (\r
	190	VOID\r
	191	);\r
3402aac7	192	\r
1e57a462	193	UINTN\r
	194	EFIAPI\r
	195	ArmInstructionCacheLineLength (\r
	196	VOID\r
	197	);\r
168d7245 OM	198	\r
	199	UINTN\r
	200	EFIAPI\r
	201	ArmIsArchTimerImplemented (\r
	202	VOID\r
	203	);\r
	204	\r
	205	UINTN\r
	206	EFIAPI\r
	207	ArmReadIdPfr0 (\r
	208	VOID\r
	209	);\r
	210	\r
	211	UINTN\r
	212	EFIAPI\r
	213	ArmReadIdPfr1 (\r
	214	VOID\r
	215	);\r
	216	\r
64751727	217	UINTN\r
1e57a462	218	EFIAPI\r
64751727	219	ArmCacheInfo (\r
1e57a462	220	VOID\r
	221	);\r
	222	\r
	223	BOOLEAN\r
	224	EFIAPI\r
	225	ArmIsMpCore (\r
	226	VOID\r
	227	);\r
	228	\r
	229	VOID\r
	230	EFIAPI\r
	231	ArmInvalidateDataCache (\r
	232	VOID\r
	233	);\r
	234	\r
	235	\r
	236	VOID\r
	237	EFIAPI\r
	238	ArmCleanInvalidateDataCache (\r
	239	VOID\r
	240	);\r
	241	\r
	242	VOID\r
	243	EFIAPI\r
	244	ArmCleanDataCache (\r
	245	VOID\r
	246	);\r
	247	\r
	248	VOID\r
	249	EFIAPI\r
	250	ArmCleanDataCacheToPoU (\r
	251	VOID\r
	252	);\r
	253	\r
	254	VOID\r
	255	EFIAPI\r
	256	ArmInvalidateInstructionCache (\r
	257	VOID\r
	258	);\r
	259	\r
	260	VOID\r
	261	EFIAPI\r
	262	ArmInvalidateDataCacheEntryByMVA (\r
	263	IN UINTN Address\r
	264	);\r
	265	\r
	266	VOID\r
	267	EFIAPI\r
	268	ArmCleanDataCacheEntryByMVA (\r
	269	IN UINTN Address\r
	270	);\r
	271	\r
	272	VOID\r
	273	EFIAPI\r
	274	ArmCleanInvalidateDataCacheEntryByMVA (\r
	275	IN UINTN Address\r
	276	);\r
	277	\r
0ff0e414 OM	278	VOID\r
	279	EFIAPI\r
	280	ArmInvalidateDataCacheEntryBySetWay (\r
	281	IN UINTN SetWayFormat\r
	282	);\r
	283	\r
	284	VOID\r
	285	EFIAPI\r
	286	ArmCleanDataCacheEntryBySetWay (\r
	287	IN UINTN SetWayFormat\r
	288	);\r
	289	\r
	290	VOID\r
	291	EFIAPI\r
	292	ArmCleanInvalidateDataCacheEntryBySetWay (\r
	293	IN UINTN SetWayFormat\r
	294	);\r
	295	\r
1e57a462	296	VOID\r
	297	EFIAPI\r
	298	ArmEnableDataCache (\r
	299	VOID\r
	300	);\r
	301	\r
	302	VOID\r
	303	EFIAPI\r
	304	ArmDisableDataCache (\r
	305	VOID\r
	306	);\r
	307	\r
	308	VOID\r
	309	EFIAPI\r
	310	ArmEnableInstructionCache (\r
	311	VOID\r
	312	);\r
	313	\r
	314	VOID\r
	315	EFIAPI\r
	316	ArmDisableInstructionCache (\r
	317	VOID\r
	318	);\r
3402aac7	319	\r
1e57a462	320	VOID\r
	321	EFIAPI\r
	322	ArmEnableMmu (\r
	323	VOID\r
	324	);\r
	325	\r
	326	VOID\r
	327	EFIAPI\r
	328	ArmDisableMmu (\r
	329	VOID\r
	330	);\r
	331	\r
0ff0e414 OM	332	VOID\r
	333	EFIAPI\r
	334	ArmEnableCachesAndMmu (\r
	335	VOID\r
	336	);\r
	337	\r
1e57a462	338	VOID\r
	339	EFIAPI\r
	340	ArmDisableCachesAndMmu (\r
	341	VOID\r
	342	);\r
	343	\r
1e57a462	344	VOID\r
	345	EFIAPI\r
	346	ArmEnableInterrupts (\r
	347	VOID\r
	348	);\r
	349	\r
	350	UINTN\r
	351	EFIAPI\r
	352	ArmDisableInterrupts (\r
	353	VOID\r
	354	);\r
47585ed5	355	\r
1e57a462	356	BOOLEAN\r
	357	EFIAPI\r
	358	ArmGetInterruptState (\r
	359	VOID\r
	360	);\r
	361	\r
0ff0e414 OM	362	VOID\r
	363	EFIAPI\r
	364	ArmEnableAsynchronousAbort (\r
	365	VOID\r
	366	);\r
	367	\r
47585ed5	368	UINTN\r
47585ed5	369	EFIAPI\r
0ff0e414	370	ArmDisableAsynchronousAbort (\r
47585ed5	371	VOID\r
	372	);\r
	373	\r
	374	VOID\r
	375	EFIAPI\r
	376	ArmEnableIrq (\r
	377	VOID\r
	378	);\r
	379	\r
0ff0e414 OM	380	UINTN\r
	381	EFIAPI\r
	382	ArmDisableIrq (\r
	383	VOID\r
	384	);\r
	385	\r
1e57a462	386	VOID\r
	387	EFIAPI\r
	388	ArmEnableFiq (\r
	389	VOID\r
	390	);\r
	391	\r
	392	UINTN\r
	393	EFIAPI\r
	394	ArmDisableFiq (\r
	395	VOID\r
	396	);\r
3402aac7	397	\r
1e57a462	398	BOOLEAN\r
	399	EFIAPI\r
	400	ArmGetFiqState (\r
	401	VOID\r
	402	);\r
	403	\r
8dd618d2 OM	404	/**\r
	405	* Invalidate Data and Instruction TLBs\r
	406	*/\r
1e57a462	407	VOID\r
	408	EFIAPI\r
	409	ArmInvalidateTlb (\r
	410	VOID\r
	411	);\r
3402aac7	412	\r
1e57a462	413	VOID\r
	414	EFIAPI\r
	415	ArmUpdateTranslationTableEntry (\r
	416	IN VOID *TranslationTableEntry,\r
	417	IN VOID *Mva\r
	418	);\r
3402aac7	419	\r
1e57a462	420	VOID\r
	421	EFIAPI\r
	422	ArmSetDomainAccessControl (\r
	423	IN UINT32 Domain\r
	424	);\r
	425	\r
	426	VOID\r
	427	EFIAPI\r
	428	ArmSetTTBR0 (\r
	429	IN VOID *TranslationTableBase\r
	430	);\r
	431	\r
	432	VOID *\r
	433	EFIAPI\r
	434	ArmGetTTBR0BaseAddress (\r
	435	VOID\r
	436	);\r
	437	\r
6f050ad6	438	RETURN_STATUS\r
1e57a462	439	EFIAPI\r
	440	ArmConfigureMmu (\r
	441	IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
6f050ad6	442	OUT VOID **TranslationTableBase OPTIONAL,\r
1e57a462	443	OUT UINTN *TranslationTableSize OPTIONAL\r
1e57a462	444	);\r
3402aac7	445	\r
1e57a462	446	BOOLEAN\r
	447	EFIAPI\r
	448	ArmMmuEnabled (\r
	449	VOID\r
	450	);\r
3402aac7	451	\r
1e57a462	452	VOID\r
	453	EFIAPI\r
	454	ArmEnableBranchPrediction (\r
	455	VOID\r
	456	);\r
	457	\r
	458	VOID\r
	459	EFIAPI\r
	460	ArmDisableBranchPrediction (\r
	461	VOID\r
	462	);\r
	463	\r
	464	VOID\r
	465	EFIAPI\r
	466	ArmSetLowVectors (\r
	467	VOID\r
	468	);\r
	469	\r
	470	VOID\r
	471	EFIAPI\r
	472	ArmSetHighVectors (\r
	473	VOID\r
	474	);\r
	475	\r
0ff0e414 OM	476	VOID\r
	477	EFIAPI\r
	478	ArmDrainWriteBuffer (\r
	479	VOID\r
	480	);\r
	481	\r
1e57a462	482	VOID\r
	483	EFIAPI\r
	484	ArmDataMemoryBarrier (\r
	485	VOID\r
	486	);\r
3402aac7	487	\r
1e57a462	488	VOID\r
	489	EFIAPI\r
	490	ArmDataSyncronizationBarrier (\r
	491	VOID\r
	492	);\r
3402aac7	493	\r
1e57a462	494	VOID\r
	495	EFIAPI\r
	496	ArmInstructionSynchronizationBarrier (\r
	497	VOID\r
	498	);\r
	499	\r
	500	VOID\r
	501	EFIAPI\r
	502	ArmWriteVBar (\r
4e57d6d7	503	IN UINTN VectorBase\r
1e57a462	504	);\r
1e57a462	505	\r
4e57d6d7	506	UINTN\r
1e57a462	507	EFIAPI\r
	508	ArmReadVBar (\r
	509	VOID\r
	510	);\r
	511	\r
	512	VOID\r
	513	EFIAPI\r
	514	ArmWriteAuxCr (\r
	515	IN UINT32 Bit\r
	516	);\r
	517	\r
	518	UINT32\r
	519	EFIAPI\r
	520	ArmReadAuxCr (\r
	521	VOID\r
	522	);\r
	523	\r
	524	VOID\r
	525	EFIAPI\r
	526	ArmSetAuxCrBit (\r
	527	IN UINT32 Bits\r
	528	);\r
	529	\r
	530	VOID\r
	531	EFIAPI\r
	532	ArmUnsetAuxCrBit (\r
	533	IN UINT32 Bits\r
	534	);\r
	535	\r
	536	VOID\r
	537	EFIAPI\r
	538	ArmCallSEV (\r
	539	VOID\r
	540	);\r
	541	\r
	542	VOID\r
	543	EFIAPI\r
	544	ArmCallWFE (\r
	545	VOID\r
	546	);\r
	547	\r
	548	VOID\r
	549	EFIAPI\r
	550	ArmCallWFI (\r
25402f5d	551	\r
1e57a462	552	VOID\r
	553	);\r
	554	\r
	555	UINTN\r
	556	EFIAPI\r
	557	ArmReadMpidr (\r
	558	VOID\r
	559	);\r
	560	\r
9401d6f4 OM	561	UINTN\r
	562	EFIAPI\r
	563	ArmReadMidr (\r
	564	VOID\r
	565	);\r
	566	\r
1e57a462	567	UINT32\r
	568	EFIAPI\r
	569	ArmReadCpacr (\r
	570	VOID\r
	571	);\r
	572	\r
	573	VOID\r
	574	EFIAPI\r
	575	ArmWriteCpacr (\r
	576	IN UINT32 Access\r
	577	);\r
	578	\r
	579	VOID\r
	580	EFIAPI\r
	581	ArmEnableVFP (\r
	582	VOID\r
	583	);\r
	584	\r
46d4d75c OM	585	/**\r
	586	Get the Secure Configuration Register value\r
	587	\r
	588	@return Value read from the Secure Configuration Register\r
	589	\r
	590	**/\r
1e57a462	591	UINT32\r
	592	EFIAPI\r
	593	ArmReadScr (\r
	594	VOID\r
	595	);\r
	596	\r
46d4d75c OM	597	/**\r
	598	Set the Secure Configuration Register\r
	599	\r
	600	@param Value Value to write to the Secure Configuration Register\r
	601	\r
	602	**/\r
1e57a462	603	VOID\r
	604	EFIAPI\r
	605	ArmWriteScr (\r
46d4d75c	606	IN UINT32 Value\r
1e57a462	607	);\r
	608	\r
	609	UINT32\r
	610	EFIAPI\r
	611	ArmReadMVBar (\r
	612	VOID\r
	613	);\r
	614	\r
	615	VOID\r
	616	EFIAPI\r
	617	ArmWriteMVBar (\r
	618	IN UINT32 VectorMonitorBase\r
	619	);\r
	620	\r
	621	UINT32\r
	622	EFIAPI\r
	623	ArmReadSctlr (\r
	624	VOID\r
	625	);\r
	626	\r
5ea2c2d3	627	UINTN\r
	628	EFIAPI\r
	629	ArmReadHVBar (\r
	630	VOID\r
	631	);\r
	632	\r
	633	VOID\r
	634	EFIAPI\r
	635	ArmWriteHVBar (\r
	636	IN UINTN HypModeVectorBase\r
	637	);\r
	638	\r
52d44f77 OM	639	\r
	640	//\r
	641	// Helper functions for accessing CPU ACTLR\r
	642	//\r
	643	\r
	644	UINTN\r
	645	EFIAPI\r
	646	ArmReadCpuActlr (\r
	647	VOID\r
	648	);\r
	649	\r
	650	VOID\r
	651	EFIAPI\r
	652	ArmWriteCpuActlr (\r
	653	IN UINTN Val\r
	654	);\r
	655	\r
	656	VOID\r
	657	EFIAPI\r
	658	ArmSetCpuActlrBit (\r
	659	IN UINTN Bits\r
	660	);\r
	661	\r
	662	VOID\r
	663	EFIAPI\r
	664	ArmUnsetCpuActlrBit (\r
	665	IN UINTN Bits\r
	666	);\r
	667	\r
1e57a462	668	#endif // __ARM_LIB__\r