projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 1e57a462 | 1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| 4e57d6d7 | 4 | Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r |
| 1e57a462 | 5 | \r |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef __ARM_LIB__\r | |
| 17 | #define __ARM_LIB__\r | |
| 18 | \r | |
| 19 | #include <Uefi/UefiBaseType.h>\r | |
| 20 | \r | |
| 25402f5d HL |
21 | #ifdef MDE_CPU_ARM\r |
| 22 | #ifdef ARM_CPU_ARMv6\r | |
| 23 | #include <Chipset/ARM1176JZ-S.h>\r | |
| 24 | #else\r | |
| 25 | #include <Chipset/ArmV7.h>\r | |
| 26 | #endif\r | |
| 27 | #elif defined(MDE_CPU_AARCH64)\r | |
| 28 | #include <Chipset/AArch64.h>\r | |
| 1e57a462 | 29 | #else\r |
| 25402f5d | 30 | #error "Unknown chipset."\r |
| 1e57a462 | 31 | #endif\r |
| 32 | \r | |
| 33 | typedef enum {\r | |
| 34 | ARM_CACHE_TYPE_WRITE_BACK,\r | |
| 35 | ARM_CACHE_TYPE_UNKNOWN\r | |
| 36 | } ARM_CACHE_TYPE;\r | |
| 37 | \r | |
| 38 | typedef enum {\r | |
| 39 | ARM_CACHE_ARCHITECTURE_UNIFIED,\r | |
| 40 | ARM_CACHE_ARCHITECTURE_SEPARATE,\r | |
| 41 | ARM_CACHE_ARCHITECTURE_UNKNOWN\r | |
| 42 | } ARM_CACHE_ARCHITECTURE;\r | |
| 43 | \r | |
| 44 | typedef struct {\r | |
| 45 | ARM_CACHE_TYPE Type;\r | |
| 46 | ARM_CACHE_ARCHITECTURE Architecture;\r | |
| 47 | BOOLEAN DataCachePresent;\r | |
| 48 | UINTN DataCacheSize;\r | |
| 49 | UINTN DataCacheAssociativity;\r | |
| 50 | UINTN DataCacheLineLength;\r | |
| 51 | BOOLEAN InstructionCachePresent;\r | |
| 52 | UINTN InstructionCacheSize;\r | |
| 53 | UINTN InstructionCacheAssociativity;\r | |
| 54 | UINTN InstructionCacheLineLength;\r | |
| 55 | } ARM_CACHE_INFO;\r | |
| 56 | \r | |
| 57 | /**\r | |
| 58 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r | |
| 59 | *\r | |
| 60 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r | |
| 61 | * be used in Secure World to distinguished Secure to Non-Secure memory.\r | |
| 62 | */\r | |
| 63 | typedef enum {\r | |
| 64 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r | |
| 65 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r | |
| 66 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r | |
| 67 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r | |
| 68 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r | |
| 69 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r | |
| 70 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r | |
| 71 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r | |
| 72 | } ARM_MEMORY_REGION_ATTRIBUTES;\r | |
| 73 | \r | |
| 74 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r | |
| 75 | \r | |
| 76 | typedef struct {\r | |
| 77 | EFI_PHYSICAL_ADDRESS PhysicalBase;\r | |
| 78 | EFI_VIRTUAL_ADDRESS VirtualBase;\r | |
| c357fd6a | 79 | UINT64 Length;\r |
| 1e57a462 | 80 | ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r |
| 81 | } ARM_MEMORY_REGION_DESCRIPTOR;\r | |
| 82 | \r | |
| 83 | typedef VOID (*CACHE_OPERATION)(VOID);\r | |
| 84 | typedef VOID (*LINE_OPERATION)(UINTN);\r | |
| 85 | \r | |
| 86 | //\r | |
| 87 | // ARM Processor Mode\r | |
| 88 | //\r | |
| 89 | typedef enum {\r | |
| 90 | ARM_PROCESSOR_MODE_USER = 0x10,\r | |
| 91 | ARM_PROCESSOR_MODE_FIQ = 0x11,\r | |
| 92 | ARM_PROCESSOR_MODE_IRQ = 0x12,\r | |
| 93 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r | |
| 94 | ARM_PROCESSOR_MODE_ABORT = 0x17,\r | |
| 95 | ARM_PROCESSOR_MODE_HYP = 0x1A,\r | |
| 96 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r | |
| 97 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r | |
| 98 | ARM_PROCESSOR_MODE_MASK = 0x1F\r | |
| 99 | } ARM_PROCESSOR_MODE;\r | |
| 100 | \r | |
| 101 | //\r | |
| 102 | // ARM Cpu IDs\r | |
| 103 | //\r | |
| 104 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r | |
| 105 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r | |
| 106 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r | |
| 107 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r | |
| 108 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r | |
| 109 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r | |
| 110 | \r | |
| 111 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r | |
| 112 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r | |
| 113 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r | |
| 114 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r | |
| 115 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r | |
| 116 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r | |
| 117 | \r | |
| 118 | //\r | |
| 119 | // ARM MP Core IDs\r | |
| 120 | //\r | |
| 1e57a462 | 121 | #define ARM_CORE_MASK 0xFF\r |
| 122 | #define ARM_CLUSTER_MASK (0xFF << 8)\r | |
| 123 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r | |
| 124 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r | |
| e359565e | 125 | #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r |
| 1e57a462 | 126 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r |
| 127 | \r | |
| 128 | ARM_CACHE_TYPE\r | |
| 129 | EFIAPI\r | |
| 130 | ArmCacheType (\r | |
| 131 | VOID\r | |
| 132 | );\r | |
| 133 | \r | |
| 134 | ARM_CACHE_ARCHITECTURE\r | |
| 135 | EFIAPI\r | |
| 136 | ArmCacheArchitecture (\r | |
| 137 | VOID\r | |
| 138 | );\r | |
| 139 | \r | |
| 140 | VOID\r | |
| 141 | EFIAPI\r | |
| 142 | ArmCacheInformation (\r | |
| 143 | OUT ARM_CACHE_INFO *CacheInfo\r | |
| 144 | );\r | |
| 145 | \r | |
| 146 | BOOLEAN\r | |
| 147 | EFIAPI\r | |
| 148 | ArmDataCachePresent (\r | |
| 149 | VOID\r | |
| 150 | );\r | |
| 3402aac7 | 151 | \r |
| 1e57a462 | 152 | UINTN\r |
| 153 | EFIAPI\r | |
| 154 | ArmDataCacheSize (\r | |
| 155 | VOID\r | |
| 156 | );\r | |
| 3402aac7 | 157 | \r |
| 1e57a462 | 158 | UINTN\r |
| 159 | EFIAPI\r | |
| 160 | ArmDataCacheAssociativity (\r | |
| 161 | VOID\r | |
| 162 | );\r | |
| 3402aac7 | 163 | \r |
| 1e57a462 | 164 | UINTN\r |
| 165 | EFIAPI\r | |
| 166 | ArmDataCacheLineLength (\r | |
| 167 | VOID\r | |
| 168 | );\r | |
| 3402aac7 | 169 | \r |
| 1e57a462 | 170 | BOOLEAN\r |
| 171 | EFIAPI\r | |
| 172 | ArmInstructionCachePresent (\r | |
| 173 | VOID\r | |
| 174 | );\r | |
| 3402aac7 | 175 | \r |
| 1e57a462 | 176 | UINTN\r |
| 177 | EFIAPI\r | |
| 178 | ArmInstructionCacheSize (\r | |
| 179 | VOID\r | |
| 180 | );\r | |
| 3402aac7 | 181 | \r |
| 1e57a462 | 182 | UINTN\r |
| 183 | EFIAPI\r | |
| 184 | ArmInstructionCacheAssociativity (\r | |
| 185 | VOID\r | |
| 186 | );\r | |
| 3402aac7 | 187 | \r |
| 1e57a462 | 188 | UINTN\r |
| 189 | EFIAPI\r | |
| 190 | ArmInstructionCacheLineLength (\r | |
| 191 | VOID\r | |
| 192 | );\r | |
| 168d7245 OM |
193 | \r |
| 194 | UINTN\r | |
| 195 | EFIAPI\r | |
| 196 | ArmIsArchTimerImplemented (\r | |
| 197 | VOID\r | |
| 198 | );\r | |
| 199 | \r | |
| 200 | UINTN\r | |
| 201 | EFIAPI\r | |
| 202 | ArmReadIdPfr0 (\r | |
| 203 | VOID\r | |
| 204 | );\r | |
| 205 | \r | |
| 206 | UINTN\r | |
| 207 | EFIAPI\r | |
| 208 | ArmReadIdPfr1 (\r | |
| 209 | VOID\r | |
| 210 | );\r | |
| 211 | \r | |
| 64751727 | 212 | UINTN\r |
| 1e57a462 | 213 | EFIAPI\r |
| 64751727 | 214 | ArmCacheInfo (\r |
| 1e57a462 | 215 | VOID\r |
| 216 | );\r | |
| 217 | \r | |
| 218 | BOOLEAN\r | |
| 219 | EFIAPI\r | |
| 220 | ArmIsMpCore (\r | |
| 221 | VOID\r | |
| 222 | );\r | |
| 223 | \r | |
| 224 | VOID\r | |
| 225 | EFIAPI\r | |
| 226 | ArmInvalidateDataCache (\r | |
| 227 | VOID\r | |
| 228 | );\r | |
| 229 | \r | |
| 230 | \r | |
| 231 | VOID\r | |
| 232 | EFIAPI\r | |
| 233 | ArmCleanInvalidateDataCache (\r | |
| 234 | VOID\r | |
| 235 | );\r | |
| 236 | \r | |
| 237 | VOID\r | |
| 238 | EFIAPI\r | |
| 239 | ArmCleanDataCache (\r | |
| 240 | VOID\r | |
| 241 | );\r | |
| 242 | \r | |
| 243 | VOID\r | |
| 244 | EFIAPI\r | |
| 245 | ArmCleanDataCacheToPoU (\r | |
| 246 | VOID\r | |
| 247 | );\r | |
| 248 | \r | |
| 249 | VOID\r | |
| 250 | EFIAPI\r | |
| 251 | ArmInvalidateInstructionCache (\r | |
| 252 | VOID\r | |
| 253 | );\r | |
| 254 | \r | |
| 255 | VOID\r | |
| 256 | EFIAPI\r | |
| 257 | ArmInvalidateDataCacheEntryByMVA (\r | |
| 258 | IN UINTN Address\r | |
| 259 | );\r | |
| 260 | \r | |
| 261 | VOID\r | |
| 262 | EFIAPI\r | |
| 263 | ArmCleanDataCacheEntryByMVA (\r | |
| 264 | IN UINTN Address\r | |
| 265 | );\r | |
| 266 | \r | |
| 267 | VOID\r | |
| 268 | EFIAPI\r | |
| 269 | ArmCleanInvalidateDataCacheEntryByMVA (\r | |
| 270 | IN UINTN Address\r | |
| 271 | );\r | |
| 272 | \r | |
| 0ff0e414 OM |
273 | VOID\r |
| 274 | EFIAPI\r | |
| 275 | ArmInvalidateDataCacheEntryBySetWay (\r | |
| 276 | IN UINTN SetWayFormat\r | |
| 277 | );\r | |
| 278 | \r | |
| 279 | VOID\r | |
| 280 | EFIAPI\r | |
| 281 | ArmCleanDataCacheEntryBySetWay (\r | |
| 282 | IN UINTN SetWayFormat\r | |
| 283 | );\r | |
| 284 | \r | |
| 285 | VOID\r | |
| 286 | EFIAPI\r | |
| 287 | ArmCleanInvalidateDataCacheEntryBySetWay (\r | |
| 288 | IN UINTN SetWayFormat\r | |
| 289 | );\r | |
| 290 | \r | |
| 1e57a462 | 291 | VOID\r |
| 292 | EFIAPI\r | |
| 293 | ArmEnableDataCache (\r | |
| 294 | VOID\r | |
| 295 | );\r | |
| 296 | \r | |
| 297 | VOID\r | |
| 298 | EFIAPI\r | |
| 299 | ArmDisableDataCache (\r | |
| 300 | VOID\r | |
| 301 | );\r | |
| 302 | \r | |
| 303 | VOID\r | |
| 304 | EFIAPI\r | |
| 305 | ArmEnableInstructionCache (\r | |
| 306 | VOID\r | |
| 307 | );\r | |
| 308 | \r | |
| 309 | VOID\r | |
| 310 | EFIAPI\r | |
| 311 | ArmDisableInstructionCache (\r | |
| 312 | VOID\r | |
| 313 | );\r | |
| 3402aac7 | 314 | \r |
| 1e57a462 | 315 | VOID\r |
| 316 | EFIAPI\r | |
| 317 | ArmEnableMmu (\r | |
| 318 | VOID\r | |
| 319 | );\r | |
| 320 | \r | |
| 321 | VOID\r | |
| 322 | EFIAPI\r | |
| 323 | ArmDisableMmu (\r | |
| 324 | VOID\r | |
| 325 | );\r | |
| 326 | \r | |
| 0ff0e414 OM |
327 | VOID\r |
| 328 | EFIAPI\r | |
| 329 | ArmEnableCachesAndMmu (\r | |
| 330 | VOID\r | |
| 331 | );\r | |
| 332 | \r | |
| 1e57a462 | 333 | VOID\r |
| 334 | EFIAPI\r | |
| 335 | ArmDisableCachesAndMmu (\r | |
| 336 | VOID\r | |
| 337 | );\r | |
| 338 | \r | |
| 1e57a462 | 339 | VOID\r |
| 340 | EFIAPI\r | |
| 341 | ArmEnableInterrupts (\r | |
| 342 | VOID\r | |
| 343 | );\r | |
| 344 | \r | |
| 345 | UINTN\r | |
| 346 | EFIAPI\r | |
| 347 | ArmDisableInterrupts (\r | |
| 348 | VOID\r | |
| 349 | );\r | |
| 47585ed5 | 350 | \r |
| 1e57a462 | 351 | BOOLEAN\r |
| 352 | EFIAPI\r | |
| 353 | ArmGetInterruptState (\r | |
| 354 | VOID\r | |
| 355 | );\r | |
| 356 | \r | |
| 0ff0e414 OM |
357 | VOID\r |
| 358 | EFIAPI\r | |
| 359 | ArmEnableAsynchronousAbort (\r | |
| 360 | VOID\r | |
| 361 | );\r | |
| 362 | \r | |
| 47585ed5 | 363 | UINTN\r |
| 364 | EFIAPI\r | |
| 0ff0e414 | 365 | ArmDisableAsynchronousAbort (\r |
| 47585ed5 | 366 | VOID\r |
| 367 | );\r | |
| 368 | \r | |
| 369 | VOID\r | |
| 370 | EFIAPI\r | |
| 371 | ArmEnableIrq (\r | |
| 372 | VOID\r | |
| 373 | );\r | |
| 374 | \r | |
| 0ff0e414 OM |
375 | UINTN\r |
| 376 | EFIAPI\r | |
| 377 | ArmDisableIrq (\r | |
| 378 | VOID\r | |
| 379 | );\r | |
| 380 | \r | |
| 1e57a462 | 381 | VOID\r |
| 382 | EFIAPI\r | |
| 383 | ArmEnableFiq (\r | |
| 384 | VOID\r | |
| 385 | );\r | |
| 386 | \r | |
| 387 | UINTN\r | |
| 388 | EFIAPI\r | |
| 389 | ArmDisableFiq (\r | |
| 390 | VOID\r | |
| 391 | );\r | |
| 3402aac7 | 392 | \r |
| 1e57a462 | 393 | BOOLEAN\r |
| 394 | EFIAPI\r | |
| 395 | ArmGetFiqState (\r | |
| 396 | VOID\r | |
| 397 | );\r | |
| 398 | \r | |
| 8dd618d2 OM |
399 | /**\r |
| 400 | * Invalidate Data and Instruction TLBs\r | |
| 401 | */\r | |
| 1e57a462 | 402 | VOID\r |
| 403 | EFIAPI\r | |
| 404 | ArmInvalidateTlb (\r | |
| 405 | VOID\r | |
| 406 | );\r | |
| 3402aac7 | 407 | \r |
| 1e57a462 | 408 | VOID\r |
| 409 | EFIAPI\r | |
| 410 | ArmUpdateTranslationTableEntry (\r | |
| 411 | IN VOID *TranslationTableEntry,\r | |
| 412 | IN VOID *Mva\r | |
| 413 | );\r | |
| 3402aac7 | 414 | \r |
| 1e57a462 | 415 | VOID\r |
| 416 | EFIAPI\r | |
| 417 | ArmSetDomainAccessControl (\r | |
| 418 | IN UINT32 Domain\r | |
| 419 | );\r | |
| 420 | \r | |
| 421 | VOID\r | |
| 422 | EFIAPI\r | |
| 423 | ArmSetTTBR0 (\r | |
| 424 | IN VOID *TranslationTableBase\r | |
| 425 | );\r | |
| 426 | \r | |
| 427 | VOID *\r | |
| 428 | EFIAPI\r | |
| 429 | ArmGetTTBR0BaseAddress (\r | |
| 430 | VOID\r | |
| 431 | );\r | |
| 432 | \r | |
| 6f050ad6 | 433 | RETURN_STATUS\r |
| 1e57a462 | 434 | EFIAPI\r |
| 435 | ArmConfigureMmu (\r | |
| 436 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r | |
| 6f050ad6 | 437 | OUT VOID **TranslationTableBase OPTIONAL,\r |
| 1e57a462 | 438 | OUT UINTN *TranslationTableSize OPTIONAL\r |
| 439 | );\r | |
| 3402aac7 | 440 | \r |
| 1e57a462 | 441 | BOOLEAN\r |
| 442 | EFIAPI\r | |
| 443 | ArmMmuEnabled (\r | |
| 444 | VOID\r | |
| 445 | );\r | |
| 3402aac7 | 446 | \r |
| 1e57a462 | 447 | VOID\r |
| 448 | EFIAPI\r | |
| 449 | ArmEnableBranchPrediction (\r | |
| 450 | VOID\r | |
| 451 | );\r | |
| 452 | \r | |
| 453 | VOID\r | |
| 454 | EFIAPI\r | |
| 455 | ArmDisableBranchPrediction (\r | |
| 456 | VOID\r | |
| 457 | );\r | |
| 458 | \r | |
| 459 | VOID\r | |
| 460 | EFIAPI\r | |
| 461 | ArmSetLowVectors (\r | |
| 462 | VOID\r | |
| 463 | );\r | |
| 464 | \r | |
| 465 | VOID\r | |
| 466 | EFIAPI\r | |
| 467 | ArmSetHighVectors (\r | |
| 468 | VOID\r | |
| 469 | );\r | |
| 470 | \r | |
| 0ff0e414 OM |
471 | VOID\r |
| 472 | EFIAPI\r | |
| 473 | ArmDrainWriteBuffer (\r | |
| 474 | VOID\r | |
| 475 | );\r | |
| 476 | \r | |
| 1e57a462 | 477 | VOID\r |
| 478 | EFIAPI\r | |
| 479 | ArmDataMemoryBarrier (\r | |
| 480 | VOID\r | |
| 481 | );\r | |
| 3402aac7 | 482 | \r |
| 1e57a462 | 483 | VOID\r |
| 484 | EFIAPI\r | |
| 485 | ArmDataSyncronizationBarrier (\r | |
| 486 | VOID\r | |
| 487 | );\r | |
| 3402aac7 | 488 | \r |
| 1e57a462 | 489 | VOID\r |
| 490 | EFIAPI\r | |
| 491 | ArmInstructionSynchronizationBarrier (\r | |
| 492 | VOID\r | |
| 493 | );\r | |
| 494 | \r | |
| 495 | VOID\r | |
| 496 | EFIAPI\r | |
| 497 | ArmWriteVBar (\r | |
| 4e57d6d7 | 498 | IN UINTN VectorBase\r |
| 1e57a462 | 499 | );\r |
| 500 | \r | |
| 4e57d6d7 | 501 | UINTN\r |
| 1e57a462 | 502 | EFIAPI\r |
| 503 | ArmReadVBar (\r | |
| 504 | VOID\r | |
| 505 | );\r | |
| 506 | \r | |
| 507 | VOID\r | |
| 508 | EFIAPI\r | |
| 509 | ArmWriteAuxCr (\r | |
| 510 | IN UINT32 Bit\r | |
| 511 | );\r | |
| 512 | \r | |
| 513 | UINT32\r | |
| 514 | EFIAPI\r | |
| 515 | ArmReadAuxCr (\r | |
| 516 | VOID\r | |
| 517 | );\r | |
| 518 | \r | |
| 519 | VOID\r | |
| 520 | EFIAPI\r | |
| 521 | ArmSetAuxCrBit (\r | |
| 522 | IN UINT32 Bits\r | |
| 523 | );\r | |
| 524 | \r | |
| 525 | VOID\r | |
| 526 | EFIAPI\r | |
| 527 | ArmUnsetAuxCrBit (\r | |
| 528 | IN UINT32 Bits\r | |
| 529 | );\r | |
| 530 | \r | |
| 531 | VOID\r | |
| 532 | EFIAPI\r | |
| 533 | ArmCallSEV (\r | |
| 534 | VOID\r | |
| 535 | );\r | |
| 536 | \r | |
| 537 | VOID\r | |
| 538 | EFIAPI\r | |
| 539 | ArmCallWFE (\r | |
| 540 | VOID\r | |
| 541 | );\r | |
| 542 | \r | |
| 543 | VOID\r | |
| 544 | EFIAPI\r | |
| 545 | ArmCallWFI (\r | |
| 25402f5d | 546 | \r |
| 1e57a462 | 547 | VOID\r |
| 548 | );\r | |
| 549 | \r | |
| 550 | UINTN\r | |
| 551 | EFIAPI\r | |
| 552 | ArmReadMpidr (\r | |
| 553 | VOID\r | |
| 554 | );\r | |
| 555 | \r | |
| 9401d6f4 OM |
556 | UINTN\r |
| 557 | EFIAPI\r | |
| 558 | ArmReadMidr (\r | |
| 559 | VOID\r | |
| 560 | );\r | |
| 561 | \r | |
| 1e57a462 | 562 | UINT32\r |
| 563 | EFIAPI\r | |
| 564 | ArmReadCpacr (\r | |
| 565 | VOID\r | |
| 566 | );\r | |
| 567 | \r | |
| 568 | VOID\r | |
| 569 | EFIAPI\r | |
| 570 | ArmWriteCpacr (\r | |
| 571 | IN UINT32 Access\r | |
| 572 | );\r | |
| 573 | \r | |
| 574 | VOID\r | |
| 575 | EFIAPI\r | |
| 576 | ArmEnableVFP (\r | |
| 577 | VOID\r | |
| 578 | );\r | |
| 579 | \r | |
| 46d4d75c OM |
580 | /**\r |
| 581 | Get the Secure Configuration Register value\r | |
| 582 | \r | |
| 583 | @return Value read from the Secure Configuration Register\r | |
| 584 | \r | |
| 585 | **/\r | |
| 1e57a462 | 586 | UINT32\r |
| 587 | EFIAPI\r | |
| 588 | ArmReadScr (\r | |
| 589 | VOID\r | |
| 590 | );\r | |
| 591 | \r | |
| 46d4d75c OM |
592 | /**\r |
| 593 | Set the Secure Configuration Register\r | |
| 594 | \r | |
| 595 | @param Value Value to write to the Secure Configuration Register\r | |
| 596 | \r | |
| 597 | **/\r | |
| 1e57a462 | 598 | VOID\r |
| 599 | EFIAPI\r | |
| 600 | ArmWriteScr (\r | |
| 46d4d75c | 601 | IN UINT32 Value\r |
| 1e57a462 | 602 | );\r |
| 603 | \r | |
| 604 | UINT32\r | |
| 605 | EFIAPI\r | |
| 606 | ArmReadMVBar (\r | |
| 607 | VOID\r | |
| 608 | );\r | |
| 609 | \r | |
| 610 | VOID\r | |
| 611 | EFIAPI\r | |
| 612 | ArmWriteMVBar (\r | |
| 613 | IN UINT32 VectorMonitorBase\r | |
| 614 | );\r | |
| 615 | \r | |
| 616 | UINT32\r | |
| 617 | EFIAPI\r | |
| 618 | ArmReadSctlr (\r | |
| 619 | VOID\r | |
| 620 | );\r | |
| 621 | \r | |
| 5ea2c2d3 | 622 | UINTN\r |
| 623 | EFIAPI\r | |
| 624 | ArmReadHVBar (\r | |
| 625 | VOID\r | |
| 626 | );\r | |
| 627 | \r | |
| 628 | VOID\r | |
| 629 | EFIAPI\r | |
| 630 | ArmWriteHVBar (\r | |
| 631 | IN UINTN HypModeVectorBase\r | |
| 632 | );\r | |
| 633 | \r | |
| 52d44f77 OM |
634 | \r |
| 635 | //\r | |
| 636 | // Helper functions for accessing CPU ACTLR\r | |
| 637 | //\r | |
| 638 | \r | |
| 639 | UINTN\r | |
| 640 | EFIAPI\r | |
| 641 | ArmReadCpuActlr (\r | |
| 642 | VOID\r | |
| 643 | );\r | |
| 644 | \r | |
| 645 | VOID\r | |
| 646 | EFIAPI\r | |
| 647 | ArmWriteCpuActlr (\r | |
| 648 | IN UINTN Val\r | |
| 649 | );\r | |
| 650 | \r | |
| 651 | VOID\r | |
| 652 | EFIAPI\r | |
| 653 | ArmSetCpuActlrBit (\r | |
| 654 | IN UINTN Bits\r | |
| 655 | );\r | |
| 656 | \r | |
| 657 | VOID\r | |
| 658 | EFIAPI\r | |
| 659 | ArmUnsetCpuActlrBit (\r | |
| 660 | IN UINTN Bits\r | |
| 661 | );\r | |
| 662 | \r | |
| 1e57a462 | 663 | #endif // __ARM_LIB__\r |