3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
5 Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
14 #include <Uefi/UefiBaseType.h>
17 #include <Chipset/ArmV7.h>
18 #elif defined(MDE_CPU_AARCH64)
19 #include <Chipset/AArch64.h>
21 #error "Unknown chipset."
24 #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
25 EFI_MEMORY_WT | EFI_MEMORY_WB | \
29 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
31 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
32 * be used in Secure World to distinguished Secure to Non-Secure memory.
35 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
36 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
37 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
38 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
40 // On some platforms, memory mapped flash region is designed as not supporting
41 // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
43 // Do NOT use below two attributes if you are not sure.
44 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE
,
45 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE
,
47 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
48 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
49 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
50 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
51 } ARM_MEMORY_REGION_ATTRIBUTES
;
53 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
56 EFI_PHYSICAL_ADDRESS PhysicalBase
;
57 EFI_VIRTUAL_ADDRESS VirtualBase
;
59 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
60 } ARM_MEMORY_REGION_DESCRIPTOR
;
62 typedef VOID (*CACHE_OPERATION
)(VOID
);
63 typedef VOID (*LINE_OPERATION
)(UINTN
);
69 ARM_PROCESSOR_MODE_USER
= 0x10,
70 ARM_PROCESSOR_MODE_FIQ
= 0x11,
71 ARM_PROCESSOR_MODE_IRQ
= 0x12,
72 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
73 ARM_PROCESSOR_MODE_ABORT
= 0x17,
74 ARM_PROCESSOR_MODE_HYP
= 0x1A,
75 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
76 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
77 ARM_PROCESSOR_MODE_MASK
= 0x1F
83 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
84 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
85 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
86 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
87 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
88 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
90 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
91 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
92 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
93 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
94 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
95 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
100 #define ARM_CORE_AFF0 0xFF
101 #define ARM_CORE_AFF1 (0xFF << 8)
102 #define ARM_CORE_AFF2 (0xFF << 16)
103 #define ARM_CORE_AFF3 (0xFFULL << 32)
105 #define ARM_CORE_MASK ARM_CORE_AFF0
106 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
107 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
108 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
109 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
110 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
112 // The ARM Architecture Reference Manual for ARMv8-A defines up
113 // to 7 levels of cache, L1 through L7.
114 #define MAX_ARM_CACHE_LEVEL 7
118 ArmDataCacheLineLength (
124 ArmInstructionCacheLineLength (
130 ArmCacheWritebackGranule (
136 ArmIsArchTimerImplemented (
154 ArmInvalidateDataCache (
161 ArmCleanInvalidateDataCache (
173 ArmInvalidateInstructionCache (
179 ArmInvalidateDataCacheEntryByMVA (
185 ArmCleanDataCacheEntryToPoUByMVA (
191 ArmInvalidateInstructionCacheEntryToPoUByMVA (
197 ArmCleanDataCacheEntryByMVA (
203 ArmCleanInvalidateDataCacheEntryByMVA (
215 ArmDisableDataCache (
221 ArmEnableInstructionCache (
227 ArmDisableInstructionCache (
245 ArmEnableCachesAndMmu (
251 ArmDisableCachesAndMmu (
257 ArmEnableInterrupts (
263 ArmDisableInterrupts (
269 ArmGetInterruptState (
275 ArmEnableAsynchronousAbort (
281 ArmDisableAsynchronousAbort (
316 * Invalidate Data and Instruction TLBs
326 ArmUpdateTranslationTableEntry (
327 IN VOID
*TranslationTableEntry
,
333 ArmSetDomainAccessControl (
340 IN VOID
*TranslationTableBase
351 ArmGetTTBR0BaseAddress (
363 ArmEnableBranchPrediction (
369 ArmDisableBranchPrediction (
387 ArmDataMemoryBarrier (
393 ArmDataSynchronizationBarrier (
399 ArmInstructionSynchronizationBarrier (
489 Get the Secure Configuration Register value
491 @return Value read from the Secure Configuration Register
501 Set the Secure Configuration Register
503 @param Value Value to write to the Secure Configuration Register
521 IN UINT32 VectorMonitorBase
545 IN UINTN HypModeVectorBase
550 // Helper functions for accessing CPU ACTLR
573 ArmUnsetCpuActlrBit (
578 // Accessors for the architected generic timer registers
581 #define ARM_ARCH_TIMER_ENABLE (1 << 0)
582 #define ARM_ARCH_TIMER_IMASK (1 << 1)
583 #define ARM_ARCH_TIMER_ISTATUS (1 << 2)
707 ArmGetPhysicalAddressBits (
713 /// ID Register Helper functions
717 Check whether the CPU supports the GIC system register interface (any version)
719 @return Whether GIC System Register Interface is supported
724 ArmHasGicSystemRegisters (
730 /// AArch32-only ID Register Helper functions
733 Check whether the CPU supports the Security extensions
735 @return Whether the Security extensions are implemented
740 ArmHasSecurityExtensions (
743 #endif // MDE_CPU_ARM
745 #endif // __ARM_LIB__