ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef ARM_CPU_ARMv6
  22 #include <Chipset/ARM1176JZ-S.h>
  23 #else
  24 #include <Chipset/ArmV7.h>
  25 #endif
  26
  27 typedef enum {
  28   ARM_CACHE_TYPE_WRITE_BACK,
  29   ARM_CACHE_TYPE_UNKNOWN
  30 } ARM_CACHE_TYPE;
  31
  32 typedef enum {
  33   ARM_CACHE_ARCHITECTURE_UNIFIED,
  34   ARM_CACHE_ARCHITECTURE_SEPARATE,
  35   ARM_CACHE_ARCHITECTURE_UNKNOWN
  36 } ARM_CACHE_ARCHITECTURE;
  37
  38 typedef struct {
  39   ARM_CACHE_TYPE          Type;
  40   ARM_CACHE_ARCHITECTURE  Architecture;
  41   BOOLEAN                 DataCachePresent;
  42   UINTN                   DataCacheSize;
  43   UINTN                   DataCacheAssociativity;
  44   UINTN                   DataCacheLineLength;
  45   BOOLEAN                 InstructionCachePresent;
  46   UINTN                   InstructionCacheSize;
  47   UINTN                   InstructionCacheAssociativity;
  48   UINTN                   InstructionCacheLineLength;
  49 } ARM_CACHE_INFO;
  50
  51 /**
  52  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  53  *
  54  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  55  * be used in Secure World to distinguished Secure to Non-Secure memory.
  56  */
  57 typedef enum {
  58   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  59   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  60   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  61   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  62   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  63   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  64   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  65   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  66 } ARM_MEMORY_REGION_ATTRIBUTES;
  67
  68 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  69
  70 typedef struct {
  71   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  72   EFI_VIRTUAL_ADDRESS           VirtualBase;
  73   UINTN                         Length;
  74   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  75 } ARM_MEMORY_REGION_DESCRIPTOR;
  76
  77 typedef VOID (*CACHE_OPERATION)(VOID);
  78 typedef VOID (*LINE_OPERATION)(UINTN);
  79
  80 typedef enum {
  81   ARM_PROCESSOR_MODE_USER       = 0x10,
  82   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  83   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  84   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  85   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  86   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  87   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  88   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  89   ARM_PROCESSOR_MODE_MASK       = 0x1F
  90 } ARM_PROCESSOR_MODE;
  91
  92 #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
  93 #define GET_CORE_ID(MpId)     ((MpId) & 0xFF)
  94 #define GET_CLUSTER_ID(MpId)  (((MpId) >> 8) & 0xFF)
  95 // Get the position of the core for the Stack Offset (4 Core per Cluster)
  96 //   Position = (ClusterId * 4) + CoreId
  97 #define GET_CORE_POS(MpId)    ((((MpId) >> 6) & 0xFF) + ((MpId) & 0xFF))
  98 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & 0xFF)
  99
 100 ARM_CACHE_TYPE
 101 EFIAPI
 102 ArmCacheType (
 103   VOID
 104   );
 105
 106 ARM_CACHE_ARCHITECTURE
 107 EFIAPI
 108 ArmCacheArchitecture (
 109   VOID
 110   );
 111
 112 VOID
 113 EFIAPI
 114 ArmCacheInformation (
 115   OUT ARM_CACHE_INFO  *CacheInfo
 116   );
 117
 118 BOOLEAN
 119 EFIAPI
 120 ArmDataCachePresent (
 121   VOID
 122   );
 123
 124 UINTN
 125 EFIAPI
 126 ArmDataCacheSize (
 127   VOID
 128   );
 129
 130 UINTN
 131 EFIAPI
 132 ArmDataCacheAssociativity (
 133   VOID
 134   );
 135
 136 UINTN
 137 EFIAPI
 138 ArmDataCacheLineLength (
 139   VOID
 140   );
 141
 142 BOOLEAN
 143 EFIAPI
 144 ArmInstructionCachePresent (
 145   VOID
 146   );
 147
 148 UINTN
 149 EFIAPI
 150 ArmInstructionCacheSize (
 151   VOID
 152   );
 153
 154 UINTN
 155 EFIAPI
 156 ArmInstructionCacheAssociativity (
 157   VOID
 158   );
 159
 160 UINTN
 161 EFIAPI
 162 ArmInstructionCacheLineLength (
 163   VOID
 164   );
 165
 166 UINT32
 167 EFIAPI
 168 Cp15IdCode (
 169   VOID
 170   );
 171
 172 UINT32
 173 EFIAPI
 174 Cp15CacheInfo (
 175   VOID
 176   );
 177
 178 BOOLEAN
 179 EFIAPI
 180 ArmIsMpCore (
 181   VOID
 182   );
 183
 184 VOID
 185 EFIAPI
 186 ArmInvalidateDataCache (
 187   VOID
 188   );
 189
 190
 191 VOID
 192 EFIAPI
 193 ArmCleanInvalidateDataCache (
 194   VOID
 195   );
 196
 197 VOID
 198 EFIAPI
 199 ArmCleanDataCache (
 200   VOID
 201   );
 202
 203 VOID
 204 EFIAPI
 205 ArmCleanDataCacheToPoU (
 206   VOID
 207   );
 208
 209 VOID
 210 EFIAPI
 211 ArmInvalidateInstructionCache (
 212   VOID
 213   );
 214
 215 VOID
 216 EFIAPI
 217 ArmInvalidateDataCacheEntryByMVA (
 218   IN  UINTN   Address
 219   );
 220
 221 VOID
 222 EFIAPI
 223 ArmCleanDataCacheEntryByMVA (
 224   IN  UINTN   Address
 225   );
 226
 227 VOID
 228 EFIAPI
 229 ArmCleanInvalidateDataCacheEntryByMVA (
 230   IN  UINTN   Address
 231   );
 232
 233 VOID
 234 EFIAPI
 235 ArmEnableDataCache (
 236   VOID
 237   );
 238
 239 VOID
 240 EFIAPI
 241 ArmDisableDataCache (
 242   VOID
 243   );
 244
 245 VOID
 246 EFIAPI
 247 ArmEnableInstructionCache (
 248   VOID
 249   );
 250
 251 VOID
 252 EFIAPI
 253 ArmDisableInstructionCache (
 254   VOID
 255   );
 256
 257 VOID
 258 EFIAPI
 259 ArmEnableMmu (
 260   VOID
 261   );
 262
 263 VOID
 264 EFIAPI
 265 ArmDisableMmu (
 266   VOID
 267   );
 268
 269 VOID
 270 EFIAPI
 271 ArmDisableCachesAndMmu (
 272   VOID
 273   );
 274
 275 VOID
 276 EFIAPI
 277 ArmInvalidateInstructionAndDataTlb (
 278   VOID
 279   );
 280
 281 VOID
 282 EFIAPI
 283 ArmEnableInterrupts (
 284   VOID
 285   );
 286
 287 UINTN
 288 EFIAPI
 289 ArmDisableInterrupts (
 290   VOID
 291   );
 292
 293 BOOLEAN
 294 EFIAPI
 295 ArmGetInterruptState (
 296   VOID
 297   );
 298
 299 VOID
 300 EFIAPI
 301 ArmEnableFiq (
 302   VOID
 303   );
 304
 305 UINTN
 306 EFIAPI
 307 ArmDisableFiq (
 308   VOID
 309   );
 310
 311 BOOLEAN
 312 EFIAPI
 313 ArmGetFiqState (
 314   VOID
 315   );
 316
 317 VOID
 318 EFIAPI
 319 ArmInvalidateTlb (
 320   VOID
 321   );
 322
 323 VOID
 324 EFIAPI
 325 ArmUpdateTranslationTableEntry (
 326   IN  VOID     *TranslationTableEntry,
 327   IN  VOID     *Mva
 328   );
 329
 330 VOID
 331 EFIAPI
 332 ArmSetDomainAccessControl (
 333   IN  UINT32  Domain
 334   );
 335
 336 VOID
 337 EFIAPI
 338 ArmSetTTBR0 (
 339   IN  VOID  *TranslationTableBase
 340   );
 341
 342 VOID *
 343 EFIAPI
 344 ArmGetTTBR0BaseAddress (
 345   VOID
 346   );
 347
 348 VOID
 349 EFIAPI
 350 ArmConfigureMmu (
 351   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 352   OUT VOID                          **TranslationTableBase OPTIONAL,
 353   OUT UINTN                         *TranslationTableSize  OPTIONAL
 354   );
 355
 356 BOOLEAN
 357 EFIAPI
 358 ArmMmuEnabled (
 359   VOID
 360   );
 361
 362 VOID
 363 EFIAPI
 364 ArmSwitchProcessorMode (
 365   IN ARM_PROCESSOR_MODE Mode
 366   );
 367
 368 ARM_PROCESSOR_MODE
 369 EFIAPI
 370 ArmProcessorMode (
 371   VOID
 372   );
 373
 374 VOID
 375 EFIAPI
 376 ArmEnableBranchPrediction (
 377   VOID
 378   );
 379
 380 VOID
 381 EFIAPI
 382 ArmDisableBranchPrediction (
 383   VOID
 384   );
 385
 386 VOID
 387 EFIAPI
 388 ArmSetLowVectors (
 389   VOID
 390   );
 391
 392 VOID
 393 EFIAPI
 394 ArmSetHighVectors (
 395   VOID
 396   );
 397
 398 VOID
 399 EFIAPI
 400 ArmDataMemoryBarrier (
 401   VOID
 402   );
 403
 404 VOID
 405 EFIAPI
 406 ArmDataSyncronizationBarrier (
 407   VOID
 408   );
 409
 410 VOID
 411 EFIAPI
 412 ArmInstructionSynchronizationBarrier (
 413   VOID
 414   );
 415
 416 VOID
 417 EFIAPI
 418 ArmWriteVBar (
 419   IN  UINT32   VectorBase
 420   );
 421
 422 UINT32
 423 EFIAPI
 424 ArmReadVBar (
 425   VOID
 426   );
 427
 428 VOID
 429 EFIAPI
 430 ArmWriteAuxCr (
 431   IN  UINT32    Bit
 432   );
 433
 434 UINT32
 435 EFIAPI
 436 ArmReadAuxCr (
 437   VOID
 438   );
 439
 440 VOID
 441 EFIAPI
 442 ArmSetAuxCrBit (
 443   IN  UINT32    Bits
 444   );
 445
 446 VOID
 447 EFIAPI
 448 ArmUnsetAuxCrBit (
 449   IN  UINT32    Bits
 450   );
 451
 452 VOID
 453 EFIAPI
 454 ArmCallSEV (
 455   VOID
 456   );
 457
 458 VOID
 459 EFIAPI
 460 ArmCallWFE (
 461   VOID
 462   );
 463
 464 VOID
 465 EFIAPI
 466 ArmCallWFI (
 467   VOID
 468   );
 469
 470 UINTN
 471 EFIAPI
 472 ArmReadMpidr (
 473   VOID
 474   );
 475
 476 UINT32
 477 EFIAPI
 478 ArmReadCpacr (
 479   VOID
 480   );
 481
 482 VOID
 483 EFIAPI
 484 ArmWriteCpacr (
 485   IN  UINT32   Access
 486   );
 487
 488 VOID
 489 EFIAPI
 490 ArmEnableVFP (
 491   VOID
 492   );
 493
 494 UINT32
 495 EFIAPI
 496 ArmReadNsacr (
 497   VOID
 498   );
 499
 500 VOID
 501 EFIAPI
 502 ArmWriteNsacr (
 503   IN  UINT32   SetWayFormat
 504   );
 505
 506 UINT32
 507 EFIAPI
 508 ArmReadScr (
 509   VOID
 510   );
 511
 512 VOID
 513 EFIAPI
 514 ArmWriteScr (
 515   IN  UINT32   SetWayFormat
 516   );
 517
 518 UINT32
 519 EFIAPI
 520 ArmReadMVBar (
 521   VOID
 522   );
 523
 524 VOID
 525 EFIAPI
 526 ArmWriteMVBar (
 527   IN  UINT32   VectorMonitorBase
 528   );
 529
 530 UINT32
 531 EFIAPI
 532 ArmReadSctlr (
 533   VOID
 534   );
 535
 536 #endif // __ARM_LIB__