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ArmPkg/Mmu: do not configure block translations at level 0
[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Mmu.c
1 /** @file
2 * File managing the MMU for ARMv8 architecture
3 *
4 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include <Uefi.h>
17 #include <Chipset/AArch64.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <Library/ArmLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/DebugLib.h>
23 #include "AArch64Lib.h"
24 #include "ArmLibPrivate.h"
25
26 // We use this index definition to define an invalid block entry
27 #define TT_ATTR_INDX_INVALID ((UINT32)~0)
28
29 STATIC
30 UINT64
31 ArmMemoryAttributeToPageAttribute (
32 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
33 )
34 {
35 switch (Attributes) {
36 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
37 return TT_ATTR_INDX_MEMORY_WRITE_BACK;
38 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
39 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
40 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
41 return TT_ATTR_INDX_DEVICE_MEMORY;
42 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
43 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
44 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
45 return TT_ATTR_INDX_MEMORY_WRITE_BACK;
46 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
47 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
48 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
49 return TT_ATTR_INDX_DEVICE_MEMORY;
50 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
51 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
52 default:
53 ASSERT(0);
54 return TT_ATTR_INDX_DEVICE_MEMORY;
55 }
56 }
57
58 UINT64
59 PageAttributeToGcdAttribute (
60 IN UINT64 PageAttributes
61 )
62 {
63 UINT64 GcdAttributes;
64
65 switch (PageAttributes & TT_ATTR_INDX_MASK) {
66 case TT_ATTR_INDX_DEVICE_MEMORY:
67 GcdAttributes = EFI_MEMORY_UC;
68 break;
69 case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
70 GcdAttributes = EFI_MEMORY_WC;
71 break;
72 case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
73 GcdAttributes = EFI_MEMORY_WT;
74 break;
75 case TT_ATTR_INDX_MEMORY_WRITE_BACK:
76 GcdAttributes = EFI_MEMORY_WB;
77 break;
78 default:
79 DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));
80 ASSERT (0);
81 // The Global Coherency Domain (GCD) value is defined as a bit set.
82 // Returning 0 means no attribute has been set.
83 GcdAttributes = 0;
84 }
85
86 // Determine protection attributes
87 if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
88 // Read only cases map to write-protect
89 GcdAttributes |= EFI_MEMORY_WP;
90 }
91
92 // Process eXecute Never attribute
93 if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {
94 GcdAttributes |= EFI_MEMORY_XP;
95 }
96
97 return GcdAttributes;
98 }
99
100 UINT64
101 GcdAttributeToPageAttribute (
102 IN UINT64 GcdAttributes
103 )
104 {
105 UINT64 PageAttributes;
106
107 switch (GcdAttributes & 0xFF) {
108 case EFI_MEMORY_UC:
109 PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
110 break;
111 case EFI_MEMORY_WC:
112 PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
113 break;
114 case EFI_MEMORY_WT:
115 PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
116 break;
117 case EFI_MEMORY_WB:
118 PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;
119 break;
120 default:
121 DEBUG ((EFI_D_ERROR, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes));
122 ASSERT (0);
123 // If no match has been found then we mark the memory as device memory.
124 // The only side effect of using device memory should be a slow down in the performance.
125 PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
126 }
127
128 // Determine protection attributes
129 if (GcdAttributes & EFI_MEMORY_WP) {
130 // Read only cases map to write-protect
131 PageAttributes |= TT_AP_RO_RO;
132 }
133
134 // Process eXecute Never attribute
135 if (GcdAttributes & EFI_MEMORY_XP) {
136 PageAttributes |= (TT_PXN_MASK | TT_UXN_MASK);
137 }
138
139 return PageAttributes;
140 }
141
142 ARM_MEMORY_REGION_ATTRIBUTES
143 GcdAttributeToArmAttribute (
144 IN UINT64 GcdAttributes
145 )
146 {
147 switch (GcdAttributes & 0xFF) {
148 case EFI_MEMORY_UC:
149 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
150 case EFI_MEMORY_WC:
151 return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
152 case EFI_MEMORY_WT:
153 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
154 case EFI_MEMORY_WB:
155 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
156 default:
157 DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));
158 ASSERT (0);
159 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
160 }
161 }
162
163 // Describe the T0SZ values for each translation table level
164 typedef struct {
165 UINTN MinT0SZ;
166 UINTN MaxT0SZ;
167 UINTN LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
168 // the MaxT0SZ is not at the boundary of the table
169 } T0SZ_DESCRIPTION_PER_LEVEL;
170
171 // Map table for the corresponding Level of Table
172 STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {
173 { 16, 24, 24 }, // Table Level 0
174 { 25, 33, 33 }, // Table Level 1
175 { 34, 39, 42 } // Table Level 2
176 };
177
178 VOID
179 GetRootTranslationTableInfo (
180 IN UINTN T0SZ,
181 OUT UINTN *TableLevel,
182 OUT UINTN *TableEntryCount
183 )
184 {
185 UINTN Index;
186
187 // Identify the level of the root table from the given T0SZ
188 for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {
189 if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {
190 break;
191 }
192 }
193
194 // If we have not found the corresponding maximum T0SZ then we use the last one
195 if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {
196 Index--;
197 }
198
199 // Get the level of the root table
200 if (TableLevel) {
201 *TableLevel = Index;
202 }
203
204 // The Size of the Table is 2^(T0SZ-LargestT0SZ)
205 if (TableEntryCount) {
206 *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);
207 }
208 }
209
210 STATIC
211 VOID
212 LookupAddresstoRootTable (
213 IN UINT64 MaxAddress,
214 OUT UINTN *T0SZ,
215 OUT UINTN *TableEntryCount
216 )
217 {
218 UINTN TopBit;
219
220 // Check the parameters are not NULL
221 ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));
222
223 // Look for the highest bit set in MaxAddress
224 for (TopBit = 63; TopBit != 0; TopBit--) {
225 if ((1ULL << TopBit) & MaxAddress) {
226 // MaxAddress top bit is found
227 TopBit = TopBit + 1;
228 break;
229 }
230 }
231 ASSERT (TopBit != 0);
232
233 // Calculate T0SZ from the top bit of the MaxAddress
234 *T0SZ = 64 - TopBit;
235
236 // Get the Table info from T0SZ
237 GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);
238 }
239
240 STATIC
241 UINT64*
242 GetBlockEntryListFromAddress (
243 IN UINT64 *RootTable,
244 IN UINT64 RegionStart,
245 OUT UINTN *TableLevel,
246 IN OUT UINT64 *BlockEntrySize,
247 OUT UINT64 **LastBlockEntry
248 )
249 {
250 UINTN RootTableLevel;
251 UINTN RootTableEntryCount;
252 UINT64 *TranslationTable;
253 UINT64 *BlockEntry;
254 UINT64 *SubTableBlockEntry;
255 UINT64 BlockEntryAddress;
256 UINTN BaseAddressAlignment;
257 UINTN PageLevel;
258 UINTN Index;
259 UINTN IndexLevel;
260 UINTN T0SZ;
261 UINT64 Attributes;
262 UINT64 TableAttributes;
263
264 // Initialize variable
265 BlockEntry = NULL;
266
267 // Ensure the parameters are valid
268 if (!(TableLevel && BlockEntrySize && LastBlockEntry)) {
269 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
270 return NULL;
271 }
272
273 // Ensure the Region is aligned on 4KB boundary
274 if ((RegionStart & (SIZE_4KB - 1)) != 0) {
275 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
276 return NULL;
277 }
278
279 // Ensure the required size is aligned on 4KB boundary and not 0
280 if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0 || *BlockEntrySize == 0) {
281 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
282 return NULL;
283 }
284
285 T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
286 // Get the Table info from T0SZ
287 GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);
288
289 // If the start address is 0x0 then we use the size of the region to identify the alignment
290 if (RegionStart == 0) {
291 // Identify the highest possible alignment for the Region Size
292 BaseAddressAlignment = LowBitSet64 (*BlockEntrySize);
293 } else {
294 // Identify the highest possible alignment for the Base Address
295 BaseAddressAlignment = LowBitSet64 (RegionStart);
296 }
297
298 // Identify the Page Level the RegionStart must belong to. Note that PageLevel
299 // should be at least 1 since block translations are not supported at level 0
300 PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1);
301
302 // If the required size is smaller than the current block size then we need to go to the page below.
303 // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment
304 // of the allocation size
305 while (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) {
306 // It does not fit so we need to go a page level above
307 PageLevel++;
308 }
309
310 //
311 // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
312 //
313
314 TranslationTable = RootTable;
315 for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {
316 BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);
317
318 if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
319 // Go to the next table
320 TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
321
322 // If we are at the last level then update the last level to next level
323 if (IndexLevel == PageLevel) {
324 // Enter the next level
325 PageLevel++;
326 }
327 } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {
328 // If we are not at the last level then we need to split this BlockEntry
329 if (IndexLevel != PageLevel) {
330 // Retrieve the attributes from the block entry
331 Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;
332
333 // Convert the block entry attributes into Table descriptor attributes
334 TableAttributes = TT_TABLE_AP_NO_PERMISSION;
335 if (Attributes & TT_PXN_MASK) {
336 TableAttributes = TT_TABLE_PXN;
337 }
338 if (Attributes & TT_UXN_MASK) {
339 TableAttributes = TT_TABLE_XN;
340 }
341 if (Attributes & TT_NS) {
342 TableAttributes = TT_TABLE_NS;
343 }
344
345 // Get the address corresponding at this entry
346 BlockEntryAddress = RegionStart;
347 BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
348 // Shift back to right to set zero before the effective address
349 BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
350
351 // Set the correct entry type for the next page level
352 if ((IndexLevel + 1) == 3) {
353 Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;
354 } else {
355 Attributes |= TT_TYPE_BLOCK_ENTRY;
356 }
357
358 // Create a new translation table
359 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
360 if (TranslationTable == NULL) {
361 return NULL;
362 }
363
364 // Populate the newly created lower level table
365 SubTableBlockEntry = TranslationTable;
366 for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
367 *SubTableBlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));
368 SubTableBlockEntry++;
369 }
370
371 // Fill the BlockEntry with the new TranslationTable
372 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY;
373 }
374 } else {
375 if (IndexLevel != PageLevel) {
376 //
377 // Case when we have an Invalid Entry and we are at a page level above of the one targetted.
378 //
379
380 // Create a new translation table
381 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
382 if (TranslationTable == NULL) {
383 return NULL;
384 }
385
386 ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));
387
388 // Fill the new BlockEntry with the TranslationTable
389 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;
390 }
391 }
392 }
393
394 // Expose the found PageLevel to the caller
395 *TableLevel = PageLevel;
396
397 // Now, we have the Table Level we can get the Block Size associated to this table
398 *BlockEntrySize = TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel);
399
400 // The last block of the root table depends on the number of entry in this table,
401 // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table.
402 *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable,
403 (PageLevel == RootTableLevel) ? RootTableEntryCount : TT_ENTRY_COUNT);
404
405 return BlockEntry;
406 }
407
408 STATIC
409 RETURN_STATUS
410 FillTranslationTable (
411 IN UINT64 *RootTable,
412 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
413 )
414 {
415 UINT64 Attributes;
416 UINT32 Type;
417 UINT64 RegionStart;
418 UINT64 RemainingRegionLength;
419 UINT64 *BlockEntry;
420 UINT64 *LastBlockEntry;
421 UINT64 BlockEntrySize;
422 UINTN TableLevel;
423
424 // Ensure the Length is aligned on 4KB boundary
425 if ((MemoryRegion->Length == 0) || ((MemoryRegion->Length & (SIZE_4KB - 1)) != 0)) {
426 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
427 return RETURN_INVALID_PARAMETER;
428 }
429
430 // Variable initialization
431 Attributes = ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF;
432 RemainingRegionLength = MemoryRegion->Length;
433 RegionStart = MemoryRegion->VirtualBase;
434
435 do {
436 // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
437 // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
438 BlockEntrySize = RemainingRegionLength;
439 BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);
440 if (BlockEntry == NULL) {
441 // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
442 return RETURN_OUT_OF_RESOURCES;
443 }
444
445 if (TableLevel != 3) {
446 Type = TT_TYPE_BLOCK_ENTRY;
447 } else {
448 Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;
449 }
450
451 do {
452 // Fill the Block Entry with attribute and output block address
453 *BlockEntry = (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;
454
455 // Go to the next BlockEntry
456 RegionStart += BlockEntrySize;
457 RemainingRegionLength -= BlockEntrySize;
458 BlockEntry++;
459
460 // Break the inner loop when next block is a table
461 // Rerun GetBlockEntryListFromAddress to avoid page table memory leak
462 if (TableLevel != 3 &&
463 (*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
464 break;
465 }
466 } while ((RemainingRegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));
467 } while (RemainingRegionLength != 0);
468
469 return RETURN_SUCCESS;
470 }
471
472 RETURN_STATUS
473 SetMemoryAttributes (
474 IN EFI_PHYSICAL_ADDRESS BaseAddress,
475 IN UINT64 Length,
476 IN UINT64 Attributes,
477 IN EFI_PHYSICAL_ADDRESS VirtualMask
478 )
479 {
480 RETURN_STATUS Status;
481 ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;
482 UINT64 *TranslationTable;
483
484 MemoryRegion.PhysicalBase = BaseAddress;
485 MemoryRegion.VirtualBase = BaseAddress;
486 MemoryRegion.Length = Length;
487 MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);
488
489 TranslationTable = ArmGetTTBR0BaseAddress ();
490
491 Status = FillTranslationTable (TranslationTable, &MemoryRegion);
492 if (RETURN_ERROR (Status)) {
493 return Status;
494 }
495
496 // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
497 // flush and invalidate pages
498 ArmCleanInvalidateDataCache ();
499
500 ArmInvalidateInstructionCache ();
501
502 // Invalidate all TLB entries so changes are synced
503 ArmInvalidateTlb ();
504
505 return RETURN_SUCCESS;
506 }
507
508 RETURN_STATUS
509 EFIAPI
510 ArmConfigureMmu (
511 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
512 OUT VOID **TranslationTableBase OPTIONAL,
513 OUT UINTN *TranslationTableSize OPTIONAL
514 )
515 {
516 VOID* TranslationTable;
517 UINTN TranslationTablePageCount;
518 UINT32 TranslationTableAttribute;
519 ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;
520 UINT64 MaxAddress;
521 UINT64 TopAddress;
522 UINTN T0SZ;
523 UINTN RootTableEntryCount;
524 UINT64 TCR;
525 RETURN_STATUS Status;
526
527 if(MemoryTable == NULL) {
528 ASSERT (MemoryTable != NULL);
529 return RETURN_INVALID_PARAMETER;
530 }
531
532 // Identify the highest address of the memory table
533 MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;
534 MemoryTableEntry = MemoryTable;
535 while (MemoryTableEntry->Length != 0) {
536 TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;
537 if (TopAddress > MaxAddress) {
538 MaxAddress = TopAddress;
539 }
540 MemoryTableEntry++;
541 }
542
543 // Lookup the Table Level to get the information
544 LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);
545
546 //
547 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
548 //
549 // Ideally we will be running at EL2, but should support EL1 as well.
550 // UEFI should not run at EL3.
551 if (ArmReadCurrentEL () == AARCH64_EL2) {
552 //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
553 TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
554
555 // Set the Physical Address Size using MaxAddress
556 if (MaxAddress < SIZE_4GB) {
557 TCR |= TCR_PS_4GB;
558 } else if (MaxAddress < SIZE_64GB) {
559 TCR |= TCR_PS_64GB;
560 } else if (MaxAddress < SIZE_1TB) {
561 TCR |= TCR_PS_1TB;
562 } else if (MaxAddress < SIZE_4TB) {
563 TCR |= TCR_PS_4TB;
564 } else if (MaxAddress < SIZE_16TB) {
565 TCR |= TCR_PS_16TB;
566 } else if (MaxAddress < SIZE_256TB) {
567 TCR |= TCR_PS_256TB;
568 } else {
569 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
570 ASSERT (0); // Bigger than 48-bit memory space are not supported
571 return RETURN_UNSUPPORTED;
572 }
573 } else if (ArmReadCurrentEL () == AARCH64_EL1) {
574 TCR = T0SZ | TCR_TG0_4KB;
575
576 // Set the Physical Address Size using MaxAddress
577 if (MaxAddress < SIZE_4GB) {
578 TCR |= TCR_IPS_4GB;
579 } else if (MaxAddress < SIZE_64GB) {
580 TCR |= TCR_IPS_64GB;
581 } else if (MaxAddress < SIZE_1TB) {
582 TCR |= TCR_IPS_1TB;
583 } else if (MaxAddress < SIZE_4TB) {
584 TCR |= TCR_IPS_4TB;
585 } else if (MaxAddress < SIZE_16TB) {
586 TCR |= TCR_IPS_16TB;
587 } else if (MaxAddress < SIZE_256TB) {
588 TCR |= TCR_IPS_256TB;
589 } else {
590 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
591 ASSERT (0); // Bigger than 48-bit memory space are not supported
592 return RETURN_UNSUPPORTED;
593 }
594 } else {
595 ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
596 return RETURN_UNSUPPORTED;
597 }
598
599 // Set TCR
600 ArmSetTCR (TCR);
601
602 // Allocate pages for translation table
603 TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64));
604 TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE);
605 if (TranslationTable == NULL) {
606 return RETURN_OUT_OF_RESOURCES;
607 }
608 // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
609 // functions without needing to pass this value across the functions. The MMU is only enabled
610 // after the translation tables are populated.
611 ArmSetTTBR0 (TranslationTable);
612
613 if (TranslationTableBase != NULL) {
614 *TranslationTableBase = TranslationTable;
615 }
616
617 if (TranslationTableSize != NULL) {
618 *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
619 }
620
621 ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
622
623 // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
624 ArmDisableMmu ();
625 ArmDisableDataCache ();
626 ArmDisableInstructionCache ();
627
628 // Make sure nothing sneaked into the cache
629 ArmCleanInvalidateDataCache ();
630 ArmInvalidateInstructionCache ();
631
632 TranslationTableAttribute = TT_ATTR_INDX_INVALID;
633 while (MemoryTable->Length != 0) {
634 // Find the memory attribute for the Translation Table
635 if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&
636 ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
637 TranslationTableAttribute = MemoryTable->Attributes;
638 }
639
640 Status = FillTranslationTable (TranslationTable, MemoryTable);
641 if (RETURN_ERROR (Status)) {
642 goto FREE_TRANSLATION_TABLE;
643 }
644 MemoryTable++;
645 }
646
647 // Translate the Memory Attributes into Translation Table Register Attributes
648 if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
649 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
650 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;
651 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
652 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
653 TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;
654 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
655 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
656 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;
657 } else {
658 // If we failed to find a mapping that contains the root translation table then it probably means the translation table
659 // is not mapped in the given memory map.
660 ASSERT (0);
661 Status = RETURN_UNSUPPORTED;
662 goto FREE_TRANSLATION_TABLE;
663 }
664
665 // Set again TCR after getting the Translation Table attributes
666 ArmSetTCR (TCR);
667
668 ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC
669 MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
670 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
671 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB
672
673 ArmDisableAlignmentCheck ();
674 ArmEnableInstructionCache ();
675 ArmEnableDataCache ();
676
677 ArmEnableMmu ();
678 return RETURN_SUCCESS;
679
680 FREE_TRANSLATION_TABLE:
681 FreePages (TranslationTable, TranslationTablePageCount);
682 return Status;
683 }
EFI Development Kit II mirror for PVE