Now that the AArch64 MMU code correctly identifies and handles
naturally aligned regions of more than 2 MB in size, it will happily
try to use block mappings at level 0 to map huge memory regions, such
as the single cacheable 1:1 mapping we use for Xen domU to map the
entire PA space. However, block mappings are not supported at level 0
so the resulting translation tables will be incorrect, causing
execution to fail as soon as the MMU is enabled.
So use level 1 as the minimum level at which to perform block
translations.
Reported-by: Julien Grall <julien.grall@citrix.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18568
6f19259b-4bc3-4df7-8a09-
765794883524
BaseAddressAlignment = LowBitSet64 (RegionStart);\r
}\r
\r
- // Identify the Page Level the RegionStart must belongs to\r
- PageLevel = 3 - ((BaseAddressAlignment - 12) / 9);\r
+ // Identify the Page Level the RegionStart must belong to. Note that PageLevel\r
+ // should be at least 1 since block translations are not supported at level 0\r
+ PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1);\r
\r
// If the required size is smaller than the current block size then we need to go to the page below.\r
// The PageLevel was calculated on the Base Address alignment but did not take in account the alignment\r