ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLibV8.h>
  17
  18 .text
  19 .align 3
  20
  21 GCC_ASM_EXPORT (ArmIsMpCore)
  22 GCC_ASM_EXPORT (ArmEnableAsynchronousAbort)
  23 GCC_ASM_EXPORT (ArmDisableAsynchronousAbort)
  24 GCC_ASM_EXPORT (ArmEnableIrq)
  25 GCC_ASM_EXPORT (ArmDisableIrq)
  26 GCC_ASM_EXPORT (ArmEnableFiq)
  27 GCC_ASM_EXPORT (ArmDisableFiq)
  28 GCC_ASM_EXPORT (ArmEnableInterrupts)
  29 GCC_ASM_EXPORT (ArmDisableInterrupts)
  30 GCC_ASM_EXPORT (ArmDisableAllExceptions)
  31 GCC_ASM_EXPORT (ReadCCSIDR)
  32 GCC_ASM_EXPORT (ReadCLIDR)
  33
  34 #------------------------------------------------------------------------------
  35
  36 .set MPIDR_U_BIT,    (30)
  37 .set MPIDR_U_MASK,   (1 << MPIDR_U_BIT)
  38
  39 // DAIF bit definitions for writing through msr daifclr/sr daifset
  40 .set DAIF_WR_FIQ_BIT,   (1 << 0)
  41 .set DAIF_WR_IRQ_BIT,   (1 << 1)
  42 .set DAIF_WR_ABORT_BIT, (1 << 2)
  43 .set DAIF_WR_DEBUG_BIT, (1 << 3)
  44 .set DAIF_WR_INT_BITS,  (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)
  45 .set DAIF_WR_ALL,       (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)
  46
  47
  48 ASM_PFX(ArmIsMpCore):
  49   mrs   x0, mpidr_el1         // Read EL1 Mutliprocessor Affinty Reg (MPIDR)
  50   and   x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system
  51   lsr   x0, x0, #MPIDR_U_BIT
  52   eor   x0, x0, #1
  53   ret
  54
  55
  56 ASM_PFX(ArmEnableAsynchronousAbort):
  57   msr   daifclr, #DAIF_WR_ABORT_BIT
  58   isb
  59   ret
  60
  61
  62 ASM_PFX(ArmDisableAsynchronousAbort):
  63   msr   daifset, #DAIF_WR_ABORT_BIT
  64   isb
  65   ret
  66
  67
  68 ASM_PFX(ArmEnableIrq):
  69   msr   daifclr, #DAIF_WR_IRQ_BIT
  70   isb
  71   ret
  72
  73
  74 ASM_PFX(ArmDisableIrq):
  75   msr   daifset, #DAIF_WR_IRQ_BIT
  76   isb
  77   ret
  78
  79
  80 ASM_PFX(ArmEnableFiq):
  81   msr   daifclr, #DAIF_WR_FIQ_BIT
  82   isb
  83   ret
  84
  85
  86 ASM_PFX(ArmDisableFiq):
  87   msr   daifset, #DAIF_WR_FIQ_BIT
  88   isb
  89   ret
  90
  91
  92 ASM_PFX(ArmEnableInterrupts):
  93   msr   daifclr, #DAIF_WR_INT_BITS
  94   isb
  95   ret
  96
  97
  98 ASM_PFX(ArmDisableInterrupts):
  99   msr   daifset, #DAIF_WR_INT_BITS
 100   isb
 101   ret
 102
 103
 104 ASM_PFX(ArmDisableAllExceptions):
 105   msr   daifset, #DAIF_WR_ALL
 106   isb
 107   ret
 108
 109
 110 // UINT32
 111 // ReadCCSIDR (
 112 //   IN UINT32 CSSELR
 113 //   )
 114 ASM_PFX(ReadCCSIDR):
 115   msr   csselr_el1, x0        // Write Cache Size Selection Register (CSSELR)
 116   isb
 117   mrs   x0, ccsidr_el1        // Read current Cache Size ID Register (CCSIDR)
 118   ret
 119
 120
 121 // UINT32
 122 // ReadCLIDR (
 123 //   IN UINT32 CSSELR
 124 //   )
 125 ASM_PFX(ReadCLIDR):
 126   mrs   x0, clidr_el1         // Read Cache Level ID Register
 127   ret
 128
 129 ASM_FUNCTION_REMOVE_IF_UNREFERENCED