ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
   5 //
   6 // SPDX-License-Identifier: BSD-2-Clause-Patent
   7 //
   8 //------------------------------------------------------------------------------
   9
  10     INCLUDE AsmMacroIoLib.inc
  11
  12
  13     INCLUDE AsmMacroExport.inc
  14
  15  RVCT_ASM_EXPORT ArmReadMidr
  16   mrc     p15,0,R0,c0,c0,0
  17   bx      LR
  18
  19  RVCT_ASM_EXPORT ArmCacheInfo
  20   mrc     p15,0,R0,c0,c0,1
  21   bx      LR
  22
  23  RVCT_ASM_EXPORT ArmGetInterruptState
  24   mrs     R0,CPSR
  25   tst     R0,#0x80      // Check if IRQ is enabled.
  26   moveq   R0,#1
  27   movne   R0,#0
  28   bx      LR
  29
  30  RVCT_ASM_EXPORT ArmGetFiqState
  31   mrs     R0,CPSR
  32   tst     R0,#0x40      // Check if FIQ is enabled.
  33   moveq   R0,#1
  34   movne   R0,#0
  35   bx      LR
  36
  37  RVCT_ASM_EXPORT ArmSetDomainAccessControl
  38   mcr     p15,0,r0,c3,c0,0
  39   bx      lr
  40
  41  RVCT_ASM_EXPORT CPSRMaskInsert
  42   stmfd   sp!, {r4-r12, lr} // save all the banked registers
  43   mov     r3, sp            // copy the stack pointer into a non-banked register
  44   mrs     r2, cpsr          // read the cpsr
  45   bic     r2, r2, r0        // clear mask in the cpsr
  46   and     r1, r1, r0        // clear bits outside the mask in the input
  47   orr     r2, r2, r1        // set field
  48   msr     cpsr_cxsf, r2     // write back cpsr (may have caused a mode switch)
  49   isb
  50   mov     sp, r3            // restore stack pointer
  51   ldmfd   sp!, {r4-r12, lr} // restore registers
  52   bx      lr                // return (hopefully thumb-safe!)             // return (hopefully thumb-safe!)
  53
  54  RVCT_ASM_EXPORT CPSRRead
  55   mrs     r0, cpsr
  56   bx      lr
  57
  58  RVCT_ASM_EXPORT ArmReadCpacr
  59   mrc     p15, 0, r0, c1, c0, 2
  60   bx      lr
  61
  62  RVCT_ASM_EXPORT ArmWriteCpacr
  63   mcr     p15, 0, r0, c1, c0, 2
  64   isb
  65   bx      lr
  66
  67  RVCT_ASM_EXPORT ArmWriteAuxCr
  68   mcr     p15, 0, r0, c1, c0, 1
  69   bx      lr
  70
  71  RVCT_ASM_EXPORT ArmReadAuxCr
  72   mrc     p15, 0, r0, c1, c0, 1
  73   bx      lr
  74
  75  RVCT_ASM_EXPORT ArmSetTTBR0
  76   mcr     p15,0,r0,c2,c0,0
  77   isb
  78   bx      lr
  79
  80  RVCT_ASM_EXPORT ArmSetTTBCR
  81   mcr     p15, 0, r0, c2, c0, 2
  82   isb
  83   bx      lr
  84
  85  RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress
  86   mrc     p15,0,r0,c2,c0,0
  87   MOV32   r1, 0xFFFFC000
  88   and     r0, r0, r1
  89   isb
  90   bx      lr
  91
  92 //
  93 //VOID
  94 //ArmUpdateTranslationTableEntry (
  95 //  IN VOID  *TranslationTableEntry  // R0
  96 //  IN VOID  *MVA                    // R1
  97 //  );
  98  RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry
  99   mcr     p15,0,R0,c7,c14,1     // DCCIMVAC Clean data cache by MVA
 100   dsb
 101   mcr     p15,0,R1,c8,c7,1      // TLBIMVA TLB Invalidate MVA
 102   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 103   dsb
 104   isb
 105   bx      lr
 106
 107  RVCT_ASM_EXPORT ArmInvalidateTlb
 108   mov     r0,#0
 109   mcr     p15,0,r0,c8,c7,0
 110   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 111   dsb
 112   isb
 113   bx      lr
 114
 115  RVCT_ASM_EXPORT ArmReadScr
 116   mrc     p15, 0, r0, c1, c1, 0
 117   bx      lr
 118
 119  RVCT_ASM_EXPORT ArmWriteScr
 120   mcr     p15, 0, r0, c1, c1, 0
 121   isb
 122   bx      lr
 123
 124  RVCT_ASM_EXPORT ArmReadHVBar
 125   mrc     p15, 4, r0, c12, c0, 0
 126   bx      lr
 127
 128  RVCT_ASM_EXPORT ArmWriteHVBar
 129   mcr     p15, 4, r0, c12, c0, 0
 130   bx      lr
 131
 132  RVCT_ASM_EXPORT ArmReadMVBar
 133   mrc     p15, 0, r0, c12, c0, 1
 134   bx      lr
 135
 136  RVCT_ASM_EXPORT ArmWriteMVBar
 137   mcr     p15, 0, r0, c12, c0, 1
 138   bx      lr
 139
 140  RVCT_ASM_EXPORT ArmCallWFE
 141   wfe
 142   bx      lr
 143
 144  RVCT_ASM_EXPORT ArmCallSEV
 145   sev
 146   bx      lr
 147
 148  RVCT_ASM_EXPORT ArmReadSctlr
 149   mrc     p15, 0, r0, c1, c0, 0      // Read SCTLR into R0 (Read control register configuration data)
 150   bx      lr
 151
 152  RVCT_ASM_EXPORT ArmWriteSctlr
 153   mcr     p15, 0, r0, c1, c0, 0
 154   bx      lr
 155
 156  RVCT_ASM_EXPORT ArmReadCpuActlr
 157   mrc     p15, 0, r0, c1, c0, 1
 158   bx      lr
 159
 160  RVCT_ASM_EXPORT ArmWriteCpuActlr
 161   mcr     p15, 0, r0, c1, c0, 1
 162   dsb
 163   isb
 164   bx      lr
 165
 166  RVCT_ASM_EXPORT ArmGetPhysicalAddressBits
 167   mrc     p15, 0, r0, c0, c1, 4   ; MMFR0
 168   and     r0, r0, #0xf            ; VMSA [3:0]
 169   cmp     r0, #5                  ; >= 5 implies LPAE support
 170   movlt   r0, #32                 ; 32 bits if no LPAE
 171   movge   r0, #40                 ; 40 bits if LPAE
 172   bx      lr
 173
 174   END