ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include <Chipset/ARM1176JZ-S.h>
  17 #include <Library/ArmLib.h>
  18 #include <Library/BaseMemoryLib.h>
  19 #include <Library/MemoryAllocationLib.h>
  20
  21 VOID
  22 FillTranslationTable (
  23   IN  UINT32                        *TranslationTable,
  24   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
  25   )
  26 {
  27   UINT32  *Entry;
  28   UINTN   Sections;
  29   UINTN   Index;
  30   UINT32  Attributes;
  31   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
  32
  33   switch (MemoryRegion->Attributes) {
  34     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
  35       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
  36       break;
  37     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
  38       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
  39       break;
  40     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
  41       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
  42       break;
  43     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
  44       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
  45       break;
  46     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
  47       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
  48       break;
  49     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
  50       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
  51       break;
  52     default:
  53       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
  54       break;
  55   }
  56
  57   Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
  58   Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
  59
  60   for (Index = 0; Index < Sections; Index++)
  61   {
  62     *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
  63     PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
  64   }
  65 }
  66
  67 RETURN_STATUS
  68 EFIAPI
  69 ArmConfigureMmu (
  70   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
  71   OUT VOID                         **TranslationTableBase OPTIONAL,
  72   OUT UINTN                         *TranslationTableSize OPTIONAL
  73   )
  74 {
  75   VOID  *TranslationTable;
  76
  77   // Allocate pages for translation table.
  78   TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
  79   if (TranslationTable == NULL) {
  80     return RETURN_OUT_OF_RESOURCES;
  81   }
  82   TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
  83
  84   if (TranslationTableBase != NULL) {
  85     *TranslationTableBase = TranslationTable;
  86   }
  87
  88   if (TranslationTableBase != NULL) {
  89     *TranslationTableSize = TRANSLATION_TABLE_SIZE;
  90   }
  91
  92   ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
  93
  94   ArmCleanInvalidateDataCache();
  95   ArmInvalidateInstructionCache();
  96   ArmInvalidateTlb();
  97
  98   ArmDisableDataCache();
  99   ArmDisableInstructionCache();
 100   ArmDisableMmu();
 101
 102   // Make sure nothing sneaked into the cache
 103   ArmCleanInvalidateDataCache();
 104   ArmInvalidateInstructionCache();
 105
 106   while (MemoryTable->Length != 0) {
 107     FillTranslationTable(TranslationTable, MemoryTable);
 108     MemoryTable++;
 109   }
 110
 111   ArmSetTTBR0(TranslationTable);
 112
 113   ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
 114                             DOMAIN_ACCESS_CONTROL_NONE(14) |
 115                             DOMAIN_ACCESS_CONTROL_NONE(13) |
 116                             DOMAIN_ACCESS_CONTROL_NONE(12) |
 117                             DOMAIN_ACCESS_CONTROL_NONE(11) |
 118                             DOMAIN_ACCESS_CONTROL_NONE(10) |
 119                             DOMAIN_ACCESS_CONTROL_NONE( 9) |
 120                             DOMAIN_ACCESS_CONTROL_NONE( 8) |
 121                             DOMAIN_ACCESS_CONTROL_NONE( 7) |
 122                             DOMAIN_ACCESS_CONTROL_NONE( 6) |
 123                             DOMAIN_ACCESS_CONTROL_NONE( 5) |
 124                             DOMAIN_ACCESS_CONTROL_NONE( 4) |
 125                             DOMAIN_ACCESS_CONTROL_NONE( 3) |
 126                             DOMAIN_ACCESS_CONTROL_NONE( 2) |
 127                             DOMAIN_ACCESS_CONTROL_NONE( 1) |
 128                             DOMAIN_ACCESS_CONTROL_MANAGER(0));
 129
 130   ArmEnableInstructionCache();
 131   ArmEnableDataCache();
 132   ArmEnableMmu();
 133
 134   return RETURN_SUCCESS;
 135 }