ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include <Chipset/ARM926EJ-S.h>
  17 #include <Library/ArmLib.h>
  18 #include <Library/BaseMemoryLib.h>
  19 #include <Library/MemoryAllocationLib.h>
  20 #include <Library/DebugLib.h>
  21
  22 VOID
  23 FillTranslationTable (
  24   IN  UINT32                        *TranslationTable,
  25   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
  26   )
  27 {
  28   UINT32  *Entry;
  29   UINTN   Sections;
  30   UINTN   Index;
  31   UINT32  Attributes;
  32   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
  33
  34   switch (MemoryRegion->Attributes) {
  35     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
  36       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
  37       break;
  38     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
  39       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
  40       break;
  41     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
  42       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
  43       break;
  44     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
  45     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
  46     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
  47       ASSERT(0); // Trustzone is not supported on ARMv5
  48     default:
  49       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
  50       break;
  51   }
  52
  53   Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
  54   Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
  55
  56   // The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
  57   ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
  58
  59   for (Index = 0; Index < Sections; Index++)
  60   {
  61     *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
  62     PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
  63   }
  64 }
  65
  66 RETURN_STATUS
  67 EFIAPI
  68 ArmConfigureMmu (
  69   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
  70   OUT VOID                         **TranslationTableBase OPTIONAL,
  71   OUT UINTN                         *TranslationTableSize OPTIONAL
  72   )
  73 {
  74   VOID  *TranslationTable;
  75
  76   // Allocate pages for translation table.
  77   TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
  78   if (TranslationTable == NULL) {
  79     return RETURN_OUT_OF_RESOURCES;
  80   }
  81   TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
  82
  83   if (TranslationTableBase != NULL) {
  84     *TranslationTableBase = TranslationTable;
  85   }
  86
  87   if (TranslationTableBase != NULL) {
  88     *TranslationTableSize = TRANSLATION_TABLE_SIZE;
  89   }
  90
  91   ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
  92
  93   ArmCleanInvalidateDataCache();
  94   ArmInvalidateInstructionCache();
  95   ArmInvalidateTlb();
  96
  97   ArmDisableDataCache();
  98   ArmDisableInstructionCache();
  99   ArmDisableMmu();
 100
 101   // Make sure nothing sneaked into the cache
 102   ArmCleanInvalidateDataCache();
 103   ArmInvalidateInstructionCache();
 104
 105   while (MemoryTable->Length != 0) {
 106     FillTranslationTable(TranslationTable, MemoryTable);
 107     MemoryTable++;
 108   }
 109
 110   ArmSetTTBR0(TranslationTable);
 111
 112   ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
 113                             DOMAIN_ACCESS_CONTROL_NONE(14) |
 114                             DOMAIN_ACCESS_CONTROL_NONE(13) |
 115                             DOMAIN_ACCESS_CONTROL_NONE(12) |
 116                             DOMAIN_ACCESS_CONTROL_NONE(11) |
 117                             DOMAIN_ACCESS_CONTROL_NONE(10) |
 118                             DOMAIN_ACCESS_CONTROL_NONE( 9) |
 119                             DOMAIN_ACCESS_CONTROL_NONE( 8) |
 120                             DOMAIN_ACCESS_CONTROL_NONE( 7) |
 121                             DOMAIN_ACCESS_CONTROL_NONE( 6) |
 122                             DOMAIN_ACCESS_CONTROL_NONE( 5) |
 123                             DOMAIN_ACCESS_CONTROL_NONE( 4) |
 124                             DOMAIN_ACCESS_CONTROL_NONE( 3) |
 125                             DOMAIN_ACCESS_CONTROL_NONE( 2) |
 126                             DOMAIN_ACCESS_CONTROL_NONE( 1) |
 127                             DOMAIN_ACCESS_CONTROL_MANAGER(0));
 128
 129   ArmEnableInstructionCache();
 130   ArmEnableDataCache();
 131   ArmEnableMmu();
 132
 133   return RETURN_SUCCESS;
 134 }