3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Chipset/ArmV7.h>
16 #include <Library/ArmLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/IoLib.h>
20 #include "ArmLibPrivate.h"
28 return ARM_CACHE_TYPE_WRITE_BACK
;
31 ARM_CACHE_ARCHITECTURE
33 ArmCacheArchitecture (
37 UINT32 CLIDR
= ReadCLIDR ();
39 return (ARM_CACHE_ARCHITECTURE
)CLIDR
; // BugBug Fix Me
48 UINT32 CLIDR
= ReadCLIDR ();
50 if ((CLIDR
& 0x2) == 0x2) {
51 // Instruction cache exists
54 if ((CLIDR
& 0x7) == 0x4) {
71 UINT32 CCSIDR
= ReadCCSIDR (0);
73 LineSize
= (1 << ((CCSIDR
& 0x7) + 2));
74 Associativity
= ((CCSIDR
>> 3) & 0x3ff) + 1;
75 NumSets
= ((CCSIDR
>> 13) & 0x7fff) + 1;
77 // LineSize is in words (4 byte chunks)
78 return NumSets
* Associativity
* LineSize
* 4;
83 ArmDataCacheAssociativity (
87 UINT32 CCSIDR
= ReadCCSIDR (0);
89 return ((CCSIDR
>> 3) & 0x3ff) + 1;
97 UINT32 CCSIDR
= ReadCCSIDR (0);
99 return ((CCSIDR
>> 13) & 0x7fff) + 1;
104 ArmDataCacheLineLength (
108 UINT32 CCSIDR
= ReadCCSIDR (0) & 7;
110 // * 4 converts to bytes
111 return (1 << (CCSIDR
+ 2)) * 4;
116 ArmInstructionCachePresent (
120 UINT32 CLIDR
= ReadCLIDR ();
122 if ((CLIDR
& 1) == 1) {
123 // Instruction cache exists
126 if ((CLIDR
& 0x7) == 0x4) {
136 ArmInstructionCacheSize (
141 UINT32 Associativity
;
143 UINT32 CCSIDR
= ReadCCSIDR (1);
145 LineSize
= (1 << ((CCSIDR
& 0x7) + 2));
146 Associativity
= ((CCSIDR
>> 3) & 0x3ff) + 1;
147 NumSets
= ((CCSIDR
>> 13) & 0x7fff) + 1;
149 // LineSize is in words (4 byte chunks)
150 return NumSets
* Associativity
* LineSize
* 4;
155 ArmInstructionCacheAssociativity (
159 UINT32 CCSIDR
= ReadCCSIDR (1);
161 return ((CCSIDR
>> 3) & 0x3ff) + 1;
167 ArmInstructionCacheSets (
171 UINT32 CCSIDR
= ReadCCSIDR (1);
173 return ((CCSIDR
>> 13) & 0x7fff) + 1;
178 ArmInstructionCacheLineLength (
182 UINT32 CCSIDR
= ReadCCSIDR (1) & 7;
184 // * 4 converts to bytes
185 return (1 << (CCSIDR
+ 2)) * 4;
192 ArmV7DataCacheOperation (
193 IN ARM_V7_CACHE_OPERATION DataCacheOperation
196 UINTN SavedInterruptState
;
198 SavedInterruptState
= ArmGetInterruptState ();
199 ArmDisableInterrupts ();
201 ArmV7AllDataCachesOperation (DataCacheOperation
);
203 ArmDrainWriteBuffer ();
205 if (SavedInterruptState
) {
206 ArmEnableInterrupts ();
212 ArmV7PoUDataCacheOperation (
213 IN ARM_V7_CACHE_OPERATION DataCacheOperation
216 UINTN SavedInterruptState
;
218 SavedInterruptState
= ArmGetInterruptState ();
219 ArmDisableInterrupts ();
221 ArmV7PerformPoUDataCacheOperation (DataCacheOperation
);
223 ArmDrainWriteBuffer ();
225 if (SavedInterruptState
) {
226 ArmEnableInterrupts ();
232 ArmInvalidateDataCache (
236 ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay
);
241 ArmCleanInvalidateDataCache (
245 ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay
);
254 ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay
);
259 ArmCleanDataCacheToPoU (
263 ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay
);