ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15 #include <Uefi.h>
  16 #include <Chipset/ArmV7.h>
  17 #include <Library/ArmLib.h>
  18 #include <Library/BaseLib.h>
  19 #include <Library/IoLib.h>
  20 #include "ArmV7Lib.h"
  21 #include "ArmLibPrivate.h"
  22
  23 ARM_CACHE_TYPE
  24 EFIAPI
  25 ArmCacheType (
  26   VOID
  27   )
  28 {
  29   return ARM_CACHE_TYPE_WRITE_BACK;
  30 }
  31
  32 ARM_CACHE_ARCHITECTURE
  33 EFIAPI
  34 ArmCacheArchitecture (
  35   VOID
  36   )
  37 {
  38   UINT32 CLIDR = ReadCLIDR ();
  39
  40   return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
  41 }
  42
  43 BOOLEAN
  44 EFIAPI
  45 ArmDataCachePresent (
  46   VOID
  47   )
  48 {
  49   UINT32 CLIDR = ReadCLIDR ();
  50
  51   if ((CLIDR & 0x2) == 0x2) {
  52     // Instruction cache exists
  53     return TRUE;
  54   }
  55   if ((CLIDR & 0x7) == 0x4) {
  56     // Unified cache
  57     return TRUE;
  58   }
  59
  60   return FALSE;
  61 }
  62
  63 UINTN
  64 EFIAPI
  65 ArmDataCacheSize (
  66   VOID
  67   )
  68 {
  69   UINT32 NumSets;
  70   UINT32 Associativity;
  71   UINT32 LineSize;
  72   UINT32 CCSIDR = ReadCCSIDR (0);
  73
  74   LineSize      = (1 << ((CCSIDR & 0x7) + 2));
  75   Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
  76   NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
  77
  78   // LineSize is in words (4 byte chunks)
  79   return  NumSets * Associativity * LineSize * 4;
  80 }
  81
  82 UINTN
  83 EFIAPI
  84 ArmDataCacheAssociativity (
  85   VOID
  86   )
  87 {
  88   UINT32 CCSIDR = ReadCCSIDR (0);
  89
  90   return ((CCSIDR >> 3) & 0x3ff) + 1;
  91 }
  92
  93 UINTN
  94 ArmDataCacheSets (
  95   VOID
  96   )
  97 {
  98   UINT32 CCSIDR = ReadCCSIDR (0);
  99
 100   return ((CCSIDR >> 13) & 0x7fff) + 1;
 101 }
 102
 103 UINTN
 104 EFIAPI
 105 ArmDataCacheLineLength (
 106   VOID
 107   )
 108 {
 109   UINT32 CCSIDR = ReadCCSIDR (0) & 7;
 110
 111   // * 4 converts to bytes
 112   return (1 << (CCSIDR + 2)) * 4;
 113 }
 114
 115 BOOLEAN
 116 EFIAPI
 117 ArmInstructionCachePresent (
 118   VOID
 119   )
 120 {
 121   UINT32 CLIDR = ReadCLIDR ();
 122
 123   if ((CLIDR & 1) == 1) {
 124     // Instruction cache exists
 125     return TRUE;
 126   }
 127   if ((CLIDR & 0x7) == 0x4) {
 128     // Unified cache
 129     return TRUE;
 130   }
 131
 132   return FALSE;
 133 }
 134
 135 UINTN
 136 EFIAPI
 137 ArmInstructionCacheSize (
 138   VOID
 139   )
 140 {
 141   UINT32 NumSets;
 142   UINT32 Associativity;
 143   UINT32 LineSize;
 144   UINT32 CCSIDR = ReadCCSIDR (1);
 145
 146   LineSize      = (1 << ((CCSIDR & 0x7) + 2));
 147   Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
 148   NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
 149
 150   // LineSize is in words (4 byte chunks)
 151   return  NumSets * Associativity * LineSize * 4;
 152 }
 153
 154 UINTN
 155 EFIAPI
 156 ArmInstructionCacheAssociativity (
 157   VOID
 158   )
 159 {
 160   UINT32 CCSIDR = ReadCCSIDR (1);
 161
 162   return ((CCSIDR >> 3) & 0x3ff) + 1;
 163 //  return 4;
 164 }
 165
 166 UINTN
 167 EFIAPI
 168 ArmInstructionCacheSets (
 169   VOID
 170   )
 171 {
 172   UINT32 CCSIDR = ReadCCSIDR (1);
 173
 174   return ((CCSIDR >> 13) & 0x7fff) + 1;
 175 }
 176
 177 UINTN
 178 EFIAPI
 179 ArmInstructionCacheLineLength (
 180   VOID
 181   )
 182 {
 183   UINT32 CCSIDR = ReadCCSIDR (1) & 7;
 184
 185   // * 4 converts to bytes
 186   return (1 << (CCSIDR + 2)) * 4;
 187
 188 //  return 64;
 189 }
 190
 191
 192 VOID
 193 ArmV7DataCacheOperation (
 194   IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
 195   )
 196 {
 197   UINTN     SavedInterruptState;
 198
 199   SavedInterruptState = ArmGetInterruptState ();
 200   ArmDisableInterrupts ();
 201
 202   ArmV7AllDataCachesOperation (DataCacheOperation);
 203
 204   ArmDrainWriteBuffer ();
 205
 206   if (SavedInterruptState) {
 207     ArmEnableInterrupts ();
 208   }
 209 }
 210
 211
 212 VOID
 213 ArmV7PoUDataCacheOperation (
 214   IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
 215   )
 216 {
 217   UINTN     SavedInterruptState;
 218
 219   SavedInterruptState = ArmGetInterruptState ();
 220   ArmDisableInterrupts ();
 221
 222   ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
 223
 224   ArmDrainWriteBuffer ();
 225
 226   if (SavedInterruptState) {
 227     ArmEnableInterrupts ();
 228   }
 229 }
 230
 231 VOID
 232 EFIAPI
 233 ArmInvalidateDataCache (
 234   VOID
 235   )
 236 {
 237   ArmDrainWriteBuffer ();
 238   ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
 239 }
 240
 241 VOID
 242 EFIAPI
 243 ArmCleanInvalidateDataCache (
 244   VOID
 245   )
 246 {
 247   ArmDrainWriteBuffer ();
 248   ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
 249 }
 250
 251 VOID
 252 EFIAPI
 253 ArmCleanDataCache (
 254   VOID
 255   )
 256 {
 257   ArmDrainWriteBuffer ();
 258   ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
 259 }
 260
 261 VOID
 262 EFIAPI
 263 ArmCleanDataCacheToPoU (
 264   VOID
 265   )
 266 {
 267   ArmDrainWriteBuffer ();
 268   ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
 269 }