ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 .text
  17 .align 2
  18
  19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  21 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  22 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  26 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
  27 GCC_ASM_EXPORT (ArmEnableMmu)
  28 GCC_ASM_EXPORT (ArmDisableMmu)
  29 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  30 GCC_ASM_EXPORT (ArmMmuEnabled)
  31 GCC_ASM_EXPORT (ArmEnableDataCache)
  32 GCC_ASM_EXPORT (ArmDisableDataCache)
  33 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  34 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  35 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
  36 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  37 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  38 GCC_ASM_EXPORT (ArmSetLowVectors)
  39 GCC_ASM_EXPORT (ArmSetHighVectors)
  40 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
  41 GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)
  42 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  43 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
  44 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  45 GCC_ASM_EXPORT (ArmReadVBar)
  46 GCC_ASM_EXPORT (ArmWriteVBar)
  47 GCC_ASM_EXPORT (ArmEnableVFP)
  48 GCC_ASM_EXPORT (ArmCallWFI)
  49 GCC_ASM_EXPORT (ArmReadCbar)
  50 GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
  51 GCC_ASM_EXPORT (ArmReadMpidr)
  52 GCC_ASM_EXPORT (ArmReadTpidrurw)
  53 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  54 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  55 GCC_ASM_EXPORT (ArmReadIdPfr1)
  56
  57 .set DC_ON, (0x1<<2)
  58 .set IC_ON, (0x1<<12)
  59 .set CTRL_M_BIT,  (1 << 0)
  60 .set CTRL_C_BIT,  (1 << 2)
  61 .set CTRL_B_BIT,  (1 << 7)
  62 .set CTRL_I_BIT,  (1 << 12)
  63
  64
  65 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  66   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  67   dsb
  68   isb
  69   bx      lr
  70
  71 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  72   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  73   dsb
  74   isb
  75   bx      lr
  76
  77
  78 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  79   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  80   dsb
  81   isb
  82   bx      lr
  83
  84
  85 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  86   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  87   dsb
  88   isb
  89   bx      lr
  90
  91
  92 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  93   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  94   dsb
  95   isb
  96   bx      lr
  97
  98
  99 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
 100   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
 101   dsb
 102   isb
 103   bx      lr
 104
 105 ASM_PFX(ArmInvalidateInstructionCache):
 106   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
 107   dsb
 108   isb
 109   bx      LR
 110
 111 ASM_PFX(ArmEnableMmu):
 112   mrc     p15,0,R0,c1,c0,0
 113   orr     R0,R0,#1
 114   mcr     p15,0,R0,c1,c0,0
 115   dsb
 116   isb
 117   bx      LR
 118
 119
 120 ASM_PFX(ArmDisableMmu):
 121   mrc     p15,0,R0,c1,c0,0
 122   bic     R0,R0,#1
 123   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 124
 125   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
 126   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 127   dsb
 128   isb
 129   bx      LR
 130
 131 ASM_PFX(ArmDisableCachesAndMmu):
 132   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
 133   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
 134   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
 135   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
 136   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
 137   dsb
 138   isb
 139   bx      LR
 140
 141 ASM_PFX(ArmMmuEnabled):
 142   mrc     p15,0,R0,c1,c0,0
 143   and     R0,R0,#1
 144   bx      LR
 145
 146 ASM_PFX(ArmEnableDataCache):
 147   ldr     R1,=DC_ON
 148   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 149   orr     R0,R0,R1              @Set C bit
 150   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 151   dsb
 152   isb
 153   bx      LR
 154
 155 ASM_PFX(ArmDisableDataCache):
 156   ldr     R1,=DC_ON
 157   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 158   bic     R0,R0,R1              @Clear C bit
 159   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 160   dsb
 161   isb
 162   bx      LR
 163
 164 ASM_PFX(ArmEnableInstructionCache):
 165   ldr     R1,=IC_ON
 166   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 167   orr     R0,R0,R1              @Set I bit
 168   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 169   dsb
 170   isb
 171   bx      LR
 172
 173 ASM_PFX(ArmDisableInstructionCache):
 174   ldr     R1,=IC_ON
 175   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 176   bic     R0,R0,R1              @Clear I bit.
 177   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 178   dsb
 179   isb
 180   bx      LR
 181
 182 ASM_PFX(ArmEnableSWPInstruction):
 183   mrc     p15, 0, r0, c1, c0, 0
 184   orr     r0, r0, #0x00000400
 185   mcr     p15, 0, r0, c1, c0, 0
 186   isb
 187   bx      LR
 188
 189 ASM_PFX(ArmEnableBranchPrediction):
 190   mrc     p15, 0, r0, c1, c0, 0
 191   orr     r0, r0, #0x00000800
 192   mcr     p15, 0, r0, c1, c0, 0
 193   dsb
 194   isb
 195   bx      LR
 196
 197 ASM_PFX(ArmDisableBranchPrediction):
 198   mrc     p15, 0, r0, c1, c0, 0
 199   bic     r0, r0, #0x00000800
 200   mcr     p15, 0, r0, c1, c0, 0
 201   dsb
 202   isb
 203   bx      LR
 204
 205 ASM_PFX(ArmSetLowVectors):
 206   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 207   bic     r0, r0, #0x00002000   @ clear V bit
 208   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 209   isb
 210   bx      LR
 211
 212 ASM_PFX(ArmSetHighVectors):
 213   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 214   orr     r0, r0, #0x00002000   @ Set V bit
 215   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 216   isb
 217   bx      LR
 218
 219 ASM_PFX(ArmV7AllDataCachesOperation):
 220   stmfd SP!,{r4-r12, LR}
 221   mov   R1, R0                @ Save Function call in R1
 222   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 223   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 224   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 225   beq   L_Finished
 226   mov   R10, #0
 227
 228 Loop1:
 229   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 230   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 231   and   R12, R12, #7          @ get those 3 bits alone
 232   cmp   R12, #2
 233   blt   L_Skip                  @ no cache or only instruction cache at this level
 234   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 235   isb                           @ isb to sync the change to the CacheSizeID reg
 236   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 237   and   R2, R12, #0x7           @ extract the line length field
 238   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 239 @  ldr   R4, =0x3FF
 240   mov   R4, #0x400
 241   sub   R4, R4, #1
 242   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 243   clz   R5, R4                  @ R5 is the bit position of the way size increment
 244 @  ldr   R7, =0x00007FFF
 245   mov   R7, #0x00008000
 246   sub   R7, R7, #1
 247   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 248
 249 Loop2:
 250   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 251
 252 Loop3:
 253   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 254   orr   R0, R0, R7, LSL R2      @ factor in the index number
 255
 256   blx   R1
 257
 258   subs  R9, R9, #1              @ decrement the way number
 259   bge   Loop3
 260   subs  R7, R7, #1              @ decrement the index
 261   bge   Loop2
 262 L_Skip:
 263   add   R10, R10, #2            @ increment the cache number
 264   cmp   R3, R10
 265   bgt   Loop1
 266
 267 L_Finished:
 268   dsb
 269   ldmfd SP!, {r4-r12, lr}
 270   bx    LR
 271
 272 ASM_PFX(ArmV7PerformPoUDataCacheOperation):
 273   stmfd SP!,{r4-r12, LR}
 274   mov   R1, R0                @ Save Function call in R1
 275   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 276   ands  R3, R6, #0x38000000    @ Mask out all but Level of Unification (LoU)
 277   mov   R3, R3, LSR #26       @ Cache level value (naturally aligned)
 278   beq   Finished2
 279   mov   R10, #0
 280
 281 Loop4:
 282   add   R2, R10, R10, LSR #1    @ Work out 3xcachelevel
 283   mov   R12, R6, LSR R2         @ bottom 3 bits are the Cache type for this level
 284   and   R12, R12, #7            @ get those 3 bits alone
 285   cmp   R12, #2
 286   blt   Skip2                   @ no cache or only instruction cache at this level
 287   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 288   isb                           @ isb to sync the change to the CacheSizeID reg
 289   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 290   and   R2, R12, #0x7            @ extract the line length field
 291   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 292   ldr   R4, =0x3FF
 293   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 294   clz   R5, R4                  @ R5 is the bit position of the way size increment
 295   ldr   R7, =0x00007FFF
 296   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 297
 298 Loop5:
 299   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 300
 301 Loop6:
 302   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 303   orr   R0, R0, R7, LSL R2      @ factor in the index number
 304
 305   blx   R1
 306
 307   subs  R9, R9, #1              @ decrement the way number
 308   bge   Loop6
 309   subs  R7, R7, #1              @ decrement the index
 310   bge   Loop5
 311 Skip2:
 312   add   R10, R10, #2            @ increment the cache number
 313   cmp   R3, R10
 314   bgt   Loop4
 315
 316 Finished2:
 317   dsb
 318   ldmfd SP!, {r4-r12, lr}
 319   bx    LR
 320
 321 ASM_PFX(ArmDataMemoryBarrier):
 322   dmb
 323   bx      LR
 324
 325 ASM_PFX(ArmDataSyncronizationBarrier):
 326 ASM_PFX(ArmDrainWriteBuffer):
 327   dsb
 328   bx      LR
 329
 330 ASM_PFX(ArmInstructionSynchronizationBarrier):
 331   isb
 332   bx      LR
 333
 334 ASM_PFX(ArmReadVBar):
 335   # Set the Address of the Vector Table in the VBAR register
 336   mrc     p15, 0, r0, c12, c0, 0
 337   bx      lr
 338
 339 ASM_PFX(ArmWriteVBar):
 340   # Set the Address of the Vector Table in the VBAR register
 341   mcr     p15, 0, r0, c12, c0, 0
 342   # Ensure the SCTLR.V bit is clear
 343   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 344   bic     r0, r0, #0x00002000   @ clear V bit
 345   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 346   isb
 347   bx      lr
 348
 349 ASM_PFX(ArmEnableVFP):
 350   # Read CPACR (Coprocessor Access Control Register)
 351   mrc     p15, 0, r0, c1, c0, 2
 352   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 353   orr     r0, r0, #0x00f00000
 354   # Write back CPACR (Coprocessor Access Control Register)
 355   mcr     p15, 0, r0, c1, c0, 2
 356   isb
 357   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 358   mov     r0, #0x40000000
 359   mcr     p10,#0x7,r0,c8,c0,#0
 360   bx      lr
 361
 362 ASM_PFX(ArmCallWFI):
 363   wfi
 364   bx      lr
 365
 366 #Note: Return 0 in Uniprocessor implementation
 367 ASM_PFX(ArmReadCbar):
 368   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 369   bx      lr
 370
 371 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
 372   mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB
 373   dsb
 374   bx lr
 375
 376 ASM_PFX(ArmReadMpidr):
 377   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 378   bx      lr
 379
 380 ASM_PFX(ArmReadTpidrurw):
 381   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 382   bx      lr
 383
 384 ASM_PFX(ArmWriteTpidrurw):
 385   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 386   bx      lr
 387
 388 ASM_PFX(ArmIsArchTimerImplemented):
 389   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 390   and    r0, r0, #0x000F0000
 391   bx     lr
 392
 393 ASM_PFX(ArmReadIdPfr1):
 394   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 395   bx     lr
 396
 397 ASM_FUNCTION_REMOVE_IF_UNREFERENCED